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  • A new miniaturized Electronic Pill (ePille) for mass medical application with bi-directional communication system Nidal Fawaz, Dirk Jansen Institute for Applied Research, Offenburg, Germany

    Abstract A new electronic capsule with bidirectional communication system is being developed for multi-task application. The capsule is designed to be a platform for medical assistant application inside the body. The designed telemetry unit is a synchronous bidirectional communication block using continuous phase DQPSK of 115 kHz low carrier frequency for inductive data transmission suited for human body energy transfer. The communication system can assist the electronic pill to trigger an actuator for drug delivery, to record temperature, or to measure pH of the body. It consists additionally to a 32bit processor, memory, external peripheries, and detection facility. The complete system is designed to fit small-size mass medical application with low power consumption, size of 7x25mm. The system is designed, simulated and emulated on FPGA. A final layout of the complete chip design is still under progress.

    1 Introduction Medical diagnosis and treatment are growing rapidly in recent years. Need of communication systems for telemetry and wireless access are expanding widely in this field. Systems known as smart pills, electronic digestible capsules and intelligent microsystems are becoming more realistic for treatment of several diseases (cancer, diabetes, ) and carrying out biomedical analysis in GI tract (temperature, pH, motility, ), GI diseases affect 60-70 million people annually while diagnosis and treatment exceed 10 Billion Euro per year. In 1957, Mackay invented the first radio telemetry capsule with one transistor, since then research and developments are carried out to produce more complicated systems that perform sophisticated biomedical treatment and analysis, such electronic systems termed by Lab-on-chip, pharmacy-on-chip, Biochips and BioMEMS are used to describe the recent modern capsules. This paper describes a developed platform of an electronic pill (ePille) to run out multi-purpose application related to medical field by establishing telemetry channel from-to the body.

    2 Electronic Pill Design Figure 1 shows the concept of the electronic pill (ePille), it is designed to: - Establish bi-directional communication channel. - Trigger an actuator for drug delivery. - Record temperature or pH value via temperature

    sensor or other chemical sensor. - Localization attempt using near field magnetic

    induction method within 20 cm circular range and 1 cm resolution.

    Figure 1 ePille concept

    2.1 Communication Block

    The communication block consists of an asynchronous DQPSK with 115 KHz carrier frequency, including a digital PLL at the receiver side. The data rate is 9600 Baud. The modulation technique is a continuous phase soft shift keying using Gaussian filter for smooth phase transition from one state to the other. The data frame package carries up to 255 bytes of data information with preamble and 16 bit CRC sum check. The system includes 4B/5B coding for 1 and 2 bit error detection as well burst error for frames less than 16 bits. Communication will be used for: - Actuating command for release of medicine. - Retrieve temperature data from the pill. - External control over standby or active mode for

    power reduction consumption. - Use of the transmitted signal for position

    detection. The complete digital system is designed using VHDL programming language.

  • 2.2 Modulator

    Figure 2 Flow diagram of the modulator

    Figure 2 shows the design flow of the modulator block. The serial data getting to the modulator block are converted into two parallel bit for quadrature form. A differential encoding is set to eliminate the difference of phase reference between the transmitter and receiver side. A soft shift keying is provided by Gaussian filtering for smooth phase transition. This signal is supplied to a numerically controlled oscillator (NCO) to generate a frequency between 107-123kHz depending on the phase shift.

    2.2.1 DQPSK Converter

    Figure 3 Differential encoding

    Differential Encoding eliminates the problem of rota-tional invariant multiples of pi/2, which the receiver cannot detect the actual phase reference. The informa-tion is encoded by the change in constellation position between symbols rather than absolute position. The IS-54 standard for digital cellular radio in North America transmits two bits per symbol as a form of Quadrature PSK. These two bits are not associated with four phases but with eight equally spaced phases as shown in figure 3.

    2.2.2 Soft Shift Keying

    (KHz)

    123- 122- 121- 120- 119- 118- 117- 116- 115

    0 52 104 156 208 (s)

    Figure 4 Gaussian filter

    A Gaussian filter is used to carry out the smooth transition from one phase to another; the instantaneous frequency is defined as the frequency that is present at a particular instant of time as shown in figure 4:

    [ ])(21)( ttw

    dtd

    tf ci pi +=

    (1) and the frequency deviation is:

    ==

    dttdftftf cid )(2

    1)()( pi

    (2)

    The phase-time relation using the Gaussian filter is described as follows:

    2

    2

    1

    2

    )(

    +=

    K

    Tt

    ci

    symbol

    eKftf

    (3)

    dteKtt K

    Tt symbol

    =

    2

    2

    1

    2

    2)( pi

    (4)

    A closed form of the Gaussian integration function does not exist; math tables or numerical integration techniques must be used to evaluate it. A definition for that is the Error function erf(x) or Q function, they are used to replace the integration form and they are known as the cumulative distribution function (CDF) for the Gaussian distribution :

    [ ])(cos)( terfKtwAtv c += (5) Table 1. Gaussian Filter Coefficients

    Coeff. +45 +135 b0 5 0000101 15 000001111 b1 13 0001101 40 000101000 b2 30 0011110 90 001011010 b3 56 0111000 169 010101001 b4 89 1011001 265 100001001 b5 116 1110100 348 101011100 b6 126 1111110 380 101111100

    135

    180 0

    90

    270

    315

    45

    225

  • The coefficients of the filter are listed in table 1. The NCO generates the modulated signal in the time domain using the following equation:

    = pi2

    2)(

    sin)( 20noutput

    nv NCO

    (6)

    2.3 Demodulator

    Figure 5 Design flow of the demodulator

    Figure 5 shows the design flow of the demodulator block which contains the reverse steps of the modulator. It consists of Schmitt-trigger for digitizing the received analog signal, a digital PLL to lock the received signal, a decision circuit to estimate the symbol value, a decoder and parallel-serial converter to recover the original data.

    2.3.1 Digital Phase Locked Loop (DPLL)

    Figure 6 Design of the digital PLL

    The task of the digital phase lock loop (PLL) is to reconstruct the transmitted signal from the digital bit stream of the received signal. The reference frequency of the PLL is 115 kHz.

    0 1 2 3 4 5 (ms)

    Figure 7 Simulation result of the transient behavior

    Figures 6 and 7 show the design of the digital PLL and its transient behavior.

    2.3.2 Decision Circuit

    The decision circuit integrates the area under the curve after the PLL output, the value of the integration will be compared to a LUT where the ranges of the four different symbols are defined. A FIR filter is additionally used to reconstruct the symbol clock to synchronize the symbol rate. The FIR filter is used as a differentiator to detect the sign change of the first order derivation that occurred at the middle of the symbol.

    0 52 104 156 208 (s)

    Figure 8 Simulation result of the eye-diagram

    The eye diagrams simulation of the demodulated signal is shown in figure 8.

    3 Hardware Emulation and Layout

    Figure 9 Emulation of the system on Cyclone II

    The communication block has been emulated on FPGA Cyclone II, an emulation test board was designed to test the systems functionality as shown in figure 9.

    Emulation test board built on FPGA board

  • A single coil was used for transmission and receiving mode. A serial combination of the coil, capacitor, and resistor were used for transmission mode while a parallel combination of the coil, capacitor, and resistor were used for receiving mode. The Q factor is around seven and the bandwidth is 16 kHz with center frequency of 115 kHz.

    Figure 10 First layout of the ASIC in 0.35 m AMIS technology, size of 14mm

    A first routing of the SoC circuit was done. A proces-sor, SRAM, external periphery, and communication block were routed using 0.35m AMIS technology. The first routings showed an area of 14mm (4 x 3.5 mm) as seen in figure 10.

    4 Summary and Conclusion A complete bidirectional system was designed, simulated, and emulated on FPGA. A first routing prototype for the digital part was done using 0.35m AMIS technology. A final layout with complete peripheries and analog components is still under progress. The system contains wake up manager unit for reduction of power consumption. An external signal will be sent either to wake up the system or shift it to standby mode. The system was able to demodulate receiving signal, CRC check sum and save the data in the memory. A transparent mode to resend the data was achieved. The system could trigger an actuator via transmitted command. A first complete prototype is still under progress.

    5 References [1] N. Fawaz, D. Jansen, M. Mogel: Entwicklung

    eines synchronen Transceivers mit DQPSK Mo-dulation und Soft Shift Keying fr eine induktive bertragung mit Erprobung in einem FPGA, MPC-Workshop, Germany, 2006.

    [2] N. Fawaz, Development of CP-DQPSK Modulator and Demodulator using VHDL for inductive data transmission, Master thesis FH-Offenburg, Germany, 2002.

    [3] N. Fawaz, D. Jansen, DQPSK Modulator for Inductive Data Transmission, MPC-Workshop, Germany, 2002.

    [4] Dirk Jansen et. alt.: Electronic Design Automation Handbook, Verlag Kluwer, NL, 2003.

    [5] C. Eichner, FHOP-Evalboard Technischer Bericht, FH-Offenburg, Germany, 2002.

    [6] D. Jansen, F. Baier, Induktive bidirektionale Schnittstelle hnlich ISO/IEC 14443-A, MPC-Workshop, Germany, 2002.

    [7] D. Jansen, Systematic Design of a Small Processor Core with C-Capability for SOC Designs; Presentation on the colloquium of the CECS, University of California, USA, 2005.

    [8] D. Jansen, Handbook der Electronic Design Automation, Hanser, Germany, 2002.