CAPS project-team Compilation et Architectures pour Processeurs Superscalaires et Spécialisés.

CAPS project-team

Compilation et Architectures pour Processeurs Superscalaires et Spécialisés

2André Seznec

CAPS project-teamIrisa-Inria

History of CAPS project-team

Created in 1994: “Compiler Parallel Architectures and Systems” Common focus:

high performance through optimizing the memory hierarchy

January 2000: split in PARIS and “historical canal” CAPS “historical canal” CAPS:

• Mainly compiler and architecture for uniprocessor• CAPS was renamed, but the acronym was conserved

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CAPS themes

Two main interacting activities

microprocessor architecture

• High performance

• Migrating high performance concepts to embedded

systems

Performance oriented compilation:

• High performance

• Embedded processors

+ Recently: Worst case execution time analysis

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CAPS « missions »

Defining the tradeoffs between:

what should be done through hardware

what can be done by the compiler

for maximum performance

or for minimum cost

or for minimum size, power ..

to guarantee in-time execution

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Issues on high performance processor architecture

Memory hierarchy management: 1 cycle L1 – 10 cycles L2 – 30 cycles L3 – 200 cycles memory

Branch prediction : 30 cycles penalty x N instructions per cycle Single cycle next instruction block address generation ?

Complexity quadratic with issue width: Register file, bypass network, issue logic

Single chip hardware thread parallelism is available: How do we exploit it ?

Understanding/predicting execution time Power management, temperature management

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Issues on code generation/software environments for embedded processors

ILP, caches are entering embedded processor world Code generation must manage them

Binary compatibility is not critical, time-to-market is critical Retargetable platforms are wanted:

• ISAs, architecture

Performance is not the only ultimate goal: Code size/ performance Power/ performance System cost/ performance WCET

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CAPS project-team composition Sept. 2005

Core team:

A. Seznec, DR INRIA

F. Bodin, Pr Rennes I

P. Michaud, CR INRIA

I. Puaut, Pr Rennes I

Honorary member:

J. Lenfant, ex-president Rennes I

Ph. D students:

0. Rochecouste, E. Toullec,

A. Arnaud, J.F. Deverge,

D. Fetis, T. Piquet, E. Petit

Post-doc : He Liqiang (arriving 09-

2005) Engineer:

J. Fouriaux

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Scientific contributions (1)Processor architecture

Global history branch predictors and instruction fetch front-end 2bcgskew used in Compaq EV8 Pipelining the I-fetch front end O-GEHL branch predictor

Limiting hardware complexity on superscalar processors Dataflow prescheduling: instruction window WSRS architecture: register file, bypass network and issue logic

Thread parallelism and single chip parallelism: CASH: CMP and SMT hybrid Execution migration: single thread on a multicore, to use all the cache

space

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Scientific contributions (2)architecture/compiler interaction

ISA simulation: ABSCISS: ISA and architecture retargetable high speed simulator

for VLIW processor IATO: simulation of out-of-order execution IA64

Low power and architecture configurability: Cache reconfiguration at software level on phase basis Hardware/software speculative management of data path and

register file width

SWARP: retargetable C-to-C preprocessor to enhance multimedia instruction use

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Scientific contributions (3)compiler and software environments

Artificial intelligence in performance tuning CAHT: case based reasoning for assisting performance tuning Automatic derivation of compiler heuristics: using

machine learning to derive compiler heuristics

Performance code size tradeoffs: Iterative compilation Mixing interpretation on compressed code and native

execution

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Scientific contributions (4)unpredictable random number generation

HAVEGE: HArdware Volatile Entropy Gathering and Expansion

• Combining entropy gathering on non-architectural hardware states of a microprocessor with pseudo-random number generation

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Direct technology transfers

A. Seznec’s sabbatical with Compaq Alpha Development group (1999-2000): EV8 branch predictor directly issued from CAPS project-team

researches Parallel access scheme to strided vectors in caches in Tarantula

vector processor project directly derived from “old” vector CAPS background

P. Michaud’s sabbatical with Intel (2001-2002): Covered by NDA

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Industrially funded Ph. Ds

3 CIFRE Ph. D. fellowships with STmicroelectronics (ended 2004) Flexible infrastructure for code scheduling and optimization Compilation and power consumption Thread extraction for heterogeneous embedded systems

1 CIFRE Ph. D. fellowship with Thomson MMD (ended 2004) Code analysis and performance evaluation for embedded systems

2 Ph. D. fellowships funded through Intel donation: WSRS architecture Pipelined instruction fetch L2 cache management

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Institutionally funded projects

EPICEA project ( ministry of industry) collaboration with UVSQ, CEA and Bull Software environment for scientific IA64 IATO simulation toolkit (distributed under GPL)

MEDEA SMT – MEDEA+ MESA (European project): Philips, STM, Bull, Eads, + SMEs + academics Multiprocessor on-a-chip for embedded systems

Paccman project (Oppidum, ministry of industry) Eads, Matra, Bull Cryptographic ASIP

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Institutionally funded projects

Member of the HIPEAC network of excellence: Funded by European Union

Participant to the SCALA research project: defining the 10 years ahead architecture Funded by European union

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Software prototypes

Calvin2+DICE: traces and emulates SPARC, fast skipping mode used internally for 4 years

ALISE: Assembly Level Infrastructure for Software Enhancement Prototype validated on MMDSP, property of STmicroelectronics

Atllas: Analysis and Tuning tool for Low Level Assembly and Source code Prototype, property of Thomson MMD

CAHT: Computer Aided Hand Tuning Prototype validated on scientific applications and embedded

applications SOFAN: code optimizer for a custom designed processor for QCD

ApeNEXT project: multiteraflop machine for QCD

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Major (mature) software developments

ABSCISS: retargetable processor simulation

SALTO: System for Assembly Languages Transformation and optimization

SWARP: C-to-C retargetable preprocessor for multimedia instructions

Menhir: Matlab to C parallel code generator

PACCMAN compiler/simulator HAVEGE random number

generator IATO toolkit: IA64 simulation

Transferred to industry

Distributed on demand, also transferred to industry



Maintenance by industry Distributed for non-commercial

use GPL

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Set-up of the start-up CAPS Entreprise(2003)

Software tools for high performance embedded systems:

Simulation, code transformation, worst-case execution time

Custom consulting services:

Performance analysis, instruction set evaluations, ..

Awarded as an innovative company by ministry of Industry

Currently 6 employees, including 5 former CAPS project-team members

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Positionning at INRIA and in France

Four groups on performance oriented compilation and architecture: Alchemy, CAPS, Compsys, R2D2

CAPS: uniprocessor architecture and compiler for embedded uniprocessor

Alchemy, Compsys: parallel architectures, now parallel embedded architectures, futuristic architectures

R2D2: reconfigurable FPGAs and SoCs

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International positioning

Processor architecture: A single large visible group in Europe: UPC Barcelona A few visible seniors in Europe: P. Stenstrom, S. Vassiliadis, .. Many groups in USA, Wisconsin, Michigan, Washington, .. + industry labs: Intel, IBM, .. CAPS highly recognized on caches and branch prediction

Compiler/software environment for embedded systems: Original position associated with the focus on developing

retargetable platforms Related activities: R. Leupers (Aachen), R. Wilhelm (Saarbruck)

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CAPS future objectives

Leverage current expertise of CAPS core team Microarchitecture Compiler/software environment

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“New-CAPS” objectives (2)

High-end microprocessor architecture:

From “ultimate performance” to “ maintaining performance to cheaper”

Migrating “high-end” concepts to embedded processors: (limited) O-O-O execution Compiler/architecture power management

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Embedded systems are more and more complex: performance often comes with unpredictability and

unstabibility• Dimensioning a system ?• Real time constraints ?

Research on performance predictability and stability: Predictable/stable performance oriented code generation Predictable/stable performance oriented architecture

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On-chip thread parallelism is a new opportunity:

Homogeneous: SMT/CMP• Tradeoffs, sharing, synchronization

Heterogeneous: • single ISA

– Power, performance,• multiple ISAs (e.g. SoC)

– Thread extraction

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Capitalize on pioneering researches: Iterative compilation Use of machine learning techniques for compilers

Believe in retargetable software environments: ISAs, architecture, ..

CAPS project-team Compilation et Architectures pour Processeurs Superscalaires et Spécialisés.

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