Nitisha Garg

Asst. Prof. (GIET)

QUESTION BANK

COMPUTER ARCHITECTURE ORGANIZATION

Q. What is Computer Architecture?

Ans. Computer Architecture : It is concerned with structure and behav iour of computer as seen by the user. It includes the information formats, the instruction set,

and techniques for a ddressing memory of a computer system is concerned with the s pecifications of the various fun ctional modules, such as processors and memories and structuring them together into a computer system.

Q. What is Computer Organisation?

Ans. Computer Organisation: It is concerned with the

way the hardware components operate and the way they are connected together to form the computer system. The various components are assumed to be in place and the task is to investigate the organisational structure to

verify that the com puter parts operate.

Q. What is the concept of layers in architectural design?

Ans. The concepts of layers in architectural design are described as below:

1. Complex problems can be segmented into smaller and

more manageable form.

2. Each layer is specialized for specific functioning.

3. Upper layers can share the services of a lower layer.

Thus layering allows us to reuse functionality.

4. Team development is possible because of logical segmentation. A team of programmers will build. The

system and work has to be sub -divided of along clear boundaries.

Q. Differentiate between computer architecture and computer organisation.

Ans. Difference between computer architecture and computer organisation:

Q. Draw top leveled view of computer components.

Ans . Computer organization includes emphasis on system components, circuit design, logical design,

structure of instructions, computer arithmetic, processor

control, assembly programming and methods of

performance enhancement.

Diagram : Top level view of computer component

Q. Write typical physical realisations of architecture.

Ans. Important types of bus architecture used in a computer system are:

(i) PCI bus

(ii) ISA bus

(iii) Universal serial bus (USB)

(iv) Accelerated graphics port (AGP).

PCI bus : PCI stands for peripheral component interconne ct It was developed by Intel. To day it is a widely used bus architecture . The PCI bus can operate with either 32 bits or 64 bit data bus and a full 32 -bit

address bus.

ISA Bus: ISA stands for industry standard Architecture.

Most Pcs contain ISA slot on the main board to connect either an 8 bit ISA card or a 16 bit ISA card.

USB : It is a high speed serial bus. It ha s higher data

.transfer rate than that of a serial port fashion. Several devices can be connected to it in a daisy chain.

AGP: It is a 32 bit expansion slot or bus specially design

for video card.

Q. What is Channel?

Ans. A channel is one of data transfer technique. This

technique is a traditionally used on mainframe computers and also becoming more common on smaller systems. It controls multiple high speed devices. It combines the features of multiple and selector channels. This channel

provides a connection to a number of High speed devices.

Q. Draw the machine architecture of 8086.

Ans.

Q. Explain about the computer Organisation.

Ans. Computer organisation is concerned with the way the hardware components operate and the way they are connected together to form the computer system. The

various components are assumed to be in place ad task is to be a organisational structure. IL includes emphasis on the system components, circuit design, logical design, structure of instruction, computer arithmetic, processor

control, assembly programming and methods of performance enhancement.

Q. Explain the significance of layered architecture

Ans. Significance of layered architecture: In layered

architecture, complex problems can be segment ed into smaller and more manageable form. Each layer is specialized for specific functioning. Team development is

possible because of logical segmentation. A team of programmers will build. The system, and work has to be sub -divided of along clear boundaries.

Q. HOw can you evaluate the performance of processor architecture.

Ans. In processor architecture, there is no. of processor

where 8086 and 8088 has taken an average of 12 cycles to execute a single instruction. XXX286 and XX386 are 4.5 cycles per instruction XX486 and most fourth generation intel compatible processor such as DMD X 85,

drop the rate further, about 2 cycles per instruction. Latest processor are pentium pre, pentiom 11/111/4/celeron and Athlon/ Duress : These P6 and P7

processor S can execute as many as three or more instructing per cycle.

Q. Explain the various types of performance

metrics.

Ans. Performance metrics include availability, response time, Channel capacity, latency, Completion time.

Q.

Or

H/W and S/W partitioning design:

Ans . One common architectural design pattern is based on layers. Layers are an architectural design pattern that

structures applications can be decomposed into groups of subtasks such that each of subtasks is at a particular level of abstraction.

A large syste m requires decomposition. One way to decompose a system is to segment it into collaborating objects. Then these objects are grouped to provide related types of services. Then these groups are

interfaced with each other for inter communication and that resu lts in a layered architecture. The traditional 3tier client server model, which separates application

functionality into three distinct abstractions, is an example of layered design. The three layers include data, business rules and graphical user interfa ce. Similar is the

051 seven layer networking model and internet protocol stack based on layered architecture.

The following are the benefits of layered architecture

1. Complex problems can be segmented into smaller and

more manageable form.

2. Team develo pment is possible because of logical segmentation. A team of programmers will build the

system, and work has to be sub -divided along cler boundaries.

3. Upper layers can share the services of a lower layer.

Thus layering allows us to reuse functionality.

4. Each layer is specialized for specific functioning.

Late source code changes should not ripple through the system of layered architecture. The similar

responsibilities should be grouped to help understand abil ity and maintainability. Layers are implemented as software to isolate each disparate concept or technology.

The layers should isolate at the conceptual level. By isolating the database from the communication code, we can change one or the other with minimum impac t

on each other. Each layer of the system deals with only one concept. The layered architecture can have many beneficial effects on application, if it is applied in proper way. The concept of architecture is simple and easy to

explain to team members and s o demonstrate where

layered architecture, the potential for reuse of many

objects in the system can greatly increased.

Q. Write a note on.

(a) VLIW Architecture (b) Super scalar processor.

Ans. (a) Very long instruction word (VLIW) is a modification over super scalar architecture VLIW

architecture implements instruction level parallelism ( ILP). VLIW processor fetches ver y long instruction work having several operations and dispatches it is paral lel

execution to different functional units. The width of instruction varies from 128 to 1024 bits. VLIW architecture offers static scheduling as super scalar architecture offers dynamic (run time) scheduling. That

means view offers a defined plan of execu tion of instruction by functional units. Due to static scheduling, VLIW architecture can handle up to eight operations pe r

clock cycle. While super scala r architecture can handle up to five operations at a time. VLIW architecture needs the complete knowled ge of Hardware like processor and their

functional units. It is fast but inefficient for object oriented and event driver programming. In event driven and object oriented programming super scala r architecture is used. Hence view and super scala r

architecture are important in different aspe cts.

(b) Super Scala r Processor : The scala r processor executes one instruction on one set of operands at a

time. The super scala r architecture allows the execution of multiple instructions at the same time. In different pipelines. Here multiple processing elements are used for

different instruction at the same time. Pipelining is also implemented in each processing elements.

The instruction fetching units fetch multiple instructions

at a time from cache. The instruction decoding unit check the independence of these instruction so that they can be executed in parallel. There should be multiple

execution units so that multiple instructions can be executed at same time. The slowest stage among fetch, decode and execute will determine the overall

performance of the system. Ideally these three stages should be equally fast. Practically execution stage in slowest and drastically affect the performance of system.

Q. Write a note on following:

(i) Pentium Processor - (ii) Server System

Ans. (i) Pentium processor : Pentium processor with super scalar architecture came as modification of 80486

and 8086. It is based on CISC and uses two pipelines for integer processor so that two instructions are processed simultaneously one pipeline will have same condition

then anoth er is compared with hardware 80486 processor had only adder in one chip floating point unit. One the other side Pentium processor is having adder,

multiplier and divide in on chip floating point unit. That means Pentium processor can do the multiplication and division fastly. The separate data and code cache of 8KB exits on chip. Dual independent bus (DIB) architecture

divides the bus as front side and backside bus. Backside Bus transfer the data from L2 Cache to CPU and vice -versa. Front side bus is used to transfer the data from

CPU to main memory and to other components of system.

Pentium processor user write back policy for cache data,

while 80486 uses write through policy for cache data. The detail other common types of processor are AMD and cyrix Although these two types of processor are less

powerful as compared to Pentium Processor.

(ii) Server System : System is formed as server or client depending upon the software used in that machine

suppose window 2003 server operating system is installed on machine, that machine will be termed as sever. If on the same machine Window 95 i s installer that machine is termed as client. Although server

machine uses specialised hardware meant for faster processing server provides the service to other machine called client attached to server. Different types of servers

are Network server, web se rver, database server, backup server. Sever system is having powerful computing power, high performance and higher clock speed. These

system are having good fault tolerance capability using disk mirroring, disk stripping and RAID concepts. These system hav e back up power supply with hot swap. IBM and SUN servers are providing the different server of

server for different use.

Q. What is principle of performance and scalability in Computer Architecture.

Ans. Computer Architecture have the good performance of computer system. It is implementing concurrency can enhance the performance. The concept of concurrency

can be implemented as parallelism or multiple processors with a computer system. The computer performance is

measured by the to tal time needed to execute

application program . Another factor that affects the performance is the speed of memory. That is reason the current technology processor is having their own cache

memory. Scalability is required in case of multiprocessor to have good performance.

The sca lability means that as the cost of multiprocessor

increase, the performance should also increase in proportion . The size access time and speed of memories and buses play a major role in the performance of the system.

Q. What is evaluation of computer architecture?

Ans. Computer Architecture involves both hardware org an isation and programming software requirements. At

seen by an assembly language programmer, computer architecture is abstracted by an instruction set, which includes opcode (operation codes), addressing modes,

register, virtual memory, etc. from the hardwar e implementation point o1 view, the abstract machine is organised with CPUs, caches, buses, microcode, pipelines

physical memory etc. Therefore, the study of architecture covers both instruction set architectures and machine implementation organisation.

Over the past four decades, computer architecture has

gone through evolution rather than revolutionary changes, sustaining features are those that were proven performance delivers. We started with Neumann

architecture built as a sequential machine executing scalar data. The sequential Computer was improved from bit survi val to word -parallel operations,

and from fixed point to floating point operations. The von

Neumann architecture is slow due to sequential execution of in programs.

Q. What is paralle lism and p ipelining in computer

Architecture?

Ans. LOOK AHEAD, PARALLELISM , AND PIPELINING IN COMPUTER ARCHITECTURE

Look ahead techniques were introduced to prefetch instruction in order to overlap I/F (Instruction fetch/decode and execution) operations and to enable

functional parallelism.

Functional parallelism was supported by two approaches : One is to use multiple functional units simultaneously and the other is to practice pipelining at

various processing levels.

The la ter includes pipe lined instruction execu tion, pipelined arithmetic computa tion, and memory access

operations. Pipelining has proven especially attractive in perform ing ident ical operations repeate dly over vector data strings. Vector operations were originally carried out

implicitly by softwar e controlled looping using scala r pipeline processors.

Q. How many cycl es are required to execute per

instruction for 8086, 8088, intel 286, 386, 486, pentium, K6 series, pentium 11/111/4/cebron, and Athion/Athion XP/Duron?

Ans. The time required to execute instructions for

different processors are as follows:

to execute a single instruction.

per instruction. 486 : The 486 and most other fourth generation intel -compatible processors, such as the DMD

5 x 86, drop the rate further, to about 2 cycles per instruction.

he pentium architecture and other fifth generation intel compatible processors, such

as those from AMD and cyrix, include twin instruction pipelines and other improvements that provide for operation at one or two instruction per cycle.

um II,fIII/4/celeron, and Athion/Athlon XP/Duron : These P6 and P7 (Sixth and Seventh generation) processors can execute as many

as three or more instructions per cycle.

Q. What is cost/benefit in layered Architecture design?

Or

Write functional view of computer which are the possible computer operational.

Ans. A larger system require decomposition. Only way to

decompose a system is to segment it into collaborating objects. These objects are grouped to provide r elated types of services. Then these groups are interfaced with

each other for inter communication and that results in a layered architecture.

The following are benefits of layered architecture

1. Complex problems can be segmented into smaller and more man ageable form.

2. Team development is possible because of logical

segmentation. A team of programmes will build the system, and work has to be subdivi ded along clear boundaries.

3. Upper layer can share the services of a lower layer. Thus layering allows us to reuse functionalities.

4. Each layer is specialized for specific functioning.

5. Late source code changes should not ripple through

the system because of layered architecture.

6. Similar responsibilities should be grouped to help under stability and ma intainability.

7. A message that moves downwards between layers is called request. A client issues a request to layer. I suppose layer I cannot fulfill it, then it delegates to layer

J 1.

8. Messages that moves upward between layers are called notification s. A notification could start at layer I. Layer I then formulates and sends a message

(notification) to layer j +1.

9. Layers are logical placed to keep information caches. Requests that normally travel down through several

layers can be cached to improve performance.

implemented as a layer. Thus if two application or inter

application elements need to communicate placing the interface responsibilities into dedicated layers. Can greatly simplify the task and mak e them more easily reusable.

Layers are implemented as software to isolate each

disparate concept or technology. The layers should isolate at conceptual level. By isolating the data base from the communicate code, we can change one or the

other with minimu m impact on each other. Each layer of the system deals with only one concept.

The layered architecture can have many beneficial effects

on application, if it is applied in proper way. The concept of the architecture is simple and easy to explain to team me mber and so demonstrate where each objects role fits into the team. With the use of layer architecture, the

potential for reuse of many objects in the system can be greatly increase. The best benefit of this layering is that .malws it easy to divide work a long layer boundaries is

easy to assign different teams or individuals to work of coding the layers in layered architectures, since the interfaces are identified and understood well in

advance of coding. Performance of system is measure of speed, throughpu t. Higher is cost involves for manufacturing of computer, High is the performance as shown in figure.

Personal computer is cheapest in term of cost among

server, mainframe and super computer. Super computer is the costliest one. Same is the hierarchy for the performance of the system. Most of simple applications

can be executed on personal computers. For faster processing server, mainframe and super computing are

used. Sometimes using too much I/O devices increases

the cost but decreasing the performance in personal computer. That is termed as diminishing the performance with increase in the cost/sublinear dimin ishing, Like SCSI

adopter increase the cost of system but that also increases the performance of server as termed as super linear economy in case of server. The ideal case is

termed as linear representation where performance increases in the same proportion of cost. These are repr esented in graph shown in figure.

Q. Define ASCII code.

Ans. ASCII stands for American Standard code for Information Interchange. It is greatly accepted standard alphanumeric code used in microcomputers. ACII of bit code represents 2 128 different characters. These

character represent 26 upper case letter (A to Z), 26 lowercase letters (a to z), 10 numbers (0 to 9), 33 special characters, symbols and 33 control characters.

ASCII 7 -bit code is divided into two portions. The left most 3 -bits portion is called zone bits and the 4 -bit portion on the right is called the numeric bits. ASCII 8 -bit

version can be used to represent a maximum of 256 characters.

Q. What is EBCDIC?

Ans . EBCDIC stands for extended Binary coded Decim al interchange code. A standard code that uses 8 -bits to represent each of 256 alphanumeric characters Extended

Binary coded Decimal interchange code is an 8 -bit character encoding used on IBM mainframes EBCDIC having eight bits code divided into two parts . The first

four, bits (on the left) are called zone and represent the category of the character and the last four bits (on the right) are called the digits and identify the specific

character.

Q. Write a short note on: (i) Excess 3 (ii) Gray code.

Ans. Excess 3 : Excess 3 is a non -weighted code used to express decimal numbers. The code derives its name from the fact that each binary code is the corresponding

8421 code plus 0021 (3). Excess representation of decimal numbers 0 to 9

Example

Gray Code : Gray coding is an important code and is known for its speed. This code is relatively free from the

errors. In binary coding or 8421 BCD, counting from 7(0111) to 8(1 000) requires 4 -bits to be chan ged simultaneously. Gray coding avoids this by following only one bit changes between subsequent numbers.

Q. What is shift register in digital computer.

Ans. Shift registers are the sequential logic circuit used to shift the data from registers in both directions. Shift

registers are designed as a group of flip - flops connected together so that the output from one flip - flop becomes the input to the next flip - flo p. The flip - flop are driven by

a common clock signals and can be set or reset simultaneously. Shift registers can be connected to form different type of counters.

Q. Which logic name is known as universal logic?

Ans . NAND logic and NOR logic gates are universal logic. It is possible to implement any logic expression by NAND

and NOR gates. This is because NAND and NOR gates can be used to perform each of Boolean operations INVERT, AND and OR. NAND is same as AND gate

symbol except that it has a small circle at output. This a small circle represents the universal operations.

Q. What is time known when D - input of D - FF must not change after clock is

applied?

Q. Addition of (1111)2 to 4 -

(1) incrementing A (ii) Addition of (F)11

(iii) No change (iv) Decrementing A.

Ans . Addition of (F)H

Q. Register A holds the 8 - bit binary 11011001.

Determine the B operand and the logic micro -operation to be performed in order to change the value in A to:

Q. An 8 - bit register R contain the binary value 10011100 what is the register

value after an arithmetic shift right? Starting from the initial number

10011100, determine the register value after an arithmetic shift left, and

state whether there is an overflow.

Q. Write an algorithm of summation of a set of numbers.

Ans . This sum is a sequential operation that requires a sequence of add and shift micro -operation. There is addition of n numbers can be done with micro -operation

by

means of combinational circuit that performs the sum all

at once.

An array addition can implemented with a combinational circuit. The argend and addend are i.e. a0, a1, a2, a3

...a.

There are following steps of summation of a set of number.

Step 1 . There is n -array, numbers which are a1, a1, a2 .. .a so the result is in sum.

Step 2 . Input of a0, a2, a3,.. .a1 are given the combinational logical circuit. It shows the result.

Step 3 . The output is takens in sum and some time, a carry is produced.

Step 4 . A carry is put in the carry flag. The total result of

sum is stored in SUM and carry is stored in CARRY.

Q. Simplify the following Boolean functions using three variable map in sum of product form.

1.f(a,b,c)=(1,4,5,6,7)

2. f.(a, b, c) = E (0, 1, 5, 7)

3. f (a, b, c) = E (1, 2, 3, 6, 7)

4. f (a, Li, c) = (3, 5, 6, 7)

5.f (a, Li, c) Y(O, 2, 3,4,6)

Ans.

Q. Simplify the ( a, b, c, d) = (0,1,2,5,8,9,10)

Boolean functions using four variable map in sum of product and product of sum form. Verify the results of both using truth table.

Ans . Sum of Product (SOP)

f(a,b,c,d) =E(O,1,2,5,8,9,1O)

These are two 4 -bit input A(A3, A2, A1, A0) B (B3, B2, B1, l3) and a 4 -bit output D (D3, D2,D, D0). The four

inputs form A(A3, A2, A1, A0) are applied directly to X (X3 X2, X1, X0)

inputs of full adder. The four are connected to data input I of four multiplexer. The

logic input 0 is connected to data input 12 oi four multiplexers.

The logic input I is connected to data input 13 of four

multiplexers. One of the four inputs of multiplexer as output is selected by two selection lines S0 and S1. The outputs from all four multiplexers are connected to the Y

(Y3 Y2 Y, Y0) inputs of full adder. The input carry Cm is applied to the carry input of the full adder FAI. The carry generated by adder is connected to next adder and finally cout is generated. The output generated by full

adder is represented by expression shown ahead.

Q. Explain the De - Morgan's theorems.

De-Morgan theorem is applicable to n number of variable. Where n can have value 2, 3, 4 etc. De -Morgan

theorem for three variables will be shown ahead.

To prove the following identity

-Morgan theorem]

-Morgan theorem]

The truth table for the second expression is given ahead.

). Prove the 2nd theorem.