Calice ECAL Readout Hardware

Status report

Adam Baird

ECAL Meeting 26 Sept 2003

LLR-Ecole Polytechnique

Calice - ECAL• Hardware - Readout Module

• Firmware– front FPGA (from Osman Zorba)– Trigger (from Matthew Warren)

Adam Baird

Rutherford Appleton Laboratory

Adam Baird

Rutherford Appleton Laboratory

Adam Baird

Rutherford Appleton Laboratory

Adam Baird

Rutherford Appleton Laboratory

Adam Baird

Rutherford Appleton Laboratory

Adam Baird

Rutherford Appleton Laboratory

Analogue - Front panel96 (8x2x6) Differential Analogue inputs (max), 16 bits 500KHz16 (8x2x1) Differential Analogue outputs (max), 16 bits 1MHz

Digital - Front panel544 (8x2x34) bi-directional busLVDS pairs (max), Peak data rate @ 100MHz = 54.4G bits/s

Processing Power - 12M Xilinx Virtex-II gates (max).

Readout - Back panel - 64 bit VME interface, plus 48 LVDS pairs

Calice ECAL - Readout Module

CMS Final Front End driver

Adam Baird

Rutherford Appleton Laboratory

CMS Final Front End driver

Adam Baird

Rutherford Appleton Laboratory

Timescales

Adam Baird

Rutherford Appleton Laboratory

Completion 2wks (from today)PCB Fabrication, 3wksPCB assembly, 1wkJTAG test, 1wk (mid Nov)VFE test (Jan 2003 ???)3 Months test3 Months production (30 June 2003)

Adam Baird

Rutherford Appleton Laboratory

Calice ECAL Firmware

Front FPGAADC data captureVFE control

Back FPGAData managementTrigger control

VME FPGA