Calibrating Achievable DesignCalibrating Achievable DesignRoundtable DiscussionRoundtable Discussion

June 9, 2002June 9, 2002

Facilitator: Bill Joyner, IBM/SRCFacilitator: Bill Joyner, IBM/SRC

Wayne Dai, Andrew Kahng, Tsu-Jae King, Wojciech Wayne Dai, Andrew Kahng, Tsu-Jae King, Wojciech Maly, Igor Markov, Herman Schmit, Dennis SylvesterMaly, Igor Markov, Herman Schmit, Dennis Sylvester

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Recent Progress in Technology Recent Progress in Technology Extrapolation and GTXExtrapolation and GTX

• Transition-aware and active-shielding global signaling Transition-aware and active-shielding global signaling approaches, RLC interconnect performance modelsapproaches, RLC interconnect performance models

• Taxonomy and correlated models of process variability, Taxonomy and correlated models of process variability, and framework for examining impact on achievable designand framework for examining impact on achievable design

• New DRAM access time model in support of eDRAM vs. New DRAM access time model in support of eDRAM vs. multi-die cost/performance modelmulti-die cost/performance model

• Release of ITRS-2001 ORTCs in GTXRelease of ITRS-2001 ORTCs in GTX• Updated GTX version in Sematech ITRS-2001 websiteUpdated GTX version in Sematech ITRS-2001 website• Enhancements in June02 releaseEnhancements in June02 release

• Ongoing studies, modeling of ITRS “shared red bricks”Ongoing studies, modeling of ITRS “shared red bricks”• Low-k benefit, variability tolerance of design, design-limiting Low-k benefit, variability tolerance of design, design-limiting

process rules, …process rules, …

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Recent Progress in CAD-IP ReuseRecent Progress in CAD-IP Reuse

• Prototype release of Bookshelf.exe Prototype release of Bookshelf.exe • New infrastructure that hosts executable Bookshelf New infrastructure that hosts executable Bookshelf

content and allows remote executioncontent and allows remote execution• Web interface, distributed computation platform, and Web interface, distributed computation platform, and

scripting capabilitiesscripting capabilities• New tilable (i.e., scalable) circuit benchmarksNew tilable (i.e., scalable) circuit benchmarks

• Network tileNetwork tile• Processing elements (floating-point adder, floating-Processing elements (floating-point adder, floating-

point multiplier, programmable FIR filter)point multiplier, programmable FIR filter)

• Initial discussions of OpenAccess API and data modelInitial discussions of OpenAccess API and data model• Benchmark scaling approachesBenchmark scaling approaches

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Recent Progress in METRICSRecent Progress in METRICS

• Expanded METRICS system to front-end acceptance and Expanded METRICS system to front-end acceptance and clock tree synthesis domainsclock tree synthesis domains

• Work with STRJ-WG1 (Japan Roadmap group) to obtain Work with STRJ-WG1 (Japan Roadmap group) to obtain design quality / value survey questions that will be used to design quality / value survey questions that will be used to survey U.S. companiessurvey U.S. companies

• Started to propagate open-source METRICS system Started to propagate open-source METRICS system available to university user group communitiesavailable to university user group communities• Exploring potential links to Bookshelf.exeExploring potential links to Bookshelf.exe• METRICS Birds-of-Feather meeting at DAC-2002METRICS Birds-of-Feather meeting at DAC-2002

• Developing and applying machine learning techniques to Developing and applying machine learning techniques to improve existing data mining and regression infrastructureimprove existing data mining and regression infrastructure

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Summary: Roles of the C.A.D. ThemeSummary: Roles of the C.A.D. Theme

Repository of best known methods, Repository of best known methods, models, metricsmodels, metrics Connects applications and drivers (e.g., Connects applications and drivers (e.g.,

ITRS MPU, SOC) to technology roadmapITRS MPU, SOC) to technology roadmap Connects algorithm (e.g., Fabrics) and Connects algorithm (e.g., Fabrics) and

design technology (e.g., Power-Energy) design technology (e.g., Power-Energy) within GSRC and to designs, interconnects, within GSRC and to designs, interconnects, devices, and materials (= other FRCs)devices, and materials (= other FRCs)

Agent of culture changeAgent of culture change Measurement & characterization of EDAMeasurement & characterization of EDA Open-source CAD-IP; vertical benchmarkingOpen-source CAD-IP; vertical benchmarking New vectors: e.g., reusable curriculum IP New vectors: e.g., reusable curriculum IP

for VLSI, VLSI design, VLSI design for VLSI, VLSI design, VLSI design technology educationtechnology education

Identify best opportunities for “sharing of red bricks” between EDA Identify best opportunities for “sharing of red bricks” between EDA and other semiconductor supplier industriesand other semiconductor supplier industries GTX studies + Manufacturing Calibration: Is low-k worth the development cost? GTX studies + Manufacturing Calibration: Is low-k worth the development cost?

What is the best interconnect process architecture for 65nm? What FEOL and What is the best interconnect process architecture for 65nm? What FEOL and BEOL variabilities can designers tolerate? What is the most cost-effective BEOL variabilities can designers tolerate? What is the most cost-effective memory-logic integration?memory-logic integration?

C.A.D. Theme

Other FRCs

Other GSRC

Themes

EDA Industry & Academia

ITRSSemi

Industry

Design Houses

METRICS & Design Process Opt

Models and Calibrations

Open-Source CAD-IP

Living ITRS

What is the design problem?

VLSI Design EducationManufacturing Calibration

How should Design help solve ITRS red bricks?

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C.A.D. Theme Draft RoadmapC.A.D. Theme Draft Roadmap

1/99 Today 1/03 1/04 1/05

o Start Fabrics Thrust, initial data model / flow discussionso Fabrics C.A.D. + Constructive Fabrics Themes

o GTX v.1 + ITRS supporto METRICS v.1 + start industry integration

o Bookshelf @ 25 slots, first papers

1/01

o GTX v.2 (with ITRS-2001)

o GTX model dirs = mfg cost/cal, global sig, mem-logic, app domainso METRICS broader academic release

o BX.exe v.1

Interactions

Initiatives and Milestones o ITRS “shared red brick” modeling, analysis, roadmapping

o Fabrics Theme – Bookshelf, flows researcho ITRS community o Power-Energy Theme – capture/guide

o MSD FRC – mfg calibration, manufacturability shared red bricks

o Interconnect FRC – model/calib, mfg/var shared red brickso Self-Test Theme – capture/guide

o Vertical benchmarks: cell libraries, DSP, netwk

o Open-source RTL-GDSII flow

o Natl VLSI design curriculum initiative

o NSF (education)

o BK 25% PD adopt, 50% slot interop

1/99 Today 1/03 1/04 1/051/01

o Fabrics– “SIP design tech backplane”o NEMI, C2S2 FRC – app roadmaps

o “SIP design tech backplane” is METRICized

o 30% of ITRS in GTX

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Foci of Industry Feedback and InteractionFoci of Industry Feedback and Interaction

• OpenAccess (common data model) – what is GSRC doing?OpenAccess (common data model) – what is GSRC doing?• CAD-IP reuse – Bookshelf Slots, codes, functionalityCAD-IP reuse – Bookshelf Slots, codes, functionality• Benchmarks – “industry-strength validation of research”Benchmarks – “industry-strength validation of research”• Education initiative?Education initiative?

• National-scale VLSI education infrastructureNational-scale VLSI education infrastructure• ITRS needs (= how to best share “red bricks”)ITRS needs (= how to best share “red bricks”)

• Incremental benefits of lower kIncremental benefits of lower k• ““Optimal interconnect stack”? (balancing power delivery, Optimal interconnect stack”? (balancing power delivery,

routing density, delay and signal integrity performance, …)routing density, delay and signal integrity performance, …)• ““What variability can designers tolerate?”What variability can designers tolerate?”• ESD protection impact on off-chip signaling bandwidthESD protection impact on off-chip signaling bandwidth• Understanding how ground rules impact layout densityUnderstanding how ground rules impact layout density

• What else?What else?

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RoundtableRoundtable Discussion QuestionsDiscussion Questions • For our industrial partners: in your designs, what is the largest For our industrial partners: in your designs, what is the largest

problem that you face ?problem that you face ?• And how does the research work in this Theme help?And how does the research work in this Theme help?

• What is being done well in this Theme?What is being done well in this Theme?• What could be improved?What could be improved?• On one or two slides (max), each industrial co-facilitator please On one or two slides (max), each industrial co-facilitator please

summarize key conclusions from this discussion.summarize key conclusions from this discussion.

Questions and issues for discussion Questions and issues for discussion not restricted to this set. not restricted to this set.