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2013-1228(Reexamination Nos. 95/001,107 and 95/001,132)

IN THE U NITED S TATES COURT OF APPEALS FOR THE F EDERAL C IRCUIT

___________

RAMBUS, INC., Appellant ,

v.

MICRON TECHNOLOGY, INC., Appellee.

___________

Appeal from the United States Patent and Trademark Office,Patent Trial and Appeal Board.

___________ BRIEF FOR APPELLANT RAMBUS INC.

___________

June 28, 2013

J. Michael JakesJames R. BarneyMolly R. Silfen

Aidan C. SkoylesFINNEGAN , HENDERSON , F ARABOW, G ARRETT & DUNNER , LLP901 New York Avenue, NW

Washington, DC 20001(202) 408-4000

Attorneys for Appellant Rambus Inc.

Case: 13-1228 Document: 27-1 Page: 1 Filed: 06/28/2013

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CERTIFICATE OF INTEREST

Pursuant to Federal Circuit Rules 27(a)(7) and 47.4(a), counsel for AppellantRambus Inc. certify the following:

1. The full name of every party or amicus represented by us is:

Rambus Inc.

2. The name of the real party in interest (if the party named in the caption is notthe real party in interest) represented by us is:

Rambus Inc.

3. All parent corporations and any publicly held companies that own 10 percent or more of the stock of any party represented by us are:

None

4. The names of all law firms and the partners or associates that appeared for the parties now represented by us in the trial court or are expected to appear in thisCourt are:

J. Michael Jakes, Kathleen Daley, James R. Barney, Naveen Modi,

Molly R. Silfen, Aidan C. SkoylesFINNEGAN , HENDERSON , FARABOW , GARRETT & DUNNER , LLP


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TABLE OF CONTENTS

Table of Authorities ................................................................................................... v

Statement of Related Cases .................................................................................... viii

Statement of Jurisdiction ............................................................................................ 1

I. Statement of the Issues .................................................................................... 2

II. Statement of the Case ...................................................................................... 2

III. Statement of Facts ............................................................................................ 6

A. Procedural HistoryMicron Appealed a Samsung Issue tothe Board That Micron Never Raised in Its OwnReexamination Request ......................................................................... 6

1. The Samsung Reexamination Request ....................................... 6

2. The Micron Reexamination Request .......................................... 7

3. The PTOs Merger of the Two Reexaminations ......................... 8

4. Samsungs Withdrawal from Reexamination ............................. 8

5. The Examiners Decision ............................................................ 8

6. The Parties Appeals to the Board .............................................. 9

7. The Boards Ruling That Micron Had Standing toAppeal Samsungs Issues .......................................................... 10

B. Facts Relating to the Boards Reversal of the ExaminersFinding That Claim 27 of the 051 Patent Is Not Anticipated

by Bennett ............................................................................................ 11

1. The 051 Patent ......................................................................... 11

2. Background of the Technology-at-Issue ................................... 12

a. Dynamic Random Access Memory Devices .................. 12

b. Asynchronous Versus Synchronous MemoryDevices ........................................................................... 12


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c. The Role of Access-Time Registers in theSynchronous Memory Devices of the 051 Patent ......... 14

3. The Bennett Reference .............................................................. 18

a. Overview of Bennett ....................................................... 18

b. The Role of Wait Lines in Bennett ............................. 21

c. Timing of Bus Activity in Bennett ................................. 24

i. Figure 36 ............................................................... 24

ii. Figure 35 ............................................................... 26

iii. Figure 32 ............................................................... 30

iv. Figures 25 a and 25 b ............................................. 32

4. The Examiners Finding That Bennett Does NotAnticipate Claim 27 .................................................................. 36

5. The Boards Decision Reversing the ExaminersFinding That Bennett Does Not Anticipate Claim 27 .............. 38

IV. Summary of Argument .................................................................................. 39

V. Argument ....................................................................................................... 40

A. The Board Erred in Determining That It Had JurisdictionOver Microns Appeal ......................................................................... 40

1. 35 U.S.C. 315 Does Not Give a Requester the Rightto Appeal Issues Raised by Another Requester inAnother Reexamination, Even If the ReexaminationsAre Merged ............................................................................... 40

2. The PTOs Merger Procedure Cannot Confer Statutory Rights upon a Party that It Would NotOtherwise Have Had Absent the Merger .................................. 44

3. Because 35 U.S.C. 315 Clearly Sets Forth theLimits of the Boards Jurisdiction, the PTO Is NotEntitled to Chevron Deference in Interpreting This


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Statute ........................................................................................ 49

4. Allowing Micron to Step Into Samsungs Shoes byAppealing Samsungs Reexamination ArgumentsViolates the Statutory Prohibition Against a PartyInstituting Simultaneous Inter Partes Reexaminationsof the Same Patent..................................................................... 49

5. The Board Could Not Have Created Jurisdiction Over Microns Appeal by Entering New Grounds of Rejection of Claims 15 and 16 ................................................ 52

B. The Board Erred in Reversing the Examiners Finding thatBennett Does Not Disclose a Value Which isRepresentative of A Number of Clock Cycles .................................. 54

1. Standards of Review ................................................................. 54

a. Factual Findings of the Board Are Reviewed for Substantial Evidence Based on the Entire Record,Including Any Findings of Fact Made by theExaminer ......................................................................... 54

b. The Boards Claim Construction Is Reviewed de Novo , and Its Anticipation Finding Is Reviewed for

Substantial Evidence ....................................................... 55

2. The Board Implicitly Misconstrued Representativeas Requiring Only the Ability to Affect the Number of Clock Cycles ....................................................................... 55

3. Under the Correct Claim Construction, the BoardsFindings Lack Substantial Evidence and Are ClearlyRebutted by the Examiners Contrary Findings ....................... 59

VI. Conclusion ..................................................................................................... 66


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TABLE OF AUTHORITIES

C ASES PAGE (S)

Almendarez-Torres v. United States ,

523 U.S. 224 (1998) ............................................................................................ 51

Brand v. Miller ,487 F.3d 862 (Fed. Cir. 2007) ...................................................................... 54, 66

Chevron U.S.A. Inc. v. Natural Resources Defense Council, Inc. ,467 U.S. 837 (1984) ................................................................................ 49, 50, 51

City of Arlington, Texas v. Federal Communications Commission , No. 11-1545, slip op. (S. Ct. May 20, 2013) ...................................................... 50

Fornaris v. Ridge Tool Co. ,400 U.S. 41 (1970) .............................................................................................. 43

Gechter v. Davidson ,116 F.3d 1454 (Fed. Cir. 1997) .......................................................................... 55

In re Baker Hughes Inc. ,215 F.3d 1297 (Fed. Cir. 2000) .......................................................................... 55

In re Gartside ,203 F.3d 1305 (Fed. Cir. 2000) .......................................................................... 54

In re Paulsen ,30 F.3d 1475 (Fed. Cir. 1994) ............................................................................ 55

In re Suitco Surface, Inc. ,603 F.3d 1255 (Fed. Cir. 2010) .......................................................................... 55

Johnson v. Manhattan Railway Co. ,289 U.S. 479 (1933) ............................................................................................ 47

Kokoszka v. Belford ,417 U.S. 642 (1974) ............................................................................................ 42

Koninklijke Philips Electronics N.V. v. Cardiac Science Operating Co. ,590 F.3d 1326 (Fed. Cir. 2010) .......................................................................... 46


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Lujan v. Defenders of Wildlife ,504 U.S. 555 (1992) ............................................................................................ 51

Merck & Co. v. Kessler ,80 F.3d 1543 (Fed. Cir. 1996) ............................................................................ 46

New York v. Microsoft Corp. ,2002 WL 318565 (D.D.C. 2002) ........................................................................ 47

Office of Senator Mark Dayton v. Hanson ,550 U.S. 511 (2007) ............................................................................................ 43

Perry Education Assn v. Perry Local Educators Assn , 460 U.S. 37 (1983) .............................................................................................. 43

Phillips v. AWH Corp. ,415 F.3d 1303 (Fed. Cir. 2005) .......................................................................... 58

Rite-Hite Corp. v. Kelley Co. ,56 F.3d 1538 (Fed. Cir. 1995) ............................................................................ 52

Southern California Federal Savings & Loan Assn v. United States ,51 Fed. Cl. 676 (Fed. Cl. 2002) .......................................................................... 48

Sullivan v. Stroop ,496 U.S. 478 (1990) ............................................................................................ 43

Syntex (U.S.A.) Inc. v. U.S. Patent & Trademark Office ,882 F.2d 1570 (Fed. Cir. 1989) .......................................................................... 53

Tafas v. Doll ,559 F.3d 1345 (Fed. Cir. 2009) .......................................................................... 47

Talbert Fuel Systems Patents Co. v. Unocal Corp. ,275 F.3d 1371 (Fed. Cir.), vacated and remanded on other grounds ,537 U.S. 802 (2002) ............................................................................................ 59

Tehrani v. Hamilton Medical, Inc. ,331 F.3d 1355 (Fed. Cir. 2003) .............................................................. 56, 58, 65

United States v. Jin Fuey Moy ,241 U.S. 394 (1916) ............................................................................................ 51


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Universal Camera Corp. v. National Labor Relations Board ,340 U.S. 474 (1951) ............................................................................................ 54

STATUTES

35 U.S.C. 2 .....................................................................................................passim

35 U.S.C. 6 ............................................................................................................ 53

35 U.S.C. 141 .......................................................................................................... 1

35 U.S.C. 314 ........................................................................................................ 43

35 U.S.C. 315 .................................................................................................passim

35 U.S.C. 317 .......................................................................................... 2, 3, 51, 52

O THER AUTHORITIES

37 C.F.R. 1.989 ..................................................................................... 8, 40, 44, 46

37 C.F.R. 41.50 ..................................................................................................... 53

37 C.F.R. 41.77 ..................................................................................................... 53

4 Donald S. Chisum, Chisum on Patents 11.06 .................................................... 53

MPEP 2674 (8th ed. Rev. 7 July 2008) ................................................................ 48


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STATEMENT OF RELATED CASES

Rambus is unaware of any other appeals or petitions taken in this

reexamination proceeding. There are, however, a number of different matters

pending in this Court and other courts that involve the patent-at-issue in this

appeal, U.S. Patent No. 6,314,051 (the 051 patent).

1. The following pending cases involve the 051 patent.

a. Rambus Inc. v. Hynix Semiconductor Inc. , No. 5:05-cv-00334-

RMW (N.D. Cal.) (Whyte, J.).

b. Rambus Inc. v. Micron Technology, Inc. , No. 5:06-cv-00244-

RMW (N.D. Cal.) (Whyte, J.).

2. The following pending cases do not involve the 051 patent but

involve patents that, like the 051 patent, descend from Application No.

07/510,898 (the 898 application).

a. Hynix Semiconductor Inc. v. Rambus Inc. , No. 5:00-cv-20905-

RMW (N.D. Cal.) (Whyte, J.). This case is on remand from Appeal Nos. 2009-

1299, -1347, 645 F.3d 1336 (Fed. Cir. 2011).

b. Micron Technology, Inc. v. Rambus Inc. , No. 1:00-cv-00792-

SLR (D. Del.) (Robinson, J.). This case is on remand from Appeal No. 2009-1263,

645 F.3d 1311 (Fed. Cir. 2011).


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c. Rambus Inc. v. LSI Corp. , No. 3:10-cv-05446-RS (N.D. Cal.)

(Seeborg, J.).

d. Rambus Inc. v. STMicroElectronics, N.V. , No. 3:10-cv-05449-

RS (N.D. Cal.) (Seeborg, J.).

3. Several ex parte and inter partes reexaminations involving patents

descended from the 898 application are pending at the U.S. Patent and Trademark

Office (PTO). Of those, the following have been appealed to this Court.

a. In re Rambus Inc. , No. 2011-1247, 694 F.3d 42 (Fed. Cir.

2012).

b. Rambus, Inc. v. Kappos , No. 2012-1634 (Fed. Cir.) (briefing

complete).

c. Rambus, Inc. v. Micron Technology, Inc. , No. 2013-1087

(Fed. Cir.) (briefing not yet complete).

d. Rambus, Inc. v. Micron Technology, Inc. , No. 2013-1192


e. Rambus, Inc. v. Micron Technology, Inc. , No. 2013-1224


f. Rambus, Inc. v. Micron Technology, Inc. , No. 2013-1339

(Fed. Cir.) (docketed).


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g. Rambus, Inc. v. Micron Technology, Inc. , No. 2013-1426

(Fed. Cir.) (docketed).


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STATEMENT OF JURISDICTION

This appeal arises from two inter partes reexamination proceedings before

the U.S. Patent and Trademark Office (PTO). Micron Technology, Inc.

(Micron), one of the requesters, appealed the examiners confirmation of the

claims-at-issue to the Board of Patent Appeals and Interferences (Board). The

Board reversed the examiners confirmation of claims 27 and 43 on April 24, 2012,

and Rambus requested rehearing, which the Board denied on November 15, 2012.

The Boards decision was final and appealable. Rambus appealed. This Court has

jurisdiction under 35 U.S.C. 141.


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I. STATEMENT OF THE ISSUES

1. Did Micron have standing to appeal an issue to the Board that it never

raised in its reexamination request, where: (1) Micron did not have a statutory right

to appeal that issue prior to the PTOs sua sponte merger of Microns and

Samsungs reexamination proceedings; (2) the PTOs merger procedure is purely

administrative and cannot, by itself, create substantive appeal rights; (3) allowing

Micron to step into Samsungs shoes on appeal violated the principle of 35 U.S.C.

317(a), which prohibits a third-party requester from concurrently pursuing two

inter partes reexaminations of the same patent; and (4) the Board originally ruled

that Micron could not appeal Samsungs issues before reversing itself on that

issue?

2. If the Board had jurisdiction, did it err in reversing the examiners

decision confirming claim 27 over Bennett, where the examiner had correctly

found that Bennett does not disclose a programmable register to store a value

which is representative of a number of clock cycles, and where the Boards

reversal of that finding was based on an incorrect construction of representative

and a factually unsupported interpretation of Bennett?

II. STATEMENT OF THE CASE

Rambus appeals the Boards reversal of the examiners decision confirming

the validity of claim 27 of the 051 patent over U.S. Patent No. 4,734,909 to


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appeal (from Samsung), i.e., that a value indicating the configuration of wait

lines in Bennett somehow satisfies this limitation. ( Id .)

As the examiner recognized, and as Micron does not dispute, a wait signal

in Bennett merely indicates whether a device is currently available to receive data;

it does not specify when it will receive data. (A1656[16:51-58].) Thus, a wait

signal is akin to a busy signal on a telephone line, merely informing the requester

that it should try again later at some unspecified time. Recognizing that wait

signals in Bennett are different than, and essentially the opposite of, the

predetermined delay time recited in claim 27, Micron devised a hypertechnical

argument based on the configuration of the wait lines in Bennettnamely,

whether they are dedicated or multiplexed.

In one subset of configurations of Bennett, wait signals are transmitted on a

dedicated wait line and can therefore be transmitted simultaneously with incoming

data. By analogy, two cars can pass on a two-lane road because each has its own

dedicated lane. In an alternative subset of configurations of Bennett, wait signals

are sent on a multiplexed line, which is shared by other signals in a time-based,

sequential fashion. This is analogous to two cars traveling in opposite directions

on a single-lane roadi.e., the cars must take turns. Samsung (and later Micron

after it stepped into Samsungs shoes) argued that the wait-line setting in Bennett

constitutes a value which is representative of the number of clock cycles to


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transpire because, ignoring all of Bennetts other settings and their effects,

multiplexing the wait-line signal and data causes the data transmission time slot to

move by one clock cycle as compared to a dedicated wait-line configuration. But

this argument, which attempts to convert Bennetts wait-line configuration into a

stored number of clock cycles, is factually incorrect, as the examiner readily

recognized.

As the examiner found, although changing the wait-line configurations in

Bennett can affect when data is sampled, the wait-line configuration itself is not

representative of a number of clock cycles since the number of wait lines [i.e.,

their configuration] does not correlate to a specific number of clock cycles.

(A1149 (emphasis in original).) He noted, for instance, that the same wait-line

value of 3 (denoting a single, dedicated wait line) results in different numbers of

clock cycles transpiring in the transactions shown in Figures 25 b, 35, and 36. He

further noted that different wait-line configurations can result in the same number

of clock cycles transpiring, for instance, as shown in the transactions in Figures

25b and 32. Thus, as the examiner correctly concluded:

[T]he above citations shown in Bennett also makes it

clear that the Wait Line does not represent a number of clock cycles but instead indicates whether data isaccepted or whether the[re] is a need to re-try at a later time. The Examiner notes that that [sic] based on the

programmed configuration, the accepting or retryingcauses data to be sampled at different clock cycles,however while the configuration digit changes the


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number of clock cycles that must transpire, theconfiguration digit itself is not indicative of the number of []clock cycles that will have transpired before data issampled.

(A1148 (emphasis in original).)

As the examiner understood (but the Board ignored), many other variables in

Bennett, including arbitration, retry conditions, pin configuration, address block

size, and bus activity, can affect the time between an operation code and data

sampling. Thus, merely knowing the wait-line configuration in Bennett (i.e.,

dedicated versus multiplexed) does not allow one to know the actual number of

clock cycles that will transpire between a given operation code and the

corresponding sampling of data, which is a critical feature of the claimed

invention. The examiner correctly recognized this and found that claim 27 is not

anticipated by Bennett. The Board erred in reversing this finding.

III. STATEMENT OF FACTS

A. Procedural HistoryMicron Appealed a Samsung Issue tothe Board that Micron Never Raised in Its OwnReexamination Request

1. The Samsung Reexamination Request

On November 7, 2008, Samsung filed a request for inter partes

reexamination of the 051 patent. In its request, Samsung alleged that claims 27,

34, and 43 of the 051 patent were anticipated by the JEDEC Standard,

U.S. Patent No 5,590,086 to Park (Park), the iAPX Manual, U.S. Patent No.


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4,480,307 to Budde (Budde), and Bennett. (A2227.) Samsung also alleged that

claims 27, 34, and 43 were rendered obvious by the JEDEC Standard in view of

Park, by Park in view of the knowledge of one of ordinary skill in the art, by the

iAPX Manual in view of either the iAPX Specification or iRAM, or by Budde in

view of iRAM. 1 ( Id. ) On January 9, 2009, the PTO ordered reexamination of the

051 patent based on Samsungs request, assigning it Reexamination Control No.

95/001,107. (A2304.)

2. The Micron Reexamination Request

On December 31, 2008, Micron filed a separate request for inter partes

reexamination of the 051 patent. In its request, Micron alleged that claim 27 of

the 051 patent was rendered obvious by Gustavson, Scalable Coherent Interface

Project (Gustavson), in view of either Bennett or U.S. Patent No. 5,301,278 to

Bowater (Bowater). (A2341-47.) Micron also alleged that claims 34 and 43

were anticipated or rendered obvious by Gustavson. ( Id. ) Notably, Micron did not

allege that claims 27, 34, or 43 were anticipated or rendered obvious by Bennett,

Budde, the iAPX Manual, the iAPX Specification, iRAM, the JEDEC Standard, or

Park. On January 22, 2009, the PTO ordered reexamination of the 051 patent

1 Samsung argued that the 051 patent was not entitled to an effective filing dateearlier than the JEDEC Standard or Park references.


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based on Microns request, assigning it Reexamination Control No. 95/001,132.

(A2355.)

3. The PTOs Merger of the Two Reexaminations

On March 6, 2009, the PTO decided sua sponte to merge the Samsung-

requested reexamination (95/001,107) and the Micron-requested reexamination

(95/001,132) into a consolidated proceeding pursuant to 37 C.F.R. 1.989.

(A2368.)

4. Samsungs Withdrawal from ReexaminationOn February 11, 2010, Samsung filed a notice of nonparticipation in inter

partes Reexamination Control No. 95/001,107, stating that it no longer intends to

participate in the present reexamination. (A2373.)

5. The Examiners Decision

On June 21, 2010, after considering all the arguments presented by Samsung

and Micron, the examiner declined to adopt Microns anticipation arguments based

on Gustavson or its obviousness arguments based on Gustavson in view of Bennett

or Bowater. (A1189-90.) The examiner also declined to adopt Samsungs

anticipation arguments based on the JEDEC Standard and Park, and Samsungs

obviousness arguments based on the iAPX Manual or Budde in view of iRAM.

(A1176-78; A1188.) The examiner adopted, however, Samsungs anticipation

argumentbut only for claim 34based on the iAPX Manual, Budde, or Bennett

and its obviousness argument based on the iAPX Manual in view of the


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iAPX Specification. Thus, at the end of prosecution, the examiner rejected claim

34 as anticipated by the iAPX Manual, Budde, or Bennett (arguments raised only

by Samsung) and sustained claims 27 and 43.

6. The Parties Appeals to the Board

Because Samsung had already withdrawn from the reexamination and was

no longer participating, it did not appeal the examiners confirmation of claims 27

and 43.

Micron, however, appealed the examiners confirmation of claims 27 and

43. Specifically, in its appeal brief to the Board, Micron challenged the examiners

findings that (1) claims 27 and 43 are not anticipated by Bennett; (2) claim 43 is

not rendered obvious by either the iAPX Manual or Budde in view of iRAM;

(3) claims 27, 34, and 43 are entitled to the earlier filing date of the 051 patents

parent application; (4) claims 34 and 43 are not anticipated by either the JEDEC

Standard or Park; and (5) claim 27 is not rendered obvious by the JEDEC Standard

in view of Park or by Park in view of the knowledge of one of ordinary skill in the

art. (A2415; A2419.) Notably, all of these arguments were originally raised by

Samsung, not Micron. Micron did not appeal any of its own issues, i.e., the

examiners nonadoption of Microns proposed rejections based on Gustavson alone

or in view of Bennett or Bowater. ( Id. )


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In short, Micron attempted to step into Samsungs shoes, taking up issues

that only Samsung had raised and that only Samsung had a statutory right to

appeal. Or, to use another analogy, Micron attempted to switch horses in the

middle of the race.

7. The Boards Ruling that Micron Had Standing toAppeal Samsungs Issues

Rambus filed a petition to expunge Microns appeal brief on the ground that

Micron lacked standing to appeal arguments that had been raised only by Samsung,

a nonparticipating party. (A2797.) On June 17, 2011, the Board denied Rambuss

petition, referring to its earlier decision in merged proceeding 95/000,250 and

95/001,124. (A2888 (citing A20003-05).) That earlier decision refers, in turn, to

the Boards February 16, 2011, reconsideration decision in merged proceeding

95/001,026 and 95/001,128 (A20009), 2 and its April 15, 2011, decision in merged

proceeding 95/000,183 and 95/001,112 (A20017). In its substantive briefs,

Rambus also raised Microns lack of standing (A2471-73), and the Board

addressed the issue in its substantive decisions, relying primarily on its petition

2 This reconsideration decision overturned the December 13, 2010, decision of theBoard in merged proceeding 95/001,026 and 95,001,128, in which the Board expunged Microns appeal brief and held that, in a notice of appeal (or crossappeal), a requester is limited to presenting rejections previously proposed by that third party requester. (A20028 (emphasis in original).)


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decision (A34-35; A4-5). Finding that it had jurisdiction, the Board then

proceeded to decide the merits of Microns appeal.

B. Facts Relating to the Boards Reversal of the ExaminersFinding that Claim 27 of the 051 Patent Is Not Anticipatedby Bennett

1. The 051 Patent

The 051 patent is titled Memory Device Having a Write Latency. (A90.)

One focus of the 051 patent is to make the memory system more efficient so that

data can be transferred faster than was possible in the prior art. This is

accomplished, in part, by: (1) employing a synchronous memory interface, i.e.,

one that utilizes an external clock signal to govern memory transactions; and

(2) using a register to store a value indicating how many clock cycles are to elapse

between an operation code and the corresponding sampling of data.

Claim 27 of the 051 patent, the sole claim-at-issue in this appeal, recites as

follows:

27. A memory device having a plurality of memoryarrays, wherein each memory array includes a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive an external clock signal;

a programmable register to store a value which isrepresentative of a number of clock cycles of the externalclock signal to transpire before sampling a first portionof data , wherein the first portion of data is sampled inresponse to an operation code; and


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data input receiver circuitry to sample the first portion of data synchronously with respect to the external clock signal.

(A120[26:30-42] (emphasis added).)

2. Background of the Technology-at-Issue

a. Dynamic Random Access Memory Devices

The improvements of the 051 patent, while applicable to many types of

memory devices, are particularly applicable to dynamic random access memory

devices or DRAMs. (A108[1:48-59].) A DRAM stores information in memory

cells, typically arranged in a two-dimensional array. (A119[23:44-46].) Each

memory cell stores a charge representing one bit of information, i.e., a 1 or 0.

(A108[1:60-64].)

A computer typically has many DRAMs controlled by a single memory

controller. (A108[2:11-14].) Information and control signals flowing between the

memory controller and the numerous DRAMs can travel on a bus, consisting of

a series of wires or lines that connect the devices. (A108[2:31-35].)

b. Asynchronous Versus Synchronous MemoryDevices

Prior to 1990 (the effective filing date of the 051 patent), conventional

DRAMs operated asynchronously, i.e., without being synchronized with an

external clock signal. (A109[3:8-14].) Because the control lines that signal read

and write operations must continually signal the asynchronous DRAM throughout


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the transfer, there was no way to temporally decouple a write operation from the

write data. The data transfers were conducted as soon as the memory controller

drove certain control signal transitions on specific bus lines and the DRAMs were

able to respond. (A108[2:8-20].)

In contrast, the DRAMs disclosed in the 051 patent are synchronous

(A111[8:43-58]), which means they operate markedly differently from prior-art

asynchronous DRAMs. The hallmark of a synchronous DRAM is that an external

clock signal governs the timing of the read and write operations. (A111[8:29-30].)

In a synchronous system, at least one signal line carries an external clock signal, as

shown below, which is used to synchronize all read and write operations for all the

DRAMs in the system.

(A105[Fig. 14].)

In this manner, the memory controller and its DRAMs operate

synchronously. For instance, the memory controller can issue an operation code

specifying a write to a particular DRAM at a given clock cycle and further

specifying that the requested data must be sampled a precise number of clock

cycles later. (A115[15:63-16:10].) Then, after that precise number of clock cycles

has elapsed, that DRAM can sample the data on the bus lines and know that it is


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the data associated with the earlier write request. ( Id. ) Meanwhile, in the

intervening clock cycles, the memory controller can issue another operation code

to another DRAM and start another access while the first DRAM is processing the

first write request. ( Id. ) In this way, transactions can be interleaved and pre-

scheduled to occur at certain times, i.e., after a certain number of clock cycles.

( Id. )

To understand why interleaving is desirable, it is important to remember that

read and write operations take time and that a memory bus has only a limited

number of lines to carry all the necessary control signals and data between the

memory controller and multiple DRAMs. (A115[15:63-16:2].) If the bus lines are

tied up during a particular transaction with one DRAM, they are not available for

other transactions that the memory controller may wish to execute. However, if

the delay time between an operation code and the corresponding sampling can be

precisely known (e.g., the data for writing will be sampled in exactly X clock

cycles), then during the intervening clock cycles, the memory controller can issue

other requests or send/receive data corresponding to previous requests. This

increases the overall efficiency of the system. ( See A111[7:7-17].)

c. The Role of Access-Time Registers in theSynchronous Memory Devices of the 051 Patent

The 051 inventors realized that, to interleave read and write transactions in

a synchronous memory system, there must be an external clock signal to which all


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DRAM transactions are synchronized, and the controller issuing the read and write

requests must know the precise amount of time that will transpire between each

request and when a particular memory device will begin outputting or receiving the

requested data. (A115[15:63-16:10].) Their solution was to include a set of

internal registers, as shown in Figure 16, containing access-time registers 173

that specify delay times for each individual memory device:

(A107[Fig. 16].)

The 051 patent describes these access-time registers as follows:

With reference to FIG. 16, each semiconductor devicecontains a set of internal registers 170, preferablyincluding a device identification (device ID) register 171,a device-type descriptor register 174, control registers175 and other registers containing other informationrelevant to that type of device. In a preferred


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implementation, semiconductor devices connected to the bus contain registers 172 which specify the memoryaddresses contained within that device and access-timeregisters 173 which store a set of one or more delaytimes at which the device can or should be available tosend or receive data.


In a preferred embodiment, read and write requests are issued as part of a

request packet, as illustrated in Figure 4:

(A95[Fig. 4].)

Part of the request packet in Figure 4 is an AccessType field, which

indicates the type of request that is being issued, where different types of requests

may have different response timings when multiple access-time registers are

provided. (A112[9:57-59].) The 051 patent explains this concept as follows:


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The AccessType field [of the request packet] specifieswhether the requested operation is a read or write and thetype of access, for example, whether it is to the controlregisters or other parts of the device, such as memory. . . .

AccessType[1:2] preferably indicates the timing of theresponse, which is stored in an access-time register,

AccessRegN.


Thus, the 051 patent discloses a synchronous memory system having an

external clock signal that governs the timing of read/write requests and the

responses to those requests. In a preferred embodiment, when the memory

controller wishes to issue a read or write request to a particular memory device, it

assembles a request packet that includes the type of access. The timing of the

response by the memory device is known based on the value stored in the access-

time register that corresponds to the type of access specified (e.g., data for write

requests for this device should be sampled in X bus cycles). (A112[9:11-13].) In

this manner, once the write request has been issued, the controller knows that it has

exactly X bus cycles to process other memory transactions before the memory

device begins sampling data to be written. This allows for interleaving, which

improves the overall efficiency of the system. (A111[7:8-18].)

The 051 patent also explains how to choose and set appropriate access

times:

The value stored in a slave access-time register 173 is preferably one-half the number of bus cycles for which


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the slave device should wait before using the bus inresponse to a request. Thus an access time value of 1would indicate that the slave should not access the busuntil at least two cycles after the last byte of the request

packet has been received.

(A115[16:2-8].) Thus, the values stored in the access-time registers have a direct

correlation to the request-to-sampling access times they represent. For instance, in

the preferred embodiment, an access-time value of 1 represents two bus cycles,

while 2 represents four bus cycles, 3 represents six bus cycles, etc. ( Id. ) And, as

the above discussion makes clear, the access time represents the number of bus

cycles a memory device will wait (i.e., skip) before it begins accessing the bus to

respond to that request. (A115[16:5-8]; see also A111[7:8-18] (A request packet

and the corresponding bus access are separated by a selected number of bus

cycles . . . .).)

3. The Bennett Reference

a. Overview of Bennett

Bennett is a 396-page patent that nowhere discloses access-time registers or

the concept of a predetermined delay time between receipt of an operation code

and the sampling of data. Instead, what this voluminous document discloses is a

versatile bus interface for a mainframe computer system, circa 1982. (A1394.)


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A key component of Bennetts system is a Versatile Bus, which is the

primary bus that carries information and control signals to and from the various

user devices that are attached to it, as illustrated in Figure 1:

(A1395[Fig. 1].)

As its name suggests, the Versatile Bus in Bennett presents an overarching

protocol that can be configured in many different ways, resulting in what Bennett

calls stupendous versatility. (A1688[79:32].) In practice, the Versatile Bus is

configured using a configuration register that includes eight parameters (I through

VIII), each having the possible values set forth in Figure 3:


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(A1397[Fig. 3].)

Bennett explains Figure 3 as follows:

FIG. 3 shows an entire spectrum of possible parameterization of Versatile Buses. The left hand column, Configuration Digit, is an index number used tospecify a selection of a particular configuration value inone of the other columns I through VIII. For example, aconfiguration digit of 5 in the position of group linescolumn I specifies that 8 lines are used in an arbitrationgroup. A string of eight configuration digits willcompletely specify a Versatile Bus configuration. For example the string 43133355 specifies a Versatile Busconfiguration with four group lines, 2 multiplexed groups

using a (fixed priority) multiplexed scheme for theconduct of time-phased arbitration[,] two SlaveIdentification/Function lines, 2 Slave Identification/Function cycles, 1 wait line and 16 data lines . . . .


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(A1687[78:26-40].) Thus, Bennett discloses a single Versatile Bus that can be

configured many different ways. (A1688[79:32].)

The area below the dashed line corresponding to configuration 55255355 in

Figure 3 defines a preferred bus configuration envelope that Bennett considered

preferable. As Bennett explains:

[I]t must be recognized that this 55255355 Versatile Businterface envelope of the preferred embodiment of theinvention will support a great multitude of subsetinterfaces meeting the design rule. For example, the

Versatile Bus configurations of 42252255 shown inFIG. 32, 43112244 shown in FIG. 33, 52252355 shownin FIG. 35, and 43153352 shown in FIG. 36, will all besupported by 55255355 preferred embodiment VersatileBus interface envelope as incorporated in the preferred embodiment Versatile Bus Interface Logics chip design.

(A1687-88[78:68-79:10]; see also A1668[39:18-20] (There are 31,045 different

allowable configurations of the preferred embodiment of the invention.).)

Notably, Figure 3 is the only configuration matrix in Bennett ( see

A1660[24:25]), and it serves as a roadmap to understanding the entire universe of

Versatile Bus configurations. ( See A1688[79:27-33].)

b. The Role of Wait Lines in Bennett

Eight configuration parameters, each taking one of up to five preferred

configuration values, describe the overall operation of a given Versatile Bus

configuration. Of these, the sixth configuration parameter (i.e., parameter VI)

specifies the number and configuration of wait lines on the Versatile Bus. A


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wait line is a bus line that carries wait information. Wait information tells an

owner (e.g., a requester) whether a slave (e.g., memory) attached to the bus is

currently able to accept data in a particular transaction. (A1686[75:57-68].) As

Bennett explains:

[T]here are a lot of meanings that can be ascribed to thewait line, all generally subsumed under the concept that aslave device is unable, unwilling, or indisposed fromaccepting the data transfer activity within a transaction.

(A1686[76:21-24].) A slave drives a nonzero wait value onto a wait line to alert a

requester that data cannot presently be accepted by that slave for that particular

transaction and that the requester should therefore try again later. ( See id. ) Thus,

it is akin to a busy signal on a conventional telephone line, telling the caller to

try again later.

As shown below in red, in column VI of Figure 3, there are three options for

the number and configuration of wait lines in the preferred embodiment of Bennett

(below the dashed envelope line): one dedicated wait line (configuration digit =

3); zero wait lines (configuration digit = 2); or MPX, which stands for a

multiplexed wait line (configuration digit = 1). ( See A1686[76:1-4].) Note that

two or four wait lines are also possible (configuration digits = 4 or 5), but these are

not within Bennetts preferred envelope. (A1686[76:57-67].)


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(A1397[Fig. 3] (boxes added).)

In the first case described above (wait-line configuration digit = 3), the

system contains one dedicated wait line, separate and distinct from any other data

line. This means the slave for a given transaction can transmit wait information

simultaneously with the master transmitting data, since they are carried on

different lines. (A1687[77:40-43].) Like two cars passing on a two-lane road, they

can travel at the same time. In the second case described above (configuration

digit = 2), there are zero wait lines and, therefore, wait information is not used at

all. (A1694[92:46-51].) In the third case described above (configuration digit =

1), wait information is multiplexed with data on a single line, such that both wait

information and data share the line. In this case, although there is no dedicated


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wait line, the slaves still transmit wait information by alternating it with the master

data on a shared line. (A1687[77:40-43].) Like two cars passing on a one-lane

road, one must wait until the other has gone first. They cannot pass at the same

time.

c. Timing of Bus Activity in Bennett

The Boards decision refers to several timing schematics in Bennett,

including those illustrated in Figures 25 a , 25 b, 35, and 36. Each of these will be

discussed briefly below to provide context for the Boards decision.

i. Figure 36

Figure 36 of Bennett shows pin utilization and activity timing for an

operation Write conducted with a large memory across a 43153355 configuration

Versatile Bus. (A1661[26:55-57] (emphasis added to highlight parameter VI).)

By reference to Figure 3, this configuration is within the envelope of Bennetts

preferred embodiment. ( See A1688[79:4-10].) Notably, parameter VI in the

Figure 36 configuration is set to 3, indicating one dedicated wait line. Figure 36 is

reproduced below with annotations added to show the write instruction and the

commencement of data sampling in response to the write instruction. Note that

time transpires in the downward direction in this figure, with each horizontal row

representing one clock cycle.


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(A1418[Fig. 36] (annotations added).)

As shown above, and as the examiner found (A1148), in the write

transaction shown in Figure 36, two clock cycles elapse between receipt of the

write instruction and the commencement of data sampling (i.e., data sampling

begins on the third clock cycle after receipt of the write instruction). The two

intervening cycles contain the wait signal (WT in the figure above) and the

address bits for the location of the write request. Note that the number of address

bits is not established based on any value stored in a register on the large memory.

(A1696[96:33-42].)

The WT signal in Figure 36 provides the wait information for the recipient

memory slave. WT allows the memory slave to refuse or accept the transaction

writeinstr.

data


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based on the instantaneous conditions of the system, i.e., the slave need not sample

the data if it will not absorb it. ( See A1686[76:26-30] ([A] Wait signal simply

tells the User who is master that the currently outgoing data is failing to be

absorbed by at least one slave User device and that the master User should

(normally) try again after an interval to send the same data.); A1656[16:56-58].)

ii. Figure 35

Figure 35 of Bennett shows pin utilization and activity timing for a Read

conducted in a split command/response cycle to a large memory across a 52252355

configuration Versatile Bus. 3 (A1661[26:51-54] (emphasis added to highlight

parameter VI). By reference to Figure 3, this configuration is within the

envelope of Bennetts preferred embodiment. ( See A1688[79:4-10].) Notably,

parameter VI in the Figure 35 configuration is set to 3, indicating one dedicated

wait linethe same as in Figure 36. (A1695-96[94:61, 95:1-2].) Figure 35 is

reproduced below with annotations showing the receipt of the read instruction and

the commencement of data delivery in response to that instruction:

3 A similar split command/response cycle would occur for a Read-Modify-Write tolarge memory. ( See A1416[Fig. 34] (showing read, read-modify-write, and block read as split transactions).)


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At the top left of Figure 35, a transaction is initiated by a requester and

Requester Wins Arbitration. Bennett explains this arbitration process as follows:

The first activity occurring in a transaction is Arbitration.The purpose of Arbitration is to select one of the mastersconnected to the Versatile Bus to control the remainder of the transaction. The master so selected is called theVersatile Bus Owner for the remainder of the transaction.

(A1683[70:8-13].) When a master attempts to control a transaction on the bus but

loses an arbitration, it must wait and retry again until it eventually wins.

(A1683[70:51-54] (If the Master discovers it is not the winner [of arbitration], it

readinstr.

data

indeterminatememory delay


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removes any drive it has on the BUSY line and waits until it can begin a new

transaction as discussed above.).)

Referring again to Figure 35 above (moving downward in time), after

winning arbitration, the requester next instructs a large memory to address and read

a stored data word. (A1696[95:3-8].) At the moment the address is conveyed to

the memory, wait information (WT) is simultaneously transmitted from the

memory to the requester, indicating whether the memory is available.

(A1696[95:8-12].)

Referring again to Figure 35, after retrieving data from the specified address,

the memory must next arbitrate onto the bus (as a master) in order to transmit that

data back to the original requester. (A1696[95:18-20].) As indicated by the first

set of vertical ellipses between receipt of the address and the arbitration cycle,

there is no predetermined time in Bennett that dictates when the memory must

begin arbitration. Instead, these ellipses indicate that an indeterminate amount of

time transpires between when the memory receives a read request and when it first

begins attempting arbitration. Similar ellipses are used in other figures of Bennett

to denote the passage of an arbitrary amount of time. ( See, e.g. , A1412[Fig. 29].)

The arbitration process itself likewise results in an indeterminate amount of

time transpiring, as shown in Figure 35. Specifically, in the middle of the figure,

on the left-hand side, the large memory enters, and loses , Arbitration in a first


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attempt to respond to the requestor with the read word. (A1696[95:18-20]

(emphasis added).) This means that the memory was unable to gain control of the

bus to respond to the read instruction. It continues to try until, [f]inally, in a

subsequent transaction, the large memory finally wins an arbitration and transmits

a Slave Identification/Function to link and command the original requestor.

(A1696[95:20-24].) This is shown in the third row of Figure 35, beginning with

Memory Wins Arbitration. The vertical ellipses after the middle box labeled

Memory Loses Arbitration indicate that an indeterminate number of arbitration

attempts were made by the memory before success was finally achieved and the

data word was transferred. ( Id .)

It should be noted that a similar split command/response cycle, like that

shown in Figure 35 above, would also occur for a read-modify-write to Bennetts

large memory. As shown in Figure 34 of Bennett, a read-modify-write operation

to large memoryjust like a read operationinvolves two bus accesses, with the

memory arbitrating onto the bus after an indeterminate delay to deliver and sample

the requested data:

As shown in the above excerpt from Figure 34 (A1416), a read-modify-write


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to large memory in Bennett begins with the requester arbitrating onto the bus

(REQ. ARB.) and transmitting the memory identification, function code (2,

signifying a read-modify-write), and the memory address. Then, after an

unspecified period of time (see the first set of vertical ellipses in Figure 35 above),

the memory will attempt to arbitrate onto the bus (MEM. ARB.). As explained

above, this could take any number of clock cycles to complete (see the second set

of vertical ellipses in Figure 35 above). Once arbitration is successful, the memory

will then address the requester, deliver the requested read data (WD READ), and

sample the requested write data (WDS WRITTEN). Notably, this results in an

indeterminate number of clock cycles transpiring between receipt of the original

read-modify-write request and the sampling of data in response to that request.

iii. Figure 32

Although not discussed explicitly by the examiner or the Board, Figure 32 is

instructive in explaining the operation of wait lines in Bennett. 4 Figure 32 shows

pin utilization and activity timing for an operation Read or Write with a fast

memory across a 42252255 configuration Versatile Bus. (A1661[26:41-44]

(emphasis added to highlight parameter VI).) By reference to Figure 3, this

4 Figure 32 was discussed by the examiner and the Board in a related reexamination of U.S. Patent No. 6,266,285, an appeal of which is copending inthis Court. See Rambus, Inc. v. Micron Technologies, Inc. , Appeal No. 2013-1224(Fed. Cir.).


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configuration is within the envelope of Bennetts preferred embodiment. ( See

A1688[79:4-10].) Notably, parameter VI in the Figure 32 configuration is set to 2,

indicating that there is no wait line. Figure 32 is reproduced below with

annotations added to show the read/write request and the commencement of data

transfer in response to the read/write request.


As shown above, in the memory read or write transaction shown in

Figure 32, there are no clock cycles (i.e., no delay time) between receipt of the

read/write instruction (i.e., the OPERATION block in the above schematic) and

the commencement of data transfer. Data begins to be transferred on the very next

clock cycle after the read or write instruction is received.

Note that if Figure 32 were configured to use the same wait configuration (3)

as Figure 36 (i.e., a non-fast-memory arrangement), such that it exchanged wait

information at the same time as the data, the data timing would remain unchanged.

In other words, in that configuration, data in Figure 32 would still be transmitted

read/ write

instr.data


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on the next clock cycle after the read/write instruction because the wait

information would be transmitted simultaneously on the same clock cycle. Thus,

two bus configurations in Bennett with the identical wait-line setting in Bennett

will not necessarily have the same sampling delay (i.e., Figure 32 with a wait

configuration of 3 would sample data on the next clock cycle after the instruction,

whereas Figure 36 using wait configuration 3 samples data on the third clock cycle

after the instruction). Likewise, two otherwise identical bus configurations in

Bennett with different wait-line settings can nevertheless have the same sampling

delay (i.e., Figure 32 would have the same zero-clock-cycle delay whether the

wait-line setting were 2, 3, 4, or 5). These are important points supporting the

examiners finding that the wait-line configuration in Bennett is not

representative of the number of clock cycles that will transpire between an

operation code and the corresponding sampling of data. (A1149.)

iv. Figures 25 a and 25 b

Figures 25 a and 25 b of Bennett are part of a sequence of figures used to

show the relative order of operations in a generic bus transaction, not disclosed as

a memory transaction. (A1691[85:11-17].) Specifically, Figures 25 a and 25 b

show hypothetical transactions for two particular configurations of the Versatile

Bus differing only in that one has a multiplexed wait and data line (Figure 25 a ),

and the other has one dedicated wait line (Figure 25 b). Notably, as the Board


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conceded in a related proceeding, these figures depict only generic informational

transactions, not necessarily memory transactions. (A20181.) Moreover, the

illustrated transactions in these figures have been artificially simplified to

illustrate the sequence of operations. Specifically, as Bennett explains, to

simplify presentation of timing concepts [in these figures,] all . . . activities are

assumed to be but one cycle . (A1691[85:17-19] (emphasis added).) This

artificial assumption would not necessarily apply, however, to real-world memory

transactions in Bennett, such as those illustrated in Figures 35 and 36 (as explained

above).

Figures 25 a and 25 b are reproduced below, showing clock cycles T0, T1,

T2, etc., across the top:

(A1408[Figs. 25 a , 25 b].)

In Figure 25 a , the Versatile Bus configuration is completely pin

multiplexed: Arbitration, Slave Identification/Function, Wait and Data all transpire

upon the selfsame data pins (lines). (A1691[86:4-9].) In other words, although


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they are shown on separately illustrated lines in Figure 25 a , they are in fact

implemented on a single bus line where the first clock cycle corresponds to

Arbitration, the second to ID/Function, the third to Wait, and the fourth to Data.

Because of this (i.e., because all four activities are transmitted sequentially on the

same bus line), this configuration must, and does, accord separate cycles to the

four activities of Arbitration, Slave Identification/Function, Wait and Data . . . .

(A1691[86:9-14].)

As can be seen in Figure 25 a , in this hypothetical, simplified transaction,

there are a total of four clock cycles between the beginning of the generic

transaction at T0 and the end of the transaction at T4. (A1691[85:49-86:30].) And

there is one clock cycle between the end of the generic ID/Function transmission at

T2 and the beginning of data transmission at T3 (which, again, would not

necessarily be the case in a real-world memory transaction in Bennett, e.g.,

because real memory transactions require a memory address and may also require

a separate memory arbitration).

In Figure 25 b, the Wait line is not multiplexed. Instead, it is provided as a

dedicated line (i.e., parameter VI is set to 3 instead of 1). Because of this, the Wait

signal and Data can both be transmitted simultaneously during T2, since they are

being transmitted on separate lines. This, in turn, allows reduction in total

transaction cycle times from 4 clock cycles to 3 clock cycles, as compared to


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Figure 25 a . (A1691[86:39-41].) This hypothetical reduction (which, again, may

be completely obscured in a real-world memory transaction once other factors are

considered) results from the fact that wait information and data are transmitted

simultaneously, rather than being multiplexed as in Figure 25 a .

It should be noted that just because Data is transmitted in Figures 25 a and

25b does not mean a slave is actually receiving that data. As explained above, a

wait instruction generally indicates unavailability of the slave device(s) to

complete the requested transaction, necessitating that the master try again after an

interval to send the same data. (A1686[76:25-30].) Thus, just because data is

being transmitted on the Versatile Bus in Figures 25 a and 25 b, this does not mean

the data is actually being absorbed by the slave to which it is addressed. Instead,

it is up to the slave whether or not to sample the data based on the instantaneous

conditions of the system.

Moreover, because Figures 25 a and 25 b show only simplified generic

informational transactions (A20181), it is impossible to know how they would

relateif at allto an actual memory transaction such as those shown in Figures

35 and 36. In other words, because Figures 25 a and 25 b are so simplified and so

generic, they provide no information about the actual time that would transpire

between an operation code and later-sampled data in an actual memory

transaction, such as those shown in Figure 35 or 36.


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For example, Figures 25 a and 25 b do not show any address information

being sent across the bus, whereas an actual memory transaction would necessarily

include such address information. ( See A1416[Fig. 34]). In Figure 36, this address

information is provided over two clock cycles. But in Figures 25 a and 25 b,

because no address information is shown, it is impossible to know how much time

would actually transpire between a write request and data sampling, even assuming

memory accesses were possible with these hypothetical transactions.

Likewise, as shown in Figure 35, depending on the transaction, the memory

may need to separately arbitrate onto the bus, which may require many attempts

before it is finally successful ( see, e.g. , the second set of vertical ellipses in Figure

35). Thus, in an actual memory transaction in Bennett, regardless of whether a

dedicated or multiplexed wait-line configuration is used, the total time could be

many cycles before data is finally transferred in response to a request. ( See, e.g. ,

A1678[60:31-35] ( Many intervening Versatile Bus transactions later , the former

slave memory will successfully arbitrate onto the Versatile Bus as a master,

address and link the central processor, and send the requested read data.

(emphasis added)).)

4. The Examiners Finding that Bennett Does NotAnticipate Claim 27

After a thorough review of the record, the examiner concluded that Bennett

does not disclose a programmable register to store a value which is representative


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of a number of clock cycles of the external clock signal to transpire before

sampling a first portion of data. (A1142-49.) The examiner found that, although

a change in the wait-line value in Bennett (i.e., parameter VI) can affect the

number of cycles that transpire in a transaction, this does not mean the wait-line

value represents the number of clock cycles that will transpire before data is

sampled in response to an operation code:

[T]he Examiner notes that Figures 25a and 25b shows[sic] that a change in the configuration value changes the

number of clock cycles that transpire, however, the abovecitations shown in Bennett also makes it clear that theWait Line does not represent a number of clock cycles

but instead indicates whether data is accepted or whether th[ere] is a need to re-try at a later time. The Examiner notes that that [sic] based on the programmed configuration, the accepting or retrying causes data to besampled at different clock cycles, however while theconfiguration digit changes the number of clock cyclesthat must transpire, the configuration digit itself is notindicative of the number of []clock cycles that willhave transpired before data is sampled.

* * * *[F]igures 35 and 36, bring to light that the ConfigurationValue of Wait Lines is not representative of a number of clock cycles since the number of wait lines does notcorrelate to a specific number of clock cycles.

(A1148-49 (emphases in original).)

Based on this finding, the examiner correctly concluded that claim 27 is not

anticipated by Bennett. ( Id. )


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5. The Boards Decision Reversing the ExaminersFinding that Bennett Does Not Anticipate Claim 27

On appeal, the Board reversed the examiners finding of no anticipation and,

specifically, the finding that Bennett does not disclose a value which is

representative of a number of clock cycles. This was based in part on the Boards

implicit misconstruction of the term representative and also its fundamental

misunderstanding of Bennett.

The Board made no attempt to rebut that the same wait-line parameter in

Bennett results in different numbers of clock cycles transpiring in the transactions

shown in Figures 25 b, 35, and 36. Instead, the Board concluded that for any

single embodiment , knowing the configuration for that embodiment tells the

number of delayed clock cycles relative to the FUNCTION/WRITE command for

that specific configuration and embodiment. (A49 (emphasis in original); A63-

66.)

Despite referring to a single embodiment, the Boards analysis actually

focused on comparing two hypothetical, generic transactions in two different bus

configurations in Bennett (Figures 25 a and 25 b) and noting how the change in

wait-line value affects data timing within these hypothetical transactions. (A48.)

The Board acknowledged that claim interpretation was the crux of the issue here,

and it implicitly adopted a construction of representative that equates a change


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(i.e., a delta) in the number of clock cycles from one configuration to another with

the claimed representative value:

Despite a perceived distinction based on claiminterpretation, the Examiners cumulative finding thatBennetts Figure 25a and 25b embodiments (or configurations) disclose a change [which] isrepresentative by a change in one clock cycle ([A1149])constitutes a finding of anticipation of claim 27.

(A65 (first alteration in original).) In other words, the Board concluded that,

because a multiplexed wait-line configuration results in one extra clock cycle

compared to a dedicated wait-line configuration (i.e., X+1 instead of X), this

satisfies the representative limitation, even though X itself can vary from

transaction to transaction.

The Boards analysis failed to address the reality of Bennetts overall

system, where the timing of memory transactions depends on much more than the

wait-line configuration, including arbitration, the pin settings and address block

size, the memorys own behavior, and the instantaneous behavior of other actors

on the bus. None of these factors serve the purpose of an intentional, stored

number of clock cycles, as required in the claim-at-issue.

IV. SUMMARY OF ARGUMENT

The Board lacked jurisdiction to hear Microns appeal of the validity of

claims 27 and 43, and therefore should have dismissed the appeal. Although the

Board had the authority to merge the Samsung and Micron proceedings for


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procedural purposes, it did not have the authority to give Micron extrastatutory

rights that allowed it to appeal issues that were raised only in Samsungs

reexamination.

Even if the Board had jurisdiction over Microns appeal (which it did not), it

erred by reversing the examiners finding that Bennett does not disclose a value

which is representative of a number of clock cycles. The Boards analysis was

premised on an implicitly incorrect construction of representative, which

allowed the Board to conclude that, just because Bennetts wait-line configuration

can affect the number of clock cycles that will transpire, this necessarily means the

configuration is representative of the number of clock cycles that will actually

transpire. Under a proper construction of representative, no such conclusion can

properly be drawn. Moreover, the Boards factual findings lack substantial

evidence and are clearly rebutted by the examiners contrary findings.

V. ARGUMENT

A. The Board Erred in Determining that It Had Jurisdictionover Microns Appeal

1. 35 U.S.C. 315 Does Not Give a Requester the Rightto Appeal Issues Raised by Another Requester inAnother Reexamination, Even If the ReexaminationsAre Merged

Under 37 C.F.R. 1.989, the PTO may, in its sole discretion, choose to

merge two or more pending inter partes reexaminations relating to the same patent

into a consolidated proceeding. The sole statutory authority for this rule is


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35 U.S.C. 2(b)(2), which generally gives the PTO the authority to establish

regulations, not inconsistent with law, that govern the conduct of proceedings in

the PTO. Nothing in 35 U.S.C. 2(b)(2), however, permits the PTO to promulgate

a regulation that confers statutory rights upon a party that it would not otherwise

have absent the regulation. Consistent with this fact, the PTO has referred to

merger merely as a procedural housekeeping issue. (A20204.)

The statutory right of a third-party requester of an inter partes reexamination

to appeal to the Board is established by 35 U.S.C. 315, which states in relevant

part:

(b) Third-Party Requester .A third-party requester [of an inter partes reexamination]

(1) may appeal under the provisions of section 134 [tothe Board], and may appeal under the provisions of sections 141 through 144 [to the CAFC], with respect toany final decision favorable to the patentability of anyoriginal or proposed amended or new claim of the patent;and

(2) may, subject to subsection (c), be a party to anyappeal taken by the patent owner under the provisions of section 134 [to the Board] or sections 141 through 144[to the CAFC].

35 U.S.C. 315(b) (2002). 5

5 Because the inter partes reexaminations at issue in this motion were instituted before the America Invents Act (AIA), the statutes and rules in existence beforethe AIA should govern this issue.


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Notably, section 315 of the patent statute does not contemplate, suggest, or

otherwise encompass the concept of merged reexamination proceedings, since

merger of reexamination proceedings is a creature of PTO regulation, not statute.

Thus, when section 315 refers to any final decision in subsection (b)(1) and any

appeal in subsection (b)(2), it is referring to any final decision or appeal in the

particular reexamination that the third party actually requested . It does not, for

instance, give Party A the right to appeal a final decision in Party Bs separate and

wholly distinct reexamination proceeding, merely because both proceedings

involve the same patent. Nor does it give Party A the right to participate in an

appeal to the Federal Circuit taken by the patent owner from a different

reexamination requested by Party B, involving a different patent.

This is abundantly clear not only from the language of section 315 itself but

also from the context of the entire statute. See Kokoszka v. Belford , 417 U.S. 642,

650 (1974) (holding that, when interpreting a statutory provision, the whole

statute must be considered). Throughout the statutory sections that implemented

the inter partes reexamination procedure in 2000, as amended in 2002, there is an

obvious and inescapable assumption that references to any (e.g., any appeal,

any document, any communication) pertain only to a particular reexamination

requested by a particular third party, not to all reexaminations generally involving

the same patent or patent owner.


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For instance, section 314(b) states in part: With the exception of the inter

partes reexamination request, any document filed by either the patent owner or the

third-party requester shall be served on the other party. 35 U.S.C. 314(b)(1)

(2000) (emphasis added). Does this mean that, if Requesters A and B are both

involved in unrelated reexaminations against the same patent owner, the patent

owner must serve both requesters with all filed documents, even if the

reexaminations involve unrelated patents? The answer is obviously no, and neither

the PTO nor Micron has ever suggested otherwise. And yet that would be the

absurd result of applying the PTOs sweeping interpretation of any in section

315(b) to the other provisions of this statute. Cf. Sullivan v. Stroop , 496 U.S. 478,

484 (1990) ([I]dentical words used in different parts of the same act are intended

to have the same meaning. (citation omitted)).

Moreover, because section 315(b) is a statute that grants appeal rights to

third-party requesters in specific circumstances, it should be narrowly construed.

See Office of Senator Mark Dayton v. Hanson , 550 U.S. 511, 515 (2007)

([S]tatutes authorizing appeals are to be strictly construed. (citing Perry Educ.

Assn v. Perry Local Educators Assn , 460 U.S. 37, 43 (1983); Fornaris v. Ridge

Tool Co. , 400 U.S. 41, 42 n.1 (1970) (per curiam))).


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2. The PTOs Merger Procedure Cannot ConferStatutory Rights upon a Party that It Would NotOtherwise Have Had Absent the Merger

Rambuss argument is best illustrated by considering Microns right to

appeal to the Board under 35 U.S.C. 315 in two distinct circumstances: (1) absent

merger and (2) with merger.

Absent merger of the two reexamination proceedings under 37 C.F.R.

1.989, the Micron-requested proceeding would have continued on its own path,

separate and distinct from the Samsung-requested proceeding. In the Micron-

requested proceeding, the examiner would have ultimately rejected all of Microns

invalidity arguments, i.e., the proposed anticipation and obviousness rejections

based on Gustavson alone or with Bennett or Bowater. (A1189-90.) At that point,

the only issues Micron could have appealed to the Board and to this Court would

have been the examiners nonadoption of those proposed rejections. See 35 U.S.C.

315(b)(1) (2002).

In the nonmerger scenario, the Samsung-requested proceeding would have

likewise continued on its own separate path. The examiner in that proceeding

would have ultimately found claim 34 anticipated by Bennett and claims 27 and 43

allowable over Bennett, iAPX, Budde, iRAM, the JEDEC Standard, and Park.

(A1129-36; A1149; A1176-78; A1188.) At that point, Rambus would have

appealed the claim 34 rejection to the Board (as it did), and Samsung would have


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had the right (but for its earlier withdrawal) to appeal the examiners affirmance of

claims 27 and 43. But since Samsung had already withdrawn from the

reexamination proceeding, it would not have appealed. Therefore, the only issue

that would have been appealed to the Board in the Samsung-requested proceeding

would have been the rejection of claim 34, appealed only by Rambus.

In the nonmerger scenario, Micron would not have had any statutory right to

appeal anything in the Samsung-requested reexamination proceeding since Micron

was never a party to that proceeding. Thus, Micron could not have appealed the

examiners affirmance of claims 27 and 43 over Bennett, iAPX, Budde, iRAM, the

JEDEC Standard, and Park. As explained above, 35 U.S.C. 315 only gives third-

party requesters the right to appeal adverse decisions in the reexaminations that

they actually requested . There is no legitimate reading of the statute that would

have conferred on Micron the right to suddenly jump into Samsungs

reexamination proceeding and appeal issues to the Board that Micron never raised

in its own proceeding. Nor is there any legitimate reading of the statute that would

have given Micron the right to step into Samsungs shoes after Samsung withdrew

from its reexamination proceeding, such that Micron could have somehow become

the appellee in Samsungs reexamination proceeding, taking up Samsungs would-

be positions before the Board and this Court.


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Compare the nonmerger scenario to what actually occurred below, i.e.,

where the PTO sua sponte merged the Samsung-requested proceeding and the

Micron-requested proceeding pursuant to 37 C.F.R. 1.989. In this merger

scenario, according to the Boards logic, Micron was suddenly endowed with new

statutory rights. According to the Board, by mere virtue of the merger procedure

a regulatory creature solely of the PTOs makingMicron now had the right to

appeal issues it never raised in its reexamination request. According to the Board,

as soon as the two proceedings were merged, the scope of 35 U.S.C. 315

expanded such that Micron could not only appeal any final decision on issues it

had raised but also on issues that Samsung had raised. According to the Boards

logic, this significant expansion of Microns statutory rights occurred solely

because of the happenstance of the PTOs decision to merge the two proceedings.

As explained above, had there been no such merger, Micron would not have

enjoyed this alleged expansion of its statutory rights.

The problem with the Boards logic is that the PTO does not have the

authority to expand a partys statutory appeal rights in this manner. See

Koninklijke Philips Elecs. N.V. v. Cardiac Sci. Operating Co. , 590 F.3d 1326, 1336

(Fed. Cir. 2010) (The PTO lacks substantive rulemaking authority.); see also

Merck & Co. v. Kessler , 80 F.3d 1543, 1549-50 (Fed. Cir. 1996) ([T]he broadest

of the PTOs rulemaking powers35 U.S.C. 6(a) [now contained in 35 U.S.C.


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2(b)]authorizes the Commissioner to promulgate regulations directed only to

the conduct of proceedings in the [PTO]; it does NOT grant the Commissioner

the authority to issue substantive rules. (third alteration in original) (citation

omitted)); Tafas v. Doll , 559 F.3d 1345, 1356 (Fed. Cir. 2009) (explaining that

rules that foreclose effective opportunity to make ones case on the merits are

substantive (citation omitted)). Thus, the PTO cannot interpret its own merger rule

in a manner that would confer new substantive rights on Micron (e.g., the right to

appeal Samsungs proposed rejections) that Micron would not have enjoyed absent

the merger.

Indeed, in litigation, consolidation of two cases does not give any party

greater or lesser rights that it would have had absent the consolidation. See

Johnson v. Manhattan Ry. Co. , 289 U.S. 479, 496-97 (1933) ([C]onsolidation is

permitted as a matter of convenience and economy in administration, but does not

merge the suits into a single cause, or change the rights of the parties, or make

those who are parties in one suit parties in another.); New York v. Microsoft

Corp. , No. Civ. A. 98-1233, 2002 WL 318565, at *4 (D.D.C. Jan. 28, 2002)

([R]ather than merging the rights of the parties, consolidation is a purely

ministerial act which, inter alia , relieves the parties and the Court of the burden of

duplicative pleadings. Hence, the mere fact of consolidation does not allow one

party to take advantage of a rule applicable to the other party. (footnote omitted));


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S. Cal. Fed. Sav. & Loan Assn v. United States , 51 Fed. Cl. 676, 678 (Fed. Cl.

2002) ([Consolidation] does not expand this Courts jurisdiction, which is

narrowly defined and statutorily prescribed by Congress. Our jurisdiction cannot

be enlarged by rule.).

By the same token, Micron should not be permitted to appeal issues raised

only by Samsung merely because of the ministerial act of merger, which is a

creature of regulation, not statute. If the Boards decision were allowed to stand,

the PTO will have effectively enlarged Microns statutory rights to appeal by

administrative fiat, contrary to the spirit and the letter of the patent statute.

Moreover, it is worth noting that the Board correctly ruled on this issue the

first time it was raised, although it later reversed itself on reconsideration.

Specifically, in merged proceeding 95/001,026 and 95/001,128, the Board

originally ruled that, in a notice of appeal (or cross appeal), a requester is limited

to presenting rejections previously proposed by that third party requester .

(A20028 (emphasis in original).) That ruling was based on the Boards

interpretation of MPEP 2674(B), which states that [a] notice of appeal by a third

party requester must identify each rejection that was previously proposed by that

third party requester which the third party requester intends to contest. MPEP

2674(B) (8th ed. Rev. 7 July 2008). Rambus submits that the Board was correct


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in this ruling, not only based on MPEP 2674(B), but also on 35 U.S.C. 315

and 2(b)(2), as explained above.

Indeed, more recently, the PTO has further muddied its position in

reexaminations of other parties patents, stating that, although two inter partes

reexaminations were merged, [n]o inter partes requester has a right to comment

on any issue raised outside the confines of the statute, e.g. issues raised in . . . the

request and comments from another requester. (A20163.) The PTO has further

opined that, for appeals to the Board, each inter partes reexamination requesters

appeal must only be taken from the finding(s) of patentability of claims in the

[Right of Appeal Notice] that the individual third party requester proposed in the

request, and any that the individual third party requester properly added during the

examination stage of the merged proceeding. (A20163; compare A2369-70 (in

present merger, including no discussion of comment rights or appeal rights).) The

PTOs inconsistency on this issue demonstrates that this Courts guidance is badly

needed.

3. Because 35 U.S.C. 315 Clearly Sets Forth the Limitsof the Boards Jurisdiction, the PTO Is Not Entitledto Chevron Deference in Interpreting This Statute

The Supreme Court recently addressed Chevron de

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