Low Power-Area Designs of 1Bit Full Adder in Cadence Virtuoso ...
cadence virtuoso 9.5 - ECE:Course Page
Transcript of cadence virtuoso 9.5 - ECE:Course Page
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Layout with Cadence Virtuoso
Jonathan Chin18-322
September 5, 2002
Windows
Main Virtuoso Window
LSW (Layer Selection Window)
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CMOS Inverter
CMOS Inverter
NFET
PFET
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Layout Steps� Create N-Well� Add Power and Ground Rails� Add P-Islands and N-Islands� Add Poly for Gates� Make Source and Drain Connections� N-Well and Substrate Contacts� I/O, power and Ground Connections
Layout Steps� Create N-Well� Add Power and Ground Rails� Add P-Islands and N-Islands� Add Poly for Gates� Make Source and Drain Connections� N-Well and Substrate Contacts� I/O, power and Ground Connections
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Create N-Well
Layout Steps� Create N-Well� Add Power and Ground Rails� Add P-Islands and N-Islands� Add Poly for Gates� Make Source and Drain Connections� N-Well and Substrate Contacts� I/O, power and Ground Connections
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Power Rails
Layout Steps� Create N-Well� Add Power and Ground Rails� Add P-Islands and N-Islands� Add Poly for Gates� Make Source and Drain Connections� N-Well and Substrate Contacts� I/O, power and Ground Connections
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P-Island and N-Island
Layout Steps� Create N-Well� Add Power and Ground Rails� Add P-Islands and N-Islands� Add Poly for Gates� Make Source and Drain Connections� N-Well and Substrate Contacts� I/O, power and Ground Connections
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Add Poly for Gates
Poly strip for Gate of PFET
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CMOS Inverter propertiesPress �q� for properties
Gates Connected
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Layout Steps� Create N-Well� Add Power and Ground Rails� Add P-Islands and N-Islands� Add Poly for Gates� Make Source and Drain Connections� N-Well and Substrate Contacts� I/O, power and Ground Connections
Bulk, Source, Drain Connections
Used for N-well contact and NFET source or drain connection
(M1-N) metal1 contact N-island
= + +
Used for P-substrate contact and PFET source or drain connection
(M1-P) P-island
+ +=
metal1 contact
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Source & Drain Connections
PFET sourceconnection
NFET source connection
NFET drainconnection
PFET drainconnection
Layout Steps� Create N-Well� Add Power and Ground Rails� Add P-Islands and N-Islands� Add Poly for Gates� Make Source and Drain Connections� N-Well and Substrate Contacts� I/O, power and Ground Connections
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N-Well & substrate ContactsN-well contact
substrate contact
Layout Steps� Create N-Well� Add Power and Ground Rails� Add P-Islands and N-Islands� Add Poly for Gates� Make Source and Drain Connections� N-Well and Substrate Contacts� I/O, power and Ground Connections
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I/O and Power ConnectionsPoly to metal 1 connection (M1-Poly)
metal1 contact poly
Poly to metal 1 connection (M1-M2)
metal1 via metal2
Input is M1-M2 connection on top of M1-Poly connection
Output is M1-M2 Connection
+ +
+ +=
=
I/O and Power Connections� Vdd and gnd pins should be
made from metal1[pn]� Input and output pins can be
made from any [pn] metal layer, in this layout they are made from metal2[pn]
� Vdd and gnd pins should have I/O type of inputOutput
� The circuit input pin (A) should have I/O type of input while the output pin (Y) should have I/O type of output
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Inverter Layout complete!
Cell Instantiation� Cadence�s method of building with hierarchy� Remember our AND gate is built from a NAND gate and
an INVERTER� Simply instantiate them both to create the AND gate
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Cell Instantiation� Need to wire up the design and add new pins� Pins from lower level designs are essentially ignored by
Cadence when you instantiate them into larger layouts
� Path tool (p) � Very useful for making same layer connection across your design
� Contact tool (o) � useful for making connections between layers
� Zoom tools� Hold down right mouse button and draw a
square around the area you want to zoom into to zoom in
� Shift + z to zoom out� f to zoom out so your entire layout fits into view
� (if this command is acting weird run DRC).
� If caps lock is on you won�t be able to select anything in the LSW window.
Layout Shortcuts and tips