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EE5518

Digital Integrated Circuit Design

Cadence IC Design Manual

Revised by Gong Xiaohui & Li Xuchuan

July 2010

Department of Electrical & Computer Engineering

National University of Singapore

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Table of Content

1. INTRODUCTION 1

1.1 Overview of Design Flow........................................................................................................................1

1.2 Getting Start ...........................................................................................................................................2

2. SCHEMATIC ENTRY 3

2.1 Creating a Design Library.....................................................................................................................3

2.2 Creating a Schematic Cellview..............................................................................................................3

2.3 Adding Instances to Schematic............................................................................................................. 3

2.4 Adding Pins to Schematic ....................................................................................................................5

2.5 Adding Power Supplies to Schematic...................................................................................................5

2.6 Adding Wires to Schematic....................................................................................................................5

2.6 Saving a Design.......................................................................................................................................6

3. SYMBOL CREATION AND TESTING CIRCUIT 7

3.1 Symbol Creation ....................................................................................................................................7

3.2 Building Test Circuit .............................................................................................................................8

3.2.1 Creating an inverter_test Cellview... ..........................................................................................8

3.2.2 Building the inverter_test Circuit ..............................................................................................9

4. SIMULATE YOUR CIRCUIT 10

4.1 Start the Simulation Environment..................................................................................................... 10

4.2 Choosing a Simulator ..........................................................................................................................10

4.3 Choose the Desired Analysis................................................................................................................10

4.3.1 DC Sweep Analysis....................................................................................................................11

4.3.2 Transient Analysis.....................................................................................................................13

4.4 Saving Simulation Data........................................................................................................................13

4.5 Saving Outputs for Ploting .................................................................................................................14

4.6 Viewing the Netlists..............................................................................................................................15

4.7 Running the Simulation ......................................................................................................................15

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5. EXPLORING THE WAVEFORM WINDOW 16

5.1 Using the Waveform Window..............................................................................................................16

5.2 Modifying the Waveform Window Display .......................................................................................16

5.3 Setting Axes Options ............................................................................................................................16

5.4 Using Direct Plot...................................................................................................................................16

5.5 Annotating Simulation Results to the Schematic Window...............................................................17

5.5.1 Viewing your schematic design................................................................................................17

5.5.2 Annotating DC operating points .............................................................................................17

5.5.3 Annotating other information..................................................................................................17

5.5.4 Annotating DC voltages ...........................................................................................................17

5.5.5 Saving annotated labels ...........................................................................................................17

5.6 Analyzing Simulation Results..............................................................................................................17

5.6.1 Starting the calculator..............................................................................................................18

6. PYHSICAL LAYOUT 19

6.1 Starting Layout Editor ........................................................................................................................19

6.2 Layout Editor .......................................................................................................................................20

6.2.1 Creating Rectangles and Polygons...........................................................................................20

6.2.2 Using Rulers to Help Your Drawing.......................................................................................20

6.2.3 Adding Transistors....... .............................................................................................................22

6.2.4 Changing Shape.........................................................................................................................22

6.2.5 Creating Path.............................................................................................................................23

6.2.6 Creating Contacts......................................................................................................................23

6.2.7 Creating Pins ............................................................................................................................24

7. DESIGN VERIFICATION: DRC, EXTRACTION, AND LVS 26

7.1 Perform Design Rule Check ...............................................................................................................26

7.2 Extraction..............................................................................................................................................27

7.3 Layout Versus Extraction (LVS).........................................................................................................29

7.3.1 Start LVS ..................................................................................................................................30

7.3.2 LVS Output ...............................................................................................................................30

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7.3.3 Displaying the Errors ...............................................................................................................30

7.3.4 Re-Running Verification...........................................................................................................31

8. POST-LAYOUT SIMULATION 32

8.1 Simulating the Extracted Cellview......................................................................................................32

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1.  INTRODUCTION

This manual describes how to

North Carolina State Universi

procedures from schematic de

 1.1.  Overview of Design Fl

 This section describes the des

on various tools that assist yo

The design flow starts with in

–Composer. Devices from theschematics. Your design will

incorporate cells which you h

After you have finished desig

ensure it works as expected.

design exercise. In the case th

to iterate round the capture-si

 

Once your schematic design h

ready to start the physical des

placement. Once the cells hav

connectivity among the cells.

By finishing placing and routi

use Cadence IC design tools to implement your

ty Cadence Design Kit (NCSU CDK). It covers t

sign to post-layout parasitic extraction and simul

  w

ign flow that you will go through in this project,

in your design exercise. Figure 1-1 shows a typ

 Figure 1-1: A general design flow

putting schematics using the Cadence's schemati

NCSU_Analog_Parts library are used to constrube hierarchical. Therefore higher level schematic

ve already developed.

ing a particular component you will then have t

e shall be using the Cadence SpectreS simulato

at your component is not working as expected, y

ulate-debug loop to adjust your design.

as been properly adjusted to fit your expectation,

ign of the chip. The physical design starts with th

e been placed, routing can be carried out. Routin

ng, you need to do Design Rule Check (DRC) to

1 

esign with the

he design

ation.

with explanation

ical design flow.

capture tool

ct yours will also

simulate it to

during this

u will then have

you are then

e cells or devices

g adds

ensure that all

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design rules are met. In the next step, Layout-Versus-Schematic (LVS) check needs to be

performed as a verification that the layout corresponds to its original schematic, in terms of

connections and device sizes. After the LVS is performed, you need to do post layout simulation

to investigate the actual performance of your circuit.

1.2.  Getting Start

For this project, you can create a working directory under your home directory by typing:

cd

mkdir ee5518

Then, go to the working directory that you have created:

cd ee5518

In order to start cadence and use the techfiles, several start-up and configuration files are neededin your working directory. You can copy these file by typing the following command in your

working directory:

cp /proj2/pg9/p90282w/techfile/* ./

cp /proj2/pg9/p90282w/techfile/.cdsinit ./

cp /proj2/pg9/p90282w/techfile/.cdsenv ./

After copying these setup files, you need to set the design kit path:

setenv CDK_DIR /proj2/pg9/p90282w/CDK/ncsu-cdk-1.5.1

Each time you open a new terminal in Linux, you have to type the above setenv command, in

order to let cadence correctly load the NCSU design kit.

You can start Cadence system by typing:

icfb &

The workstation will now start up the Cadence system. A new window as in Figure 1-2 will pop

up. This is known as the Command Input Window or CIW.

 Figure 1-2: Command Input Window

Do not iconize CIW and try to keep it in view whenever you are using Cadence. Error messages

and outputs from some of the tools will be sent to the CIW. If something does not seem to be

working always check the CIW for error messages. In addition, the CIW allows the user good

control over Cadence by interpreting skill commands which are typed into it.

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2.  SCHEMATIC ENTRY

Before you start entering your schematics using Composer, you should first create a library in

which will be used to store all cells designed by you. You only need to do this once for the

whole design exercise. The following steps will show you how to enter the following schematic.

2.1.  Creating a Design Library

1)  In CIW, select File New Library.

2)  In the New Library form (Figure 2-1),

specify your preferred library name, e.g.

mydesign.

In the Technology File column, check the

following: Attach to an existing techfile.

Click OK  when done.

3)  In the Attach Design Library to

Technology File Form (Figure 2-2), select

 NCSU_TechLib_tsmc02 process

technology for our project, and click OK. 

 Figure 2-2: Attach Design Library to Technology File Form

2.2. 

Creating a Schematic Cellview

1)  In the CIW or Library Manager, select File    New    Cellview.

 Figure 2-3: Create New File Form

2)  Set up the Create New File form as follows: 

Library Name: (your previous library name, e.g. mydesign)

Cell Name: (your cell name, e.g. inverter )

View Name : schematic

Tool : Composer-Schematic

Click OK , and you will see a blank schematic window for the "inverter " (your cell name).

2.3.  Adding Instances To Schematic

1)  Add instances by placing cellviews from libraries.

Select Add    Component in the inverter schematic window or click on the Add Instance

 Figure 2-1: New Library Form

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icon on the left of the inverter schematic window (Figure 2-4) to display the Add

Component form.

 Figure 2-4: Icons and Bindkeys

In addition to pull down menu, you can directly

type "i" to bring up Add Component form. Thus

“i” is the "bind key" for Add Componentfunction in schematic editing. You can find other

bind keys on the right of each function button, as

in Figure 2-4.

 Figure 2-5: Component Browser

2)  Select NCSU_Analog_Parts in the Library field

in the Component Browser form. Click on

 N_Transistors for NMOS and P_Transistors forPMOS. We use nmos4 and pmos4 in the

schematic design of this project.

 Figure 2-6: Add Instance Form

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3)  Specify your device size in the Add Instance Form, and place your cursor on the schematic

editing window, you will be able to see your device. Click Rotate, Upsidedown, or Sideways

button to adjust the orientation of your device.

4)  To edit the properties of a device, single click on it and press “q”, or select Edit 

Properties Objects. Use the Edit Move command if you place your device in the

wrong location.5)  After you have entered all components, click Cancel in the Add Component Form or press

Esc with your cursor in the schematic windown.

2.4.  Adding Pins To Schematic

To add pins to define the external interface of the cell.

1)  Select Add Pin from inverter Schematic Window or click the Pin icon in the schematic

window, as in Figure 2-4. 

2)  In the Add Pin form, name your pin and select the correct direction (input, output, or

input/output) for it (Figure 2-7 ).

 Figure 2-7: Add Instance Icon

3)  Move you cursor to Schematic Window, place the pin. Right-mouse click to rotate the pin if

necessary.

Caution : Do not use the add component form to place schematic pins.

2.5.  Adding Power Supplies to the Cell

Adding power supplies takes the same steps as adding MOSFETs, except in the Component

Browser, select Supply Nets  vdd for the vdd net and Supply Nets  gnd for ground.

2.6.  Adding Wires to Schematic

Add wires to connect the components and pins in the design.1)  Select Add Wire (narrow) in Schematic Window or click the Wire (narrow) icon as in

Figure 2-4.

2)  In the schematic window, click on a pin of one of your components as the first point for

your wiring. A diamond shape appears over the starting point of this wire.

3)  Follow the prompts at the bottom of the design window and click left mouse key on the

destination point for your wire.

4)  Continue wiring the schematic. When all wiring is finished, press Esc with your cursor in

the schematic window to cancel the wiring command.

A completed schematic design of an inverter in shown in Figure 2-8

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 Figure 2-8: Inverter Schematic Design

2.7.  Saving A Design

To save your schematic design:

1) Click the Check and Save icon in the schematic window.

2) Observe the CIW output area.

Your design is now saved under the mydesign library.

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3.  SYMBOL CREATION AND TESTING CIRCUIT

3.1.  Symbol Creation

Create a symbol for your design so you can place it in a test circuit for simulation.

1)  In the inverter schematic window, select Design Create Cellview    From Cellview The

Cellview From Cellview form appears, as in Figure 3-1.

 Figure 3-1: Cellview From Cellview Form

2)  Click OK in the Cellview From Cellview form. A new window displays an automatically

created symbol, as in Figure 3-2. Observe the CIW output pane and note the messages

stating that an Analog Artist CDF was generated.

 Figure 3-2: Automatically Generated Symbol for Inverter

3)  You can modify the symbol to your preferred shape.

  Move your cursor over the symbol, until the entire green rectangle is highlighted. Click

left to select it.

  Click Delete icon in the symbol window to delete the green rectangle.

 

Select Add    Shape    Polygon. Follow the prompts at the bottom of the schematic,

and draw the triangle shown in the final picture.

  Click Move icon in the schematic window, move the Vinm, Vinp, Vbias, Vout, and

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[@instanceName] to its final destination.

  Select [@partName], and use Edit    Properties    Object to change value to

Inverter.

4)  Save your edited symbol view.

A final symbol is shown below in Figure3-3.

 Figure 3-3: An Inverter Symbol  

3.2.  Building Test Circuit

To build a circuit for schematic simulation of your inverter.

3.2.1 Creating an inverter_test Cellview

1)  In the CIW or Library Manager, select File    New    Cellview. Enter the following (Figure

3-4):

Library Name : mydesign 

Cell Name : inverter_test  

View Name : schematic

And Click OK

 Figure 3-4: Create inverter_test Schematic 

A blank schematic window for inverter_test appears.

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3.2.2. Building the inverter_test circuitYou may use the component list and Properties in the following table to build the inverter_test  

schematic.

Library Name Category Instance Parameters

mydesign - inverter -NCSU_Analog_Parts Voltage_Sources vdc DC Voltage = 3V

NCSU_Analog_Parts Voltage_Sources vpulse Voltage 1 = 0 V; Voltage 2 = 3V;

Delay Time = 3n s; Rise Time = 1f s;

Fall Time = 1f s; Pulse Width = 5n s;

Period = 10n s; DC Voltage = a V.

NCSU_Analog_Parts Supply_Nets vdd, gnd -

 Figure 3-4: inverter_test Schematic 

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4 SIMULATE YOUR CIRCUIT 

Before starting the simulation, make sure that the schematic in your library name is open, and

then perform the following steps:

4.1. Start the Simulation Environment. 

In your schematic window, select Tools → Analog Environment. The Analog Environment

Simulation window appears (Figure 4-1).

 Figure 4-1: Analog Design Environment 

4.2. Choosing a Simulator 

In the Simulation window, select Setup → Simulator/ Directory/ Host. A Choosing

Simulator window appears (Figure 4-2).

 Figure 4-2: Choosing Simulator 

In the Choosing Simulator window, make sure the Simulator field is set to spectre. The

Project Directory field shows the directory where the simulation data is stored. By default,

the simulation data is stored in client’s own directory.

4.3  Choose the Desired Analysis

The following analyses are available through the Analog Environment:

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4.3.1. DC Sweep Analysis

To perform DC sweep, the sweeping source needs to be set to variable. In the schematic window,

single click to choose the sweeping source. Press the Property button. In the popped-up window,

key in the variable name in DC Voltage field, as in Figure 4-3.

 Figure 4-3: Modify the Source for DC Analysis 

 Figure 4-4: Setting for DC Analysis 

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In the Analog Design Environment, select Variables Copy From Cellview, in the Design

Variables field, double click on the design variable a

In the Value field, enter the initial value and click the OK button, as in Figure 4-5.

 Figure 4-5: Setting Variable for DC Analysis 

In the Simulation window, click the Choose Analyses icon (Analyses →  Choose).

The Choosing Analyses window appears (Figure 4-6 ).

 Figure 4-6: Choosing Analyses Window 

In Analysis field, choose DC. In Sweep Variable field, choose Design Variable by

clicking on Select Design Variable. In Sweep Range field, key in the starting andstopping point of sweeping. Press OK to complete.

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4.3.2  Transient Analysis:

Specify a stop time in the Stop Time field. The internal engine time step is generally

a function of the interval you specify (Figure 4-7).

 Figure 4-7: Choosing Analyses Window 

4.4 Saving Simulation Data 

The Simulation environment is configured to save all node voltages in the design by default.

You can modify the default to save all terminal currents as well

 Figure 4-8: Selecting Currents as Simulation Outputs 

In larger designs, where saving all of the data requires too much disk space, you can select a

specific set of nodes to save. Following steps show you how to select terminals to save.

1. In the Analog Environment window, select Outputs →  Save All. 

The Save Options window appears.

2. Do not modify the form at this time.Leave the Save Options window configured to select all node voltages.

3. Click Cancel in the Save Options window.

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4. To select specific terminals for which you save the signal current, select Outputs → 

To Be Saved →  Select On Schematic in the Simulation window.

A prompt appears at the bottom of your schematic window.

5. In the schematic, click on the terminal pins.

A circle around each of the pins indicates that the signal current through the terminal

will be saved. (Figure 4-8 )

6. Press Esc with your cursor in the schematic window to cancel the selection process.

4.5 Saving Outputs for Ploting 

Select the nodes to plot when simulation is finished.

•  Select Outputs →  To Be Plotted → Select On Schematic. 

•  Follow the prompts at the bottom of the schematic window. Click on the node

labeled for input and output.

•  Press Esc with your cursor in the schematic window.

Now you have set up the simulation environment, you can save the simulator state, which

stores information such as the Model Path, outputs, analyses, environment options, andvariables.

In the Simulation window, to save the current simulation setting, select Session→ Save State.

A saving state window appears, in the Save As field, key in the state name and press OK 

button.

 Figure 4-9: Saving State Window 

A Saving State window will appear, fill in the file name, and then click OK. You can recall

your setting in the post-layout simulation stage by selecting

Session →  Load State …

 Figure 4-10: Loading State Window 

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4.6 Viewing the Netlists 

You can view informational netlists before simulating. To view raw netlist:

In the Simulation window, select Simulation →  Netlist →  Create. 

 Figure 4-11: CIW  

If there are any errors encountered during this step, check the messages in the CIW and

retrace your steps to see that all data was entered properly.

4.7 Running the Simulation 

Select Simulation → 

Run to start the

simulation or click on

the Run Simulation

icon in the Simulation

Window. After the

simulation is done, awaveform window will

pop up showing

simulation result, as in

Figure 4-12.

 Figure 4-12: Waveform Window Displaying Simulation Results 

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5 EXPLORING THE WAVEFORM WINDOW 

The Waveform window allows you to analyze the functionality of your circuit. To explore the

feature of the Waveform window, make sure the Waveform window is visible and displays the

results of the AC and Transient Analyses from the previous Section.

5.1 Using the Waveform Window 

Two different subwindows display information within the Waveform Window.

1.  Click left with your cursor in Subwindow 1 and note the number 1 highlight. Click the Strip

Chart Mode icon on the left side of the Waveform Window or select Axes→ To Strip. 

2.  Repeat this for the AC Response in subwindow number 2. Make sure that both plots are in

the Strip mode.

3.  Use markers to measure the output peak-to-peak amplitude of the transient output signal.

Select Marker Place, choose the suitable marker for measurement.

4.  To zoom in, move the cursor to the target place, right click and hold the mouse, drag the

cursor to define the place for zoom.

5.2 Modifying the Waveform Window Display 

You can change the display in the Waveform window to highlight and isolate specific

information.1. Double click on the number which you want in the Waveform Window to bring up the

Subwindows form. Once this form is up, you can modify the property of subwindows.

2. Next, double click on the waveform for /vin to display the Curves form. You can also

Click on the /Out waveform or select Curves → Edit to do the same thing. The Curve formappears. With this form, you can change the scale, change the color of the curve, or the shape

of the tick mark.

5.3 Setting Axes Options 

Axes option let you select Axis type (rectilinear or Smith), single or multiple Y-axes, and plot

versus independent variables. You can also change other display attributes of the axes. The

axes commands always apply to the currently selected subwindow.

1. Double click the Y-Axes label, to bring up the Y-Axes options form. You can also

use the Axes →  Y-Axes command.

2. Double click the X-axis label, to bring up the X-Axis options form. You can also use the

Axes → X-Axes command.

5.4  Using Direct Plot 

The direct plot function lets you easily choose signals from your design and plot them

directly. This is very useful in debugging a design while you view the waveforms at different

nodes in your circuit.

1.  In the Analog Environment window, select Results → Direct Plot → Transient

Signal/Transient Signal Minus DC/ Transient Sum/ Transient Difference/ AC

Magnitude/AC Phase/AC Magnitude & Phase/AC Difference/Equivalent Output

Noise/ Equivalent Input Noise/ Noise Figure/ DC/ S-Parameter…./ XF…/ PSS…/

SPSS…. 

2.  Follow the prompts at the bottom of your schematic window and select the node labeled for

output.

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5.5 Annotating Simulation Results to the Schematic Window 

This annotated display is useful for documentation purposes and provide a good picture of

how the circuit is functioning.

5.5.1 Viewing your schematic design 

1. In your schematic window, select Design → Hierarchy →  Descend Edit. 

2. Follow the prompt in your schematic window and select your design instance.

The Descend form appears.

3. Set the View Name in the form to schematic and click OK. 

Your schematic appears.

5.5.2 Annotating DC operating points 

In the Analog Environment window, select Results → Annotate → DC Operating Points. DC

operating point data appears near every component in your schematic window.

5.5.3 Annotating other information 

You can annotate model parameters too.

In the Simulation window, select Results → Annotate → Model Parameters. 

5.5.4 Annotating DC voltages 

1. In the Simulation environment window, select Results → Annotate → DC Node Voltages. 

2. In your schematic window, select Window → Redraw or press the F6 key with your cursor

in the schematic window. Transient voltage data appears near every component pin in the

design window. Other operating point labels might be visible as well.

5.5.5 Saving annotated labels 

Annotated label displays are lost when you exit the Analog Artist environment, unless you

made the changes at the instance level.

In the Edit -> Component Display form, click the Save button. The Save Label Display form

appears. The Save command saves the label display information in the file listed in the form.

5.6 Analyzing Simulation Results 

The Waveform Calculator is a tool for you to analyse your simulation results. With the

Calculator, you can:

  Build, print, and plot expression containing your simulation output data.  Build expressions to be used with labels in the Waveform Window.

  Enter expressions, which can contain node voltages, port currents, operating points, model

parameters, noise parameters, design variables, mathematical functions, and arithmetic

operators, into a buffer.

  Store the buffer contents into a memory and then recall the memory contents back into the

buffer.

  Save calculator memories to a file and load those memories back into the calculator

The  Analog Environment  Help  has more instructions concerning calculator usage andfunctionality.

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5.6.1 Starting the Calculator 

Make sure that the schematic window, Analog Environment window, and Waveform

window are open.

1. 

In Analog Environment window, select Session -> Option, in the popped up optionwindow, select AWD in the Waveform Tool field.

2.  Plot the outputs. The output is plotted in AWD window.

3. In the Waveform Window, click the Calculator icon.

4. The Calculator comes up in the default mode, which is set to RPN or ReversePolish Notation.

5. Turn on the Display Stack button.

The Calculator stack appears. Move the Calculator window to see the stack.

6. Click the vt button (volage transient) in the Calculator and follow the prompt at the

bottom of the schematic window or CIW.

7. Select the out node of the circuit. Then press Esc with your cursor in the schematic

window.

8. Click erplot (erase and plot) in the Calculator.The Waveform window displays the transient voltage at the output node. This is an erase

and plot function, which erase the Waveform Window before plotting the signal in the

Calculator buffer. 

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6. PYHSICAL LAYOUT

6.1．．．．  Starting Layout Editor

If your Command Input Window (CIW) is closed, typing icfb & again under the ee5518

directory will open the CIW.

To create a layout named "inverter " in "mydesign" library,

1)  In CIW, select File New Cellview ...

2)  Selct "mydesign" as Library Name; enter "inverter " as Cell Name, "layout " as View Name;

select "Virtuoso" for Tool then click "OK" (Figure 6-1).

 Figure 6-1: Create Layout 

Cell "inverter " with "layout " view in library "mydesign" will be

created and opened. There will be an “LSW” window on the left hand

side, as in Figure 6-2. LSW stands for Layer Select Window, which

displays the colors and corresponding names of all layers defined in

the technology.

You might notice that some layer names appear more than once inLSW. For example “metal1” appears twice in LSW: first one as

“metal1 drw”, second one as “metal1 net”. metal1 drw is the Metal 1

layer for drawing purpose: a layer for drawing purpose define the chip

area on which the layer will physically reside. metal1 net is the layer

for net marking: a layer for net marking is not a physical layer, it

should be drawn within the boundaries of drw layer to define the net

name. net layers are usually used to define I/O pins.

The position of the cursor in layout editing window is indicated by the

coordinate displayed on the upper left corner of the window after X: 

and Y:. The unit here is "µm". Move your cursor around the editing

window and see the X: Y: values change with step size 0.1.

To change the step size:

1)  From Virtuoso Editing window pull down menu, select

Options    Display... to open the "Display Options form".

2)  In Display Options form, Change "X Snap Spacing" and "Y Snap Spacing" to your desired

values.

You can zoom in and zoom out by clicking Window Zoom    Zoom out by 2 / Zoom in by 2,

or simply press the bindkeys “ctrl + z” and “shift + z” to zoom in and out.

You can press “f ” to let your layout “fit” your window.

 Figure 6-2: Layer

Select Window 

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 Figure 6-3: Display Options Form 

To save and close the cell view: from Virtuoso Editing window, select Design    Save, then

Window    Close.

6.2. Layout Editor

In this section, the layout for cell "inverter " is designed using Cadence Layout Editor.

If you have closed the layout view of inverter in section 6.1, you need to open "inverter" layout

view for editing: in Library Manager window or CIW, click on "mydesign" "inverter " 

"layout ".

6.2.1. Creating Rectangles and Polygons

The most common shape in a layout is rectangle. To draw rectangles

1)  From LSW select a layer by clicking on it. You will see the selected layer highlighted.

2)  From Layout Editing window pull down menu, click left to select Create Rectangle, or

press the bindkey “r”.

3)  In the layout design window click on the first corner of the rectangle, and then click on the

opposite corner. A rectangle is formed.

4)  If this is not the rectangle you want, from menu select Edi Undo to undo the action.

5)  If you want to draw rectangles on another layer, in LSW click on the layer to change the

drawing layer then click left on the two corners.

6) 

If you have finished drawing rectangles, hit “Esc” on the key board to exit from "Create

Rectangle" command.

You can use Create    Polygon to create other shapes. The procedures are the same as creating

rectangle.

6.2.2 Using Rulers to Help Your Drawing

You may notice that there is a ruler icon at the bottom left of the Layout Editing Window. Click

it, or press bindkey “k”

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 Figure 6-4: Create Rulers 

Ruler is a handy function in drawing layout, as most design rules are stated with regard to

distances and diameters. A well-planned and well-measured layout will save your time of

debugging after Design Rule Check (DRC).

Press bindkey “shift + k” to clear all rulers.

 Figure 6-5: Add Transistors 

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6.2.3. Adding Transistors 

You need one NMOS and one PMOS to construct the inverter . NCSU design kit has provided

layouts for MOSFETs, which you can directly include as cells into your layout.

1)  In Layout Editing window, click on Add Instance icon (Figure 2.4) or press bindkey “i”.

2)  In Create Instance form, as in Figure 6-5, set as below:

Library: NCSU_TechLib_tsmc02Cell: pmos for PMOS, and nmos for NMOS

View: Layout

You can select your own value of length, width, and number of fingers for the MOSFETs.

A layout after both transistors are added is shown in Figure 6-6 . You may need to press “shift +

f ” to view the devices.

 Figure 6-6: Layout with A MOS Pair

6.2.4 Changing Shape

After you created the rectangles/polygon/transistors, you may want to relocate or resize yourdevice. You can do so by using Edit    Move/Stretch/Reshape commands to change the

location or size of the shape.

To rotate a rectangle/polygon/transistor 90 

1) Select Edit Move.

2) Move your cursor to the device, click left mouse once to select the device, then click

right mouse once to turn the transistor 90 (or double click middle mouse to bring the

Move form, and click on Rotate/Sideways/Upsidedown button).

To Stretch the shape:

1) Select Edit    Stretch

2) Left click once on the edge of the shape you want to stretch

3) Move your cursor to the new location, left click again to complete the stretch

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To Reshape the shape:

1) Select Edi    Reshape

2) Move your cursor to the shape, and click once to select it

3) Draw the new shape.

4) Follow the instruction on the bottom of the window to complete the reshape

6.2.5. Creating Path

To connect the transistors together, you need to draw paths (“wires”).

1) Select metal1 from LSW.

2) Select Create    Path, or press "p".

3) Point your cursor to the first point and click once.

4) Point to the next point, and single click to make a turn.

5) To finish creating path, double click on the end point.

6) To change the width of a path, single click on the path and press “q”. In the Edit Path

Properties form, you can change the value of Width.

 Figure 6-6: Edit Path Properties Form

6.2.6. Creating Contacts

Contacts are used to interconnect different layers.

1) Select Create    Contact, or press bindkey "o" to bring up the Create Contact form.

2) Select your Contact Type, number of Rows and Columns (Figure 6-6 ).

 Figure 6-6: Create Contact Form

3)  Place the contact onto your layout (Figure 6-8 ).

In our inverter design, the body of PMOS is attached to Vdd and the body of NMOS is attached

to Gnd. In layout, these connections are accomplished by connecting the body of PMOS (nwell)to the vdd! node/pin, and connecting the body of NMOS (p substrate) to gnd!. A common

practice is to use multiple metal-nwell and metal-substrate contacts to decrease the contact

resistance and improve the transistor performance. An example is illustrated in Figure 6-8 .

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6.2.7. Creating Pins

As in schematic design, a layout cell needs I/O pins to define its output interface, and thus its

connectivity with external cells. To create pins:

1)  In LSW, single click on the net  layer of your corresponding drawing layer on which you plan

to put your Pin. If you need the pin on poly layer, for instance, you should click on poly net  

in LSW. 2)  Select Create    Pin to bring out a Create Symbolic Pin form. You will be using shape pins

in the inverter , not symbolic pins. Select "shape pin" in the Mode field, then a Create Shape

Pin form comes out, as in Figure 6-7. 

 Figure 6-7: Create Shape Pin Form

3)  Type in your Terminal Names, I/O Type, and tick rectangle and Display Pin Name for this

project.

4) 

Draw the rectangular pin on the path/area which resides within a corresponding drawinglayer (Figure 6-8 ).

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 Figure 6-8: A Completed Layout of Inverter

You have just finished the design of your inverter layout. You need to save it by selecting Design

    Save.

metal1.net layer to

define vdd! pin

poly.net layer to

define Vin pin

M1-N contacts to

attach the body of

PMOS to Vdd

M1-P contacts to

attach the body of

NMOS to Gnd

Extended nwell region

to allow the drawing of

M1-N contacts

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7. DESIGN VERIFICATION: DRC, EXTRACTION, AND LVS 

Design Rule Check (DRC), Extraction and Layout-versus-Schematic (LVS) are tools to verify

with design rule, to extract parasitic information, and to verify layout wire routing with respect

to schematic design, respectively.

7.1. Perform Design Rule Check 

During and after the layout of inverter  is completed, it has to be verified conforming to a

complex set of design rules, in order to ensure a lower probability of fabrication defects. A tool

built into the Layout Editor, called Design Rule Checker, is used to detect any design rule

violations in the layout design. The detected errors are displayed on the layout editor window as

error markers, and the corresponding rule is also displayed. Designers are suggested to perform

DRC frequently during the layout design, especially in large scale circuits. In addition, it is

usually expected that all layout errors are eventually removed from the mask layout, before the

final design is saved.

Now you are going to verify the inverter layout by Design Rule Checker (DRC). You are

expected to have basic understanding about design rules. To perform DRC:

1)  In Layout Editing Window, select Verify DRC... This brings out a DRC from.

 Figure 7-1: DRC Form

2)  Check the Rules File is "divaDRC.rul", and Rules Library is "NCSU_TechLib_tsmc02".

3)  Click OK on DRC form.

4)  Check your CIW to see the DRC results. It takes a while to check all the DRC rules definedin the technology files. After DRC checking is done, DRC errors will be highlighted in the

layout window. You can get explanation on each highlighted error.

To get explanation on an error:

1)  In Layout Editing Window, select Verify→ Marker→ Explain 

2)  Then single click on the highlighted error area. This brings out a marker text window with

explanation (Figure 7-2)

.

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 Figure 7-2: Marker Text Window

To locate a particular error:

1)  From Layout Editing Window, select Verify→ Marker→ Find to open a Find Marker

form.

 Figure 7-3: Find Marker Window

2)  Tick Zoom To Markers option, then click Next. A marker text window with explanation will

pop up, at same time the layout window will zoom to the error.

To delete all markers, select Verify→ Marker→ Delete All

Modify your layout until there is no error warning in DRC.

7.2. Extraction 

Circuit extraction is performed after the layout is DRC error clean. It is used to create a

detailed net-list (or layout description) for the simulation tool. The circuit extractor is capable

of identifying the individual transistors and their interconnections (on various layers), as well as

the parasitic resistances and capacitances that are inevitably present between these layers. Thus,

the "extracted net-list" can provide a very accurate estimation of the actual device dimensions

and device parasites that ultimately determine the circuit performance. The extracted net-list

file and parameters are subsequently used in Layout-versus-Schematic (LVS) comparison and

post-layout simulation.

To generate the extracted view:

1)  In Layout Editing Window, select Verify→ Extract... 

2)  An Extractor form appears

3)  Make sure Extract Method is "flat", Rule File is "divaEXT.rul" and Rule Library is

"NCSU_TechLib_tsmc02".

4)  Click on “Set Switches” button, and choose “Extract_parasitic_caps”, as in Figure 7-4.

Click OK.

5)  Cadence extractor will extract the layout and save it as extracted view. You can see the

extracted view appears in the library Manager window under "inverter".

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 Figure 7-4: Extractor Form

To open the extracted view of "inverter": in Command Input Window (CIW) select Tools→ 

Library Manager …

Find the extracted view of inverter, as in Figure 7-5, and open it.

 Figure 7-5: Extractor Form

You may need to press “shift + f ” view devices. The extracted view contains the actual

devices that are recognized from the layout. Figure 7-6  shows that besides the PMOS and

NMOS, parasitic capacitances are recognized. These parasitic devices are expected to affect the

performance of our design. Thus, the extracted inverter  will provide a more “real” performance

than the schematic inverter .

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 Figure 7-6: Extracted View of Inverter

7.3. Layout Versus Schematic (LVS) 

After the extracted view is created, the

design should be checked against the

schematic circuit description created earlier.

The design called "Layout-versus-Schematic

(LVS) Check" will compare the original

schematic circuit with the one extracted

from the mask layout, and help to verify

that the two circuits are indeed equivalent.

The LVS step provides an additional level of

confidence for the integrity of the design,

and ensures that the mask layout is a correct

realization of the intended circuit topology.Note that the LVS check only guarantees

topological match: a successful LVS will

not guarantee that the extracted circuit will

actually satisfy the performance

requirements. Any errors that may show up

during LVS (such as unintended connections

between transistors, or missing

connections/devices, etc.) should be

corrected in the mask layout - before

proceeding to post-layout simulation. Also note that the extraction step must be repeated every

time you modify the mask layout.

 Figure 7-7: LVS Form

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7.3.1. Start LVS

1)  In the Extracted cellview window, select Verify→ LVS, the LVS form appears as in

Figure 7-7 .

2) 

Make sure the "schematic" and "extracted" buttons are checked, and the following fields arefilled correctly.

schematic extracted

Library mydesign mydesign

Cell inverter Inverter

View schematic extracted

Rules File: divaLVS.rul

Rules Library: NCSU_TechLib_tsmc02

3)  Click on Run.

4)  A while later, an LVS message window will pop up informing you that the LVS is

completed. If your job does not get completed, click on Info in the LVS form and read thelog for any error.

7.3.2 LVS Output

To view LVS result:

1)  In the LVS form (Figure 7-7 ), click on Output.

2)  A text window listing the output from the LVS run appears. Scroll until you see the section

that compares the layout and schematic. LVS reports this information: The net-lists failed

to match. (Figure 7-8 ).

3)  This section will tell you whether your instances, nets, and terminals are matched between

schematic and layout. If all instances, nets and terminals are matched, you can skip the next

section (section 7.3.3).

 Figure 7-8: LVS Output 

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7.3.3. Displaying the errors

To display the errors founded in LVS:

1)  In the bottom of the LVS form, click on Error Display. The LVS Error Display form

appears as shown below in Figure 7-9.

 Figure 7-9: LVS Error Display Form 

2)  In the LVS Error Display form, tick the Auto-Zoom button. Then click on First, this brings

you to the zoomed-in view of first error in the Layout Editing window.

3)  Click on Next to find next error.

4)  Repeat Step 2 until you find all errors.

5)  Click on Clear Display. This will clear all error highlighted in layout window.

If you want to see the errors in the schematic window, move your cursor to Schematic window

and click once. Then follow the Step 2 to 5.

7.3.4. Re-Running Verification

After you correct all errors in the layout, you need to run verification again. The steps are

identical to those you followed earlier in this chapter. The final design should be free from any

verification errors.

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8. POST-LAYOUT SIMULATION

The electrical performance of a full-custom design can be best analyzed by performing a post-

layout simulation on the extracted circuit netlist. At this point, the designer should have a

complete mask layout of the intended circuit/system, and should have passed the DRC and LVS

steps with no violations. The detailed (transistor-level) simulation performed using the extracted

net-list will provide a clear assessment of the circuit speed, the influence of circuit parasitics

(such as parasitic capacitances and resistances), and any glitches that may occur due to signal

delay mismatches.

If the results of post-layout simulation are not satisfactory, the designer should modify some of

the transistor dimensions and/or the circuit topology, in order to achieve the desired circuit

performance under "realistic" conditions, i.e., taking into account all of the circuit parasitics.

This may require multiple iterations on the design, until the post-layout simulation results

satisfy the original design requirements.

Finally, note that a satisfactory result in post-layout simulation still has no guarantee for a

completely successful product; the actual performance of the chip can only be verified by

testing the fabricated prototype. Even though the parasitic extraction step is used to identify the

realistic circuit conditions to a large degree from the actual mask layout, most of the extraction

routines and the simulation models used in modern design tools have inevitable numerical

limitations. This should always be one of the main design considerations, from the very

beginning.

8.1. Simulating the Extracted Cell View

After a successful LVS, you will have two cellviews that can be simulated. The first one is the

schematic, which is your initial (ideal) design, the second is the extracted, that is based on the

layout and in addition to the basic circuit includes all the layout associated parasitic effects.

Since both of these views refer to the same circuit they can be interchanged.

In this chapter, you are going to re-run the simulation for "inverter", but we will make the

simulator to use the extracted cellview instead of the schematic cellview, as in Chapter 4.

The procedure of running post-layout simulation is the same as in Chapter 4, except one

additional step to take:

1)  After you start the Analog Artist Simulation window from the testing schematic

inverter_test , choose Setup  Environment option in the Analog Artist Simulation

window.

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 Figure 8-1: Environment Options 

2) 

As in Figure 8-1, there is a “Switch View List”. This entry is an ordered list of cellviewsthat contain information that can be simulated. The simulator (netlister) will search until it

finds one of these cellviews.

3)  The default entry does not contain an extracted cellview. You need to add an entry for

“extracted” cellview in front of the “schematic” cellview.

4)  As a result of this modification, the simulator will use the extracted cellview of the cell, if

available. The final form is like Figure 8-1.

5)  Click OK .

From this point on you can perform the same simulations as in Chapter 4. The simulator will

now include parasitic effects from the actual layout.