EE/CE 4325/6325 VLSI Design

Introduction to CAD Tools

By Akshay Sridharan

akshay.sridharan@utdallas.edu

Outline

VLSI design flow

Basics of UNIX / Linux

CADENCE

HSPICE

VLSI Design Flow

Project 1: Verilog/ VHDL design (Xilinx, ModelSim)

Project 2: Synthesis using Synopsys (DesignVision)

Project 3, Project 4, Project 5 : Standard cell library design

(Cadence, hspice, Siliconsmart ACE)

Project 6: Automatic P&R and Timing Analysis

(Encounter, PrimeTime)

UNIX / Linux commands File Management

ls list contents of directory ls -al formatted listing including hidden files cd dir navigate to directory dir cd cd ~/ Navigate to home pwd list present working directory mkdir dir create a new directory named dir cp file1 file2 copy file1 to file2 cp r dir1 dir2 copy dir1 to dir2 mv file1 file2 rename of move file1 to file2

Process Management ps display active processes kill pid kill the process corresponding to pid bg list background processes, resume a stopped job in the background

UNIX / Linux commands contd.

Shortcuts ctrl+c kills the current process.

ctrl+z halts the current process

fg run the process in foreground

bg run the process in background

man commandlists unix manual for unix command.

Servers for CAD tools Use only engnx1-10 via Nomachine only!!(NX client)

all tools and setup have been setup to work correctly here.

Do not SSH from Xmanager. You will be kicked out.

Refer my website for proper connection, can also been connected remotely using UTDVPN.

http://utdallas.edu/~akshay.sridharan/index_files/Page3860.htm

CAD Directory Structure

Home

cd ~/

/home/eng/a/axs109221

Root

/

Home

cad

cd cad

cadence siliconsmart Primetime se synopsys spice

Icfb Layout Schematic DRC/LVS/QRC

Library characterization

Encounter P&R

Design Vision Lc_shell,

design_vision

Hspice

CAD Terminologies Cadence

Views Schematic

Layout (DRC/LVS/RCX or PEX)

Symbol

Abstract

Verilog/ Synopsys Behavioral/ RTL netlist

Synthesized/ mapped / gate level netlist

Spice (hspice) RC Extracted netlist

Schematic netlist

Cadence Views

Layout

Schematic Symbol

Top View of Transistors

More Cadence Terminology

More Cadence Terminology

Design Rule Check (DRC)

Layout Versus Schematic (LVS)

Layout Versus Schematic (LVS)

Pitch Size/ IO Pin Spacing

Cadence Shortcuts

Final Layout Examples

A die photograph post fabrication

EE 6325 Final Design Actual final design

Core Design

I/Os

Hspice To Run Hspice:

1. Source ./proj/cad/startup/profile.synopsys_2013

2. Type hspice file_name.sp

3. Check the terminal for any warnings and or errors. If you see "job concluded", then the run was successful

your simulation waveform result is stored in file_name.tr0

4. Use waveview to view the waveforms Type

wv file_name.tr0 &

Hspice contd. First line must be a comment or can be an empty line Hspice is case insensitive and will convert all to lower case

So INV.sp=Inv.sp=inv.sp

Need to include transistor model card for simulation. .include/home/cad/kits/IBM_CMRF8SFLM013/IBM_PDK/cmrf8sf/relLM/HSPICE/models/model013.l

ib_inc

Need to include the spice netlist .include inv.sp (E.g. The netlist for an inverter)

Instantiation: xinv in out inv (INV Gate with Input-in, Output-out

The port order is important, should follow inv.sp

Parameter definitions .param VDD=1.2V

Power Supplies vdd vdd! gnd 1.2V

Transient Simulation Tran 10ps 10ns

Run a transient analysis for 10 ns with a step size of 10ps.

Delay Measurements Fall delay

.measure tran Tphl_out trig v(in) val ='VDD/2' rise=1 + targ v(out) val ='VDD/2' fall=1

Rise delay .measure tran Tplh_out trig v(in) val ='VDD/2' fall=1 + targ v(out) val='VDD/2' rise=1