Semiconductor Materials and Device Laboratory

Jong-Ho Lee

jhl@snu.ac.kr

School of EECS and ISRC, Seoul National University

Bulk FinFETs: Fundamentals, Modeling, and Application

1

Introduction

Fundamentals of Bulk FinFETs

Modeling

Applications

Conclusions

Outline

The scaling of conventional planar MOSFETs has been facingproblems such as subthreshold swing degradation, significantDIBL, fluctuation of device characteristics, and leakage.

To solve the problems, 3-D device structures could be a solutionand have been studied.

FinFETs (built on bulk silicon or SOI wafers) among 3-D devicesare very promising candidate for future nano-scale CMOStechnology and high-density memory application.

For the bulk FinFETs which is going to be applied to massproduction, we discuss about fundamental properties, modeling,and application of the bulk FinFETs.

Introduction2

What’s bulk FinFET?

FinFET

SOI FinFET Bulk FinFET

3-D view ofbulk FinFET

Si Sub

SiO2

G fin

Si Sub

SiO2

G fin

• Low wafer cost• Low defect density• No floating body effect• High heat transfer rate

to substrate• Good process compatibility

S/D

S/D

HFin xj

0

WFin

TFOX

Heat

Korea/USA patent

Bulk FinFETs (Double- or Tri-gate MOSFETs)

ID-VGS Characteristics of 40 nm bulk N FinFET

3

S/D

S/D

HFinxj

0

WFin

TFOX

Heat

Comparison between Our Structure and Intel’s

Our Structure Intel’s StructureConventionalPlanar Structure

4

5

As+, 20 keV 3x1015/cm2, 2 Fin

25 nm

50 nm

40 nm

-0.5 0.0 0.5 1.0 1.510-10

10-9

10-8

10-7 VDS = 0.1 V

Vbs = 0 V Vbs = -1 V Vbs = -2 V

Dra

in C

urre

nt (A

)

Gate Voltage (V)ID-VGS Characteristics of 40 nm bulk N FinFETOxide

Si

CMP andpartial etch-back

Poly-Si

40 nm

Gate Poly-Si Etching

T. Park et al., SNU/KNU, Physica E19, p.6, 2003 T. Park et al., SNU/KNU, Nanomes03 2003

Top Si Width 25 nmBottom Si Width 100 nmSi Fin Height 230 nm

First Bulk FinFET in the World

T. Park et al., SNU/Samsung/KNU, p.135, Symp. on VLSI Tech. 2003

-0 .5 0.0 0.5 1.0 1.5 2.010 -14

10 -13

10 -12

10 -11

10 -10

10 -9

10 -8

10 -7

10 -6

10 -5

C onv. D R AM C ell T r.D IBL = 108 m V/V

Vds = 0.1 V Vds = 0.6 V Vds = 1.1 V Vds = 1.6 V

Dra

in C

urre

nt (

A)

G a te Vo ltage (V )

Vbs = 0 V

FinFETD IBL = 24 m V/V

F in Top W idth = 30 nmFin Bottom W idth = 61 nmFin Height = 99 nmLD R A W N = 120 nm

W = 120 nmL = 120 nm

181 nm

99 nm

61 nm

30 nm

82˚

Si Substrate

SiO2

Poly-Sifin body

SEM cross-section

Gate Electrode

SiO2

SiN

Si Substrate

Fin

SiO2

6

First Bulk FinFET at Industry

7

Introduction

Fundamentals of Bulk FinFETs

Modeling

Applications

Conclusions

Outline

Gate

Oxide

Fin

Gate

Fin

Gate

Fin

(a) (b) (c)

DG Structure TG Structure

90o Corner Half-circle Corner

8

Body Shape of FinFET

10 20 30 40 500.1

0.2

0.3

0.4

0.5

Nb=1x1019 cm-3

Tox=1.5 nm

xj,S/D=66 nmHfin=70 nm

Bulk SOI

Fin Width (nm)

Vth (V

)

Lg=25 nm

0

30

60

90

120

150

180

DIB

L (mV

/0.9V)

10 20 30 40 5070

75

80

85

90

95

100

xj,S/D=66 nmHfin=70 nm

Nb=1x1019 cm-3

Tox=1.5 nm

Lg=25 nmVDS=0.9 V

Sub

thre

shol

d S

win

g (m

V/d

ec)

Fin Width (nm)

Bulk SOIVDS=0.05 V

The bulk FinFETs (solid circles) have nearly the same Vth, DIBL, and SScharacteristics as those of SOI FinFETs (open circles).

Vth & DIBL SS

9

Equivalent FinFET on Bulk and SOI Wafers

Equivalent FinFET on Bulk and SOI Wafers

Tri-gate on bulk-silicon and SOI substrates have similar short channel performance

Source: Intel

Low body doping: xj,SDE > Hfin → DIBL & SS ↓(due to bulk punch-through) Medium body doping: xj,SDE Hfin + 10 nm To prevent bulk punch-through : xj,SDE ≤ Hfin and/or local doping

20 40 60 80 1000

100

200

300

Tox=1.5 nm

m=4.7 eVHfin=70 nm

Nb=1x1016cm-3

Nb=5x1016cm-3

Nb=5x1016cm-3

Nb=1x1017cm-3

SDE Junction Depth (nm)

DIB

L (m

V/V

)

Wfin=20 nmVDS=0.05 V

Lg=50 nm

+local doping(xp=70 nm)

70

80

90

100

110

120

130

SS

(mV

)

S/D S/D

Fin body

Local doping

xpS/D S/D

Fin body

Local doping

xp

Local dopingxp=70 nmNLocal=1x1018 cm-3

11

S/D Junction Depth Design of Bulk FinFET

Heat transfer rate : Bulk » SOI Bulk FinFET has a device temperature less by 130 oC than SOI FinFET at a

fixed VGS of 0.9 V.

-0.2 0.0 0.2 0.4 0.6 0.8 1.0

300

325

350

375

400

425

450

475

130 oC Bulk SOI

VDS=0.9 V

Tox=1.5 nm

Dev

ice

Tem

pera

ture

(K)

Gate Voltage (V)

Lg=30 nm

12

Device Temperature Characteristics

Si Nanoelectronics, 102-103, 2003

-1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50

0.0

0.1

0.2

0.3

0.4

0.5

WFin: 10, 15, 20, 30, 50 nm

WFin

: 10, 15, 20, 30, 50 nm

Body Bias (V)

VT (V

)

70

80

90

100

110

120

Subthreshold S

wing (m

V/dec)

LG=25 nm

No VT increase at a given back bias

S B

G G

Silicon Nanoelectronics workshop, p.102, 2003

Back-bias Effect

Properties of Bulk FinFETs13

Vths of three devices are the same by using gate workfunction engineering. Bulk and SOI FinFETs have an ignorable back bias effect.

-0.4 -0.2 0.0 0.2 0.4 0.60.1

0.2

0.3

0.4

0.5

VDS=0.05 V

@VBS=0 VVth0=0.35 V

Width=200 nmm=4.33 eV

Tox=1.5 nm

Hg=100 nm

Lg=50 nm

Bulk FinFET SOI FinFET Planar MOSFET

V th (V

)

VBS (V)

Nb=2x1018 cm-3

W fin=20 nmm=4.51 eV

14

Back-Bias Effects

80 82 84 86 88 90 9280

90

100

110

120LG =30 nm

HFin=70 nm WFin =20 nm

Angle () (deg)

DIB

L (m

V/V

)

Na=1x1019 cm-3

n+ poly gate

70

80

90

100

110

120

SS (mV)

20 nm

Fin

-0.2 0.0 0.2 0.4 0.6 0.8 1.00.6

0.7

0.8

0.9

1.0

1.1

1.2

VDS=0.9 V

VDS=0.05 V

W Fin=20nmHFin=70nmLG =30nm

90o

83.3o

81.6o

Gate Bias (V)

Nor

mal

ized

Dra

in C

urre

nt

Device Characteristics with Body Angle

Tapered fin widens – degradedSCEs

Closer to 90o of body angle, betterDIBL and drain current

Impact of Fin Profile

Rectangular Fin profile improves SCEs for LG scaling:Lowers SSAT

Lowers DIBL

Symp. on VLSI Tech, Intel, 2006

Gate

Fin

Si Substrate

Gate

Fin

BOX

(a) (b) (c) (d)

Bulk SOI

Gate

Fin

BOX

Gate

Fin

BOX

Process variation

17

Bottom Corner Effect

Invited talk at ECS, ECS Transactions, 19 (4) 101-112 (2009)

Ioff : (a) < (b) < (c) < (d)

-0.2 0.0 0.2 0.4 0.6 0.8 1.010-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Hfin=70 nm

VDS=0.05 V

VDS=0.9 V

n+ poly gate Tox=1.5 nmWfin=20 nm

Lg=100 nm

Bulk FinFET (a) SOI FinFET (b) SOI FinFET (d)

I D (A

)

VGS (V)

Nb=2x1018 cm-3

(a) (b) (c) (d)0.01

0.02

0.03

0.04

0.05

0.06

SOI

Thre

shol

d V

olta

ge (V

)

Bulk

Vth : (a) > (b) > (c) > (d)

ID vs VGS Vth vs Structure

18

Bottom Corner Effect

Wfin ↑ → DIBL ↑ & Vth ↓ Low doped bulk or SOI FinFETs → narrow Wfin for good characteristics

5 10 15 200.30

0.32

0.34

0.36

0.38

0.40

Simulation Model

Fin Width (nm)

V th (V

)

Hfin=70 nmLg=30 nm

Nb=5X1016cm-3

m=4.71 V

0

50

100

150

200

250

300

350

body

Si substrate

WFin

Gate TOX

oxide

Local doping @ xP=80 nm

DIB

L (mV

/V)

Rounded corner

corner effect ↓

Low doped channel

Nb=5x1016 cm-3

Local doping

xp=80 nm

NLocal=3x1018 cm-3

19

Fin Body Width Effect of Bulk FinFET with Low Nb

Planar MOSFET : Delay Time ↑ (due to Vth ↑) with negatively increasing VBS

SOI or Bulk FinFETs : nearly constant Delay Time with VBS → moreeffective devices for the full-down circuits

-0.50 -0.25 0.00 0.25

0.8

1.0

1.2

1.4

1.6 Planar MOSFET Bulk FinFET SOI FinFET

N

orm

aliz

ed D

elay

Tim

e

VBS (V)

Nb=2x1018 cm-3 C=20 fFTox=1.5 nm Lg=50 nm

-0.50 -0.25 0.00 0.25

0.8

1.0

1.2

1.4

1.6

V1

CVb

Vcc

Vin

Full-down delay time vs VBS Inverter circuit

Speed Characteristics

ECS meeting (invited talk), May, 2008

20

(a) Small signal equivalent circuit for RF device modeling.

(b) Comparison of RF parameters extracted from bulk and SOI DG FinFETs.

CgdRg

vgs

GateDrain

Substrate

gmvgsCm dtdVgs

Cgsgmbvbs

gds Csd

vbs

CjdCjs

Rsub

Source

PORT

1

PORT

2Intrinsic Body

CgdRg

vgs

GateDrain

Substrate

gmvgsCm dtdVgsCm dtdVgs

Cgsgmbvbs

gds Csd

vbs

CjdCjs

Rsub

Source

PORT

1

PORT

2Intrinsic Body

177 GHz170 GHzfT

-0.0033 fF-0.0037 fFCsd

-fF0.0151 fFCjs

-Ω8200 ΩRsub

-fF0.014 fFCjd

472 Ω461 ΩRg

0.038 fF0.037 fFCgd

0.073 fF0.0713 fFCdg

0.113 fF0.116 fFCgs

0.414 μS0.427 μSgds

166 μS160 μSgm

0.286 V0.31 VVth

SOI DG FinFET

Bulk DG FinFET

177 GHz170 GHzfT

-0.0033 fF-0.0037 fFCsd

-fF0.0151 fFCjs

-Ω8200 ΩRsub

-fF0.014 fFCjd

472 Ω461 ΩRg

0.038 fF0.037 fFCgd

0.073 fF0.0713 fFCdg

0.113 fF0.116 fFCgs

0.414 μS0.427 μSgds

166 μS160 μSgm

0.286 V0.31 VVth

SOI DG FinFET

Bulk DG FinFET

(a) (b)

21

Speed Characteristics

20 30 40 50 60 700.1

0.2

0.3

0.4

0.5Lg=100 nmTox=1.5 nm

VGS=1.0 V, VDS=1.5 V

Na=3x1018 cm-3

c=1x10-7 cm2

n+ poly gate

Solid : d=100 nmOpen : d=5 nm

Fin Width (nm)

V drop

(V)

2000

2200

2400

2600

2800

3000

3200 Peak E

lectron Temperature (K

)

Effect of S/D Resistance with Fin Body Width

• Wfin ↓ → electron temp. ↓ : Ohmic drop across Rsd (Wfin less than 50 nm)

Rsd=Ras+Rsh+Rc

22

3-D Spacer Formation

Epi grwoth blocked by the Fin spacers

Spacers completely removed allowing for epitaxial raised S/D formation

Source: Intel

23

Industry Leading Performance

NMOS

Integrated CMOS tri-gate with:1.High-k dielectrics & metal gate2.Strain engineering for NMOS & PMOS3.Dual epitaxial raised source/drains

PMOS

Source: Intel

24

25

Introduction

Fundamentals of Bulk FinFETs

Modeling

Applications

Conclusions

Outline

2-D schematic view of symmetricdouble-gate MOSFET.

Gate

Gate

Source

(n+)

Drain (n+)

Fin Body

Lov

Tox

Wfin

L

Lg

VGS

VGS

VDS

Oxide

y

x

0

Bulk FinFET or SOI FinFET (not shown)

Side-channel

S/D

S/D

TFOX

A

A’

Side-channel of bulk or SOI FinFETs :DG structure → key point

26

Schematic View of DG MOSFETs

27

Short-channel effectxm xm

S D

xls xldLc=L-2xm

xrs=xcs xrd=xcd

S

(a) (b)

xcs

xhs

G

G

Tox

Wfin

SiO2

SiO2

b dep hs hdth ,SCE

ox c

qN x x x / 2V

C L

b depth ,SCE FB B

ox

h

c

qN xV V 2 1

CxL

� Charge-sharing lengthhs hd

hx xx

2

: Vth model of the conventional planar MOSFETs

:DG M OSFETsfin0.5W

Vth Modeling of Side-Channel (1)

28

Narrow-width effect

S DG

xhs xhdLg

Hg

Lc

xdf

(a) SiO2 SiO2Fin

Body

xdf

Hg G G

TgateTox Wfin

(b)b dep d f

th ,N W Eox g

qN x xV

C 4 H

gateoxth ,s 2

dep bd

oxf

T8V ln 1x qN

xT

: an effective widthdepleted by gate fringingfield

Vth Modeling of Side-Channel (2)

Vth Modeling of Bulk FinFETs

gMS B

E2e

b dep d fth ,N W E

ox g

qN x xV

C 4 H

gateoxof

ox

T2C ln 1T

gateoxdf th ,woc 2

dep b ox

T8x V ln 1x qN T

b dep dfh

th ,woc FB B wox m g

qN x xxV V 2 1C L 2 x 4 H

b dep hs hd

th ,SCEox m

qN x x xVC 2 L 2 x

Vth equations of bulk FinFETs based on 3-D charge sharing

SCE

NWE

: in NMOSFET with n+ poly gate

The xdf and the Vth,woc are obtained by solving these equations

b dep hth ,SCE FB B

ox m

qN x xV V 2 1C L 2 x

IEEE Trans on Electron Devices, p. 537, 2007

29

0.0 0.2 0.4 0.6 0.8 1.0

0.08

0.12

0.16

0.20

WB=15 nm

L=60 nm

gm,max Method Proposed Model CC Method

L=30 nm

L=190 nm

Vth (V

)

VDS (V)

Tox=1.5 nm

Nb=5x1018 cm-3n+ poly gateVth0

0.0 0.2 0.4 0.6 0.8

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Simulation Proposed Model CC Method

I D (m

A/m

)

VDS (V)

n=200 cm2/V-sec n+ poly gateWB=15 nm

Tox=1.5 nmVGS=0.4 V

L=30 nm

Nb=2x1018 cm-3

VDS,sat=0.426 V

Nb=5x1018 cm-3

VDS,sat=0.271 V

Vth Model Considering Drain Bias

Jpn. Journal of Applied Physics

Verification in Double-Gate MOSFETs

30

10 100 1000-0.25

-0.20

-0.15

-0.10

-0.05

Simulation Model

Vth (V

)

Lg (nm)

xh=20 nm Nb=8x1017 cm-3

n+ poly gateVDS=0.05 V

Wfin=10 nmTox=1.5 nmW=-0.04274 VB=-0.045 V

20 40 60 80 100 120 140 160 180 20050

60

70

80

90

100

ideal subthreshold slop

n+ poly gate

Simulation Model

SS

(mV

/dec

.)Channel Length (nm)

Nb=5x1018 cm-3

Wfin=15 nmVDS=0.05 VTox=1.5 nm

Nb=8x1017 cm-3 , Wfin=10 nm

Vth vs Lg SS vs L

Models show a good agreement with simulation data.

Nb=5x1018 cm-3 , Wfin=15 nm

31

DC Models of Doped DG MOSFETs (2)

0.0 0.2 0.4 0.6 0.8 1.010-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

VGS (V)

I D (A

/m

) Nb=5x1018 cm-3

Wfin=15 nm

Tox=1.5 nmVDS=0.05 V

n=200 cm2/V-secn+ poly gate

0.0

0.2

0.4

0.6

0.8

1.0 Simulation Model

ID (mA/m

)

Vth=0.1297 VL=30 nm

L=190 nmVth=0.1899 V

0.0 0.2 0.4 0.6 0.80

2

4

6

Simulation Model

I D,d

rift (m

A/m

)VDS (V)

Nb=5x1018 cm-3

n+ poly gateWfin=15 nm

VGS=0.4 V

Tox=1.5 nm

n=200 cm2/V-sec

L=30 nm

VDS,sat=0.274 V

VDS,sat=0.679 VVGS=0.8 V

Nb=5x1018 cm-3, Wfin=15 nm, Tox=1.5 nm, μn=200 cm2V-1s-1

ID vs VGS ID vs VDS

Models show a good agreement with simulation data.

32

DC Models of Doped DG MOSFETs (3)

33

oxide

Si substrate

Gate

Body

Wsc

Ws

Wtc

Wtc

channel

Wsc

Ws

Hg

xh

body Wfin

Gate

Tox

r x’dep

Wc

(a) (b) (c)(a) Schematic 3-D view for considering the

corner effect(b) Cross-sectional view of the fin body

with 90 o corner

(c) Cross-sectional view of the fin bodywith half-circle corner

Schematic Views for Considering Top Corner Effect

33

h2 x13 L

,

'0.5 22 1

3c b fin h

FB Box

th c

q N W xVC

VL

Vth,s model for side-channel with a fully depleted fin body

Vth,c model for corner-channel with a fully depleted fin body

: SCE term in the corner region regardless of the corner shape

: Corner Vth model

Corner factor(=0.4): Fitting parameter

Corner-channel

b fin dfhFB B

ox gth ,s

qN 0.5W xxV 2 1C L 4 H

V

SCE & NWE

Side-channel

SCE NWE

bulk FinFET only

34

Vth Model of FinFET with Top Corner (1)

20 30 40 50 60 70 80 90 100-0.2

0.0

0.2

0.4

0.6

0.8

1.0

c=0.4

VDS=0.05 Vn+ poly gate

Nb=5x1018 cm-3 MS=-1.0683 V

Wfin=20 nmHfin=70 nmTox=1.5 nm

Nb=1019 cm-3 MS=-1.0862 V

oxide

Si substrate

body

WFin

Gate TOX

Si substrate

oxide

Simuation Model

Vth (

V)

Gate Length (nm)

5 10 15 20

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7Gate

T ox

body

Si substrate oxide

W fin H g

c=0.4

Nb=5x1018 cm-3 MS=-1.0683 V

Nb=1019 cm-3 MS=-1.0862 V

Lg=100 nm

Simuation Model

Vth (

V)Wfin (nm)

n+ poly gateTox=1.5 nm

VDS=0.05 VHfin=70 nm

Vth vs Lg Vth vs Wfin

Models show a good agreement with simulation data.

Hfin=70 nm, VDS=0.05 nm, Tox=1.5 nm, n+ poly gate

35

Vth Model of FinFET with Top Corner (3)

Vth Modeling of Bulk FinFETs

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0Mod.

c=0.25

Lg=100 nm

m=4.71 V

m=4.17 V

10.60.3Radius Ratio [=r/0.5Wfin]

r

0.5Wfin

Body

Nb=1x1019 cm-3, Hg=70 nm

Nb=5x1018 cm-3, Hg=70 nm

Nb=5x1018 cm-3, Hg=40 nm

Nb=2x1018 cm-3, Hg=70 nm

Vth (V

)

0

VDS=0.05 VWfin=20 nm

Sim.

30 40 50 60 70 80 90 100-0.2

0.0

0.2

0.4

0.6

0.8

1.0

c=0.25

VDS=0.05 Vn+ poly gate

Nb=5x1018 cm-3 MS=-1.0683 V

Wfin=20 nmHg=70 nmTox=1.5 nm

Nb=1019 cm-3 MS=-1.0862 V

oxide

Si substrate

body

WFin

Gate TOX

Si substrate

oxide

Simuation Model

V th (

V)

Gate Length (nm)

Verification of the Model

IEEE Trans on Electron Devices, p. 537, 2007

36

3-D schematic view 2-D schematic view

Bulk FinFET as an example

S/D

S/D

Hg

X jSDE

0

W finTFOX

A

A’

body

Gate

Si substrate

oxide

Top-channel region

Field penetration

region from top-

gate

●

Electricfield

●

The electric field penetration region(hatched triangle) from the top-gate intothe side-channel region.

37

Current Model of FinFET (1)

ID vs VGS

With Vth,s & Vth,c

Before considering field penetration effect

With Vth0,s & Vth0,t

After considering field penetration effect

-0.2 0.0 0.2 0.4 0.6 0.8 1.010-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Hg=70 nmVDS=0.05 VWfin=20 nm

Lg=100 nm

Simulation Side-channel (model) Top-channel (model) Total (model)

I D (A

)

VGS (V)

Nb=5x1018 cm-3

-0.2 0.0 0.2 0.4 0.6 0.8 1.0

0.0

1.0x10-5

2.0x10-5

3.0x10-5

Simulation Side-channel (model) Top-channel (model) Total (model)

I D (A

)

Nb=5x1018 cm-3

Lg=100 nm

Wfin=20 nm

VDS=0.05 VHg=70 nm

10-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

ID (A)

VGS (V)

38

Current Model of FinFET (5): An Example

ID vs VGS

39

Continuous Current Model of DG MOSFET

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

1.0x10-5

2.0x10-5

3.0x10-5

4.0x10-5

5.0x10-5

6.0x10-5

7.0x10-5

8.0x10-5

9.0x10-5

1.0x10-4

0.0 0.2 0.4 0.6 0.8 1.010-14

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Simulation Nb = 2x1018 cm-3

Nb = 1018 cm-3

Nb = 1017 cm-3

Nb = 0 cm-3

Model

I d (A)

Vgs (V)

Vds =1Vtox = 1.5nmtb = 10nmLg = 1mW = 1m

Lines: Model

Symbols: Simulation

g= b

g= midgap when Nb=0No source/drain resistances

Good agreement From intrinsic to ~1017 cm-3:

nearly the same

bsi

bb

tx

qkTtxqNx

2coslncosln2

8)4()(

22

.tan42

oxb

oxsi

ox

oxbbfbgs qt

kTtttqNVV

.22/

0

)(

d

s

bft

kTq

if

gnd eqnd

LWI

40

Introduction

Fundamentals of Bulk FinFETs

Modeling

Applications

Conclusions

Outline

First SRAM Application of Bulk FinFET41

Bulk FinFETControl planar FET Nano width planar FET

Inverter schematic

SNM Comparison

IEDM, p.27, 2003

SEMTopview

IEEE Trans on Electron Devices, p.481, 2006

Si

SiO2

SiN

Gat

e P

oly-

Si

Si F

in

-1.00 -0.75 -0.50 -0.25 0.00 0.2510-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-1

Dra

in C

urre

nt (A

)

Gate Voltage (V)

Triple Gate PMOSFET, Vds = -0.1 V Triple Gate PMOSFET, Vds = -1.1 V Planar PMOSFET, Vds = -0.1 V Planar PMOSFET, Vds = -1.1 V

VBS = 0 V

-2.5 -2.0 -1.5 -1.0 -0.5 0.00.0

-1.0x10-5

-2.0x10-5

-3.0x10-5

-4.0x10-5

-5.0x10-5

-6.0x10-5

-7.0x10-5

Dra

in C

urre

nt (A

)

Drain Voltage (V)

VBS = 0 V

Solid : Triple Gate PMOSFETDashed : Planar PMOSFET

IEEE Electron Device Letters, p. 798, 2004

Bulk pFinFET in a SRAM Cell

SEM View and I-V Curves of pMOSFET

SEM view

ID-VGS curves

ID-VDS curves

42

World 1st Saddle MOSFET for DRAM Cells

Si sub.

S/D

SiO2

Fin body

Gate A`

A

B B`

IEEE Electron Device Letters, p. 690, 2005

A – A`

B – B`

xjS /D

G ate insulato r

Gat

e

S /D

L g

G ate insulato r

G ate

S iO 2

S i sub .

W fin

L o v_ s ide

L ocal d op ing

-0.3 0.0 0.3 0.6 0.9 1.2 1.510-16

10-14

10-12

10-10

10-8

10-6

10-4

Saddle m4.71 V

Recess m4.17 V

VDS = 0.05 V 1.5 V Saddle Recess

Dra

in C

urre

nt (A

)Gate Voltage (V)

Lg=12 nm Wfin=20 nm Tox=3.5 nm Recess depth=50 nm xjS/D,LDD=21 nm

xjS/D,HDD=33 nm

Schematic View and Comparison of I-V Curves

Saddle Recess SS 69.5 132DIBL 21 170

Schematic view

Korea/USA patents

43

Summary

Brief introduction

Fundamentals of Bulk FinFET

- Nearly the same scalability and performance as those of SOI

FinFET, and has several advantages

- Body shape, temperature, back-bias, S/D resistance, and speed

- Design guideline on body doping and width

Model explains very well the behavior of Vth, internal physics, and

I-V of double/tri-gate bulk FinFETs

Bulk FinFETs could be applied to SRAM, low-power logics, and be

modified to DRAM cell

44