Xilinx XAPP852 RLDRAM II Memory Interface for Virtex-5 FPGAs
Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs
description
Transcript of Built-In Self-Test of Global Routing Resources in Virtex-4 FPGAs
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BUILT-IN SELF-TEST OF BUILT-IN SELF-TEST OF GLOBAL ROUTING RESOURCES GLOBAL ROUTING RESOURCES
IN VIRTEX-4 FPGASIN VIRTEX-4 FPGASJia Yao, Bobby Dixon, Charles Stroud and Jia Yao, Bobby Dixon, Charles Stroud and
Victor NelsonVictor NelsonDept. of Electrical & Computer EngineeringDept. of Electrical & Computer Engineering
Auburn UniversityAuburn University
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Outline of PresentationOutline of Presentation
Motivation and backgroundMotivation and background Virtex-4 global routing resourceVirtex-4 global routing resource Routing BIST ImplementationRouting BIST Implementation
for Virtex-4 FPGAsfor Virtex-4 FPGAs Implementation resultsImplementation results Application to Virtex-5Application to Virtex-5 Summary Summary
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Fault Simulation Results
0
10
20
30
40
50
60
70
80
90
100
SingleCounter
Dual Counter Dual Parity Cross-Coupled
Parity
Max LengthCAR
All 150-RuleCAR
Fa
ult
Co
vera
ge
(%
)
w/ ORA w/o ORA
0
10
20
30
40
50
60
70
80
90
100
SingleCounter
Dual Counter Dual Parity Cross-Coupled
Parity
Max LengthCAR
All 150-RuleCAR
Fa
ult
Co
vera
ge
(%
)
Dominant BFs Dominant-AND/OR BFs
8
8
6
18 19
24
Stuck-at FaultStuck-at FaultStuck-at valueStuck-at valueFeedback wires Feedback wires can be considered can be considered under test under test
Bridging FaultBridging FaultBest approachesBest approaches8-bit maximum length 8-bit maximum length
sequence CARsequence CAR cross-coupled paritycross-coupled parity
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Cross-Coupled Parity Approach
F LUT
G LUT
Podd
Cd1
Cd0
F LUT
G LUT
Peven
Cu1
Cu0Slice 0
Slice 2
Slice 1
Slice 3
TPG (Te)count-up
even parity
TPG (To)count-downodd parity
ORA (Oe)even parity
ORA (Oo)odd parity
2
1
1
2
ORAeven parity
ORAodd parity
G LUT
PoddCu1Cu0
Pass/Fail
G LUT
PevenCd1Cd0
Pass/Fail
Test Pattern SequenceCu1Cu0 Po Cd1Cd0 Pe
00 1 11 001 0 10 110 0 01 111 1 00 0
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Virtex-4 Global Routing ResourcesCLB
Switch Box
Slices (LUTs & FFs)
PIPs
Double/Hex lines
N/S/E/W
10 wires
BEG, MID, END
Long Lines
Switch Box
N/S 2 BEG 0-9
N/S 2 MID 0-9
N/S 2 END 0-9
slices
Long lines
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BIST for Double lines (North and South)
Test Pattern SequenceCu1Cu0 Po Cd1Cd0 Pe
00 1 11 001 0 10 110 0 01 111 1 00 0
Pass by 1 CLB into MID
pass by 2 CLBs into END
6 wires under test (2 configs)
12 lines under test in parallel
Alternate TPGs, ORAs position
in adjacent CLBs.
BEG 0-9
MID 0-9
END 0-9
To
Te
Oo
OoOe
Oe
Te
To
Oo
OeOo
Oe
Te
To
Oo
OeOo
Oe
BEG 0-9
MID 0-9
END 0-9
BEG 0-9
MID 0-9
END 0-9
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Loopbacks
SouthEND-to-BEGConnections
LoopbackConnections
At the edges of array via wires in the opposite
direction till the opposite
edge Example:
north double lines loopback at the top edge
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BIST for Double lines (East and West)
Involve Non-CLB Columns
END and BEG terminals in east and west directions
are connected
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Non-CLB Column Double Lines
BIST for Non-CLB Column Double LinesTPGs and ORAs locate in
adjacent CLB columns
Use east/west double
lines to connect adjacent
CLB columns
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BIST For Hex Lines
Hex lines architecture pass by 3 CLBs into MID, by 6 CLBs into END
more limitation of connections from hex lines to LUTs MID and END terminals share the same PIPs
BIST for hex linessimilar to double lines more configurations needed
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Long Lines Architecture
pass by 24 CLBs 5 wire segments
4 wires under testBi-directional two end points: source or input other three stops: input only
Orthogonal direction is tested simultaneously
i
i+1
i+6
i+7
i+12
i+13
i+18
i+19
i+24
i+25
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BIST for Long lines
Oe
Oe
Oe
Oe
Oe
Oe
Oe
Oe
Oe
Oe
Oe
Tcu
Tcu
Tcu
Tcd
Tcd
Tcd
Peven
Cuo
Cu1
Cu2
Peven
CLB i
CLB i+6
CLB i+12
CLB i+18
CLB i+24G LUT
PevenCd0-3
Pass/Fail
F LUT
ORAeven parity
(Oe)
TPG count-upeven parity (Tcu)
TPG count-downeven parity (Tcd)
Cu2 Cu1 Cu0 Peven Cd2 Cd1 Cd0 Peven
0 0 0 0 1 1 1 1
0 0 1 1 1 1 0 0
0 1 0 1 1 0 1 0
0 1 1 0 1 0 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 0 1
1 1 0 0 0 0 1 1
1 1 1 1 0 0 0 0
CLB i+2
CLB i+1
CLB i
CLB i+3
CLB i+4
CLB i+5
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Global Routing BIST Configurations
RoutingResource
DirectionTotal
ConfigsN S E W
CLB double lines 2 2 2 2 8
Non-CLB column double lines 2 2 4
CLB hex lines 4 4 2 2 12
Non-CLB column hex lines 2 2 4
CLB long lines * * 1 1 2
Non-CLB column long lines 1 1 2
Total BIST Configurations 32
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RAM RAM
DSPMIDDLE
Actual Implementation Results
I/O Cell
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Application to Virtex-5Global Routing Resource changed
double lines, pent lines and long lines N/S/E/W BEG, MID, END half as the same, half as “L-shaped” which go in
orthogonal direction as well 3 wires for each pattern in each direction
instead of 10 long lines pass by 18 CLBs, four wires
Our approach is adapted to Virtex-5 test for “L-shaped” double/pent lines
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SummaryCross-coupled Parity is the best choice
better fault coverage
the most practical for actual implementation
best choice for Virtex-5
BIST of Virtex-4 routing resources
Program to generate BIST configurations
automatically
modified for V-5
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