C. Stroud 10/06 BILBO 1

BuiltBuilt--In Logic Block Observer In Logic Block Observer -- OrganizationOrganization

zz ArchitectureArchitecturezz OperationOperationzz Test Session SchedulingTest Session Schedulingzz BIST ControllerBIST Controllerzz Concurrent BILBOConcurrent BILBOzz Benefits & LimitationsBenefits & Limitations

C. Stroud 10/06 BILBO 2

BuiltBuilt--In Logic Block Observer (BILBO)In Logic Block Observer (BILBO)zz by by KoenemannKoenemann & & MuchaMucha, 1979, 1979 1st BIST approach proposed1st BIST approach proposed

zz BIST logic added to all BIST logic added to all FFsFFs plus logic for characteristic polynomialplus logic for characteristic polynomial

zz BILBO control leads B1 & B2 facilitateBILBO control leads B1 & B2 facilitate system mode system mode -- normal operationnormal operation reset mode reset mode -- initializationinitialization LFSR mode LFSR mode -- TPGTPG MISR mode MISR mode ORAORA Scan mode neededScan mode neededBIST results retrievalBIST results retrieval Initialization of Initialization of TPGsTPGs99 to nonto non--0 values0 values

zz TestTest--perper--clock BISTclock BIST Exhaustive testing of combinational logicExhaustive testing of combinational logic

ZiB1B2

Qi-1

D Q

CK Q

Qi

Qi

CombLogicaddedto FF

BILBO FF

BILBO

BILBO

CombLogic

Z

B1B2

Q

C. Stroud 10/06 BILBO 3

BILBO EvolutionBILBO Evolutionzz Original implementationOriginal implementationRequired mode pin B1 Required mode pin B1

to control TPG vs. to control TPG vs. MISR mode during MISR mode during testingtestingForcing logic 0s on Z Forcing logic 0s on Z

inputs causes MISR to inputs causes MISR to function as LSFR for function as LSFR for TPGTPG

Used external FB LFSRUsed external FB LFSRzz Later implementation added Later implementation added

control signal B3control signal B3To control TPG vs. To control TPG vs.

MISR modesMISR modes

C. Stroud 10/06 BILBO 4

BILBO EvolutionBILBO Evolutionzz Modified BILBO was Modified BILBO was

introduced for practical introduced for practical ASIC implementationsASIC implementationsNAND gates used NAND gates used

for CMOS for CMOS friendlyfriendlystandard cellsstandard cellsOnly two control Only two control

signals neededsignals neededMinimizes area Minimizes area

overheadoverheadMost frequently used Most frequently used

BILBO approachBILBO approach

C. Stroud 10/06 BILBO 5

BILBO OperationBILBO Operationzz At least 2 test sessions requiredAt least 2 test sessions required Test session 1:Test session 1: CktsCkts A & C are CUTsA & C are CUTs BILBO 1 = MISRBILBO 1 = MISR BILBO 2 = LFSRBILBO 2 = LFSR

Test session 2:Test session 2: CktCkt B is CUTB is CUT BILBO 1 = LFSRBILBO 1 = LFSR BILBO 2 = MISRBILBO 2 = MISR

zz Need scan mode toNeed scan mode toRetrieve BIST results from Retrieve BIST results from MISRsMISRsInitialize Initialize LFSRsLFSRs to nonto non--0 values0 values

zz Works well for pipelined architecturesWorks well for pipelined architectureszz Otherwise, problems with feedbackOtherwise, problems with feedbackRequires test session schedulingRequires test session scheduling

CUT A

CUT B

CUT C

LFSR

MISR

BILBO 1

BILBO 2

TestSession

1

MISR

LFSR

TestSession

2

LFSR

MISR

Scan In

Scan Out

C. Stroud 10/06 BILBO 6

Test Session SchedulingTest Session Schedulingzz Practical application Practical application

of BILBO typically of BILBO typically requires scheduling requires scheduling of multiple test of multiple test sessions based on sessions based on interconnection of interconnection of registers and registers and combinational logiccombinational logic

C. Stroud 10/06 BILBO 7

Register SelfRegister Self--AdjacencyAdjacencyzz Common in Common in FSMsFSMsNext state is function of current stateNext state is function of current state

zz BILBO must simultaneously function as TPG and ORABILBO must simultaneously function as TPG and ORASignatures act as test vectorsSignatures act as test vectorsLoose pseudoLoose pseudo--exhaustive nature of test vectorsexhaustive nature of test vectors

zz One solution One solution the Concurrent BILBO (CBILBO)the Concurrent BILBO (CBILBO)Doubles #Doubles #FFsFFs to create independent TPG and ORAto create independent TPG and ORA

Register R1

Register R2

CombinationalLogic

system operation

R1=TPG(LFSR)

R2=ORA(MISR)

CombinationalLogic

BILBO operation CBILBO operation

R1=TPG(LFSR)

R2=ORA

CombinationalLogic

R2=TPG

C. Stroud 10/06 BILBO 8

Concurrent BILBOConcurrent BILBOzz Adds additional register to allow TPG and MISR to operate Adds additional register to allow TPG and MISR to operate

independently in cases of register selfindependently in cases of register self--adjacencyadjacency

C. Stroud 10/06 BILBO 9

BILBO SummaryBILBO Summaryzz Not practical but historically significant since it got BIST staNot practical but historically significant since it got BIST startedrted Led to pseudoLed to pseudo--exhaustiveexhaustive selfself--test (PEST)test (PEST) Led to Circular BISTLed to Circular BIST

C. Stroud 10/06 BILBO 10

BILBO SummaryBILBO SummaryAdvantagesAdvantageszz TestTest--perper--clock clock archtecturearchtecturezz PseudoPseudo--exhaustive testingexhaustive testingNo need for fault simulationNo need for fault simulation

zz Works well for pipelined applicationsWorks well for pipelined applications

DisadvantagesDisadvantageszz Difficult to implement in practical applicationsDifficult to implement in practical applicationsMultiple test sessions requireMultiple test sessions requireTest session scheduling can be difficultTest session scheduling can be difficult

Requires multiple primitive polynomials of varying degreesRequires multiple primitive polynomials of varying degreesRegister selfRegister self--adjacency difficult to overcomeadjacency difficult to overcome

zz Higher area overhead than other BIST approachesHigher area overhead than other BIST approachesMore than two gate delays in every critical pathMore than two gate delays in every critical path