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Building Compilers for Reconfigurable Switches

Lavanya Jose, Lisa Yan,Nick McKeown, and George Varghese

Research funded by AT&T, Intel, Open Networking Research Center.

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In the next 20 minutes

• Fixed-function switch chips will be replaced by reconfigurable switch chips

• We will program them using languages like P4• We need a compiler to compile P4 programs

to reconfigurable switch chips.

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Fixed-Function Switch Chips

QueuesL2

StageIPv4StagePa

rser IPv6

StageACL Stage

L3L2

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Control Flow Graph

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StageACL StageL2

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Switch Pipeline

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Fixed-Function Switch Chips Are Limited

1. Can’t add new forwarding functionality2. Can’t add new monitoring functionality

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Fixed-Function Switch Chips

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MyEncap

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MyEncap

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Fixed-Function Switch Chips Are Limited

1. Can’t add new forwarding functionality2. Can’t add new monitoring functionality3. Can’t move resources between functions

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Control Flow Graph

Switch Pipeline

Reconfigurable Switch Chips

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Mapping Control Flow to Reconfigurable Chip.

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Control Flow Graph

Switch Pipeline

Reconfigurable Switch Chips

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MatchMemory

ActionALU

Protocol Independent Switch

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Match + Action Processor: pipelined and in-parallel

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Reconfigurability: the norm in 5 years

• Reconfigurability adds mostly to logic.• Logic is getting relatively smaller.• The cost of reconfigurability is going down.• Fixed switch chip area today:– I/O (40%), Memory (40%), – Wires, Logic

Switch I/O (30%)

Memory (30%)

Wires (20%)

Logic (20%)

Switch I/O

Memory

Wires Logic

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Fixed Function Broadcom Tomahawk: 3.2 TbpsReconfigurable Cavium Xpliant: 3.2 Tbps

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Reconfigurable chips are inevitable.

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Configuring Switch ChipsP4 code

Compiler

Compiler Target

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P4 (http://p4.org/)

parser parse_ethernet { extract(ethernet);select(latest.etherType) { 0x800 : parse_ipv4; 0x86DD : parse_ipv6; }}

table ipv4_lpm { reads { ipv4.dstAddr : lpm; } actions { set_next_hop; drop; }}

control ingress { apply(l2_table); if (valid(ipv4)) { apply(ipv4_table); } if (valid(ipv6)) { apply(ipv6_table); } apply (acl);}

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(ANCS’13)Parser

Match ActionTables

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What does reconfigurability buy us?

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• Use resources efficiently– Multiple tables per stage– Big table in multiple stages

• Use fewer stagesL2

IPv4

IPv6ACL

Benefits of Reconfigurability

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Naïve Mapping: Control Flow GraphPa

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Control Flow Graph

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Table Dependency Graph (TDG)

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Switch Pipeline

Efficient Mapping: TDG

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Resource constraints

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Header widths

Action ALU inputMemory Type

Table parallelism

More resource constraints

Action Memory

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Map match action tables in a TDG to a switch pipeline while

respecting dependency and resource constraints.

The Compiler Problem

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Step 1: P4 Program

Step 2: Control Flow Graph

L2v4

v6ACL

Step 3: Table Dependency Graph

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v6ACL

Step 4: Table Configuration

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Is that it?

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Two Switches We Studied1 2 3 4 32…

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3 5

2

RMT32 Stages

(SIGCOMM 2013)

FlexPipe5 Stages

(Intel FM6000)

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Additional switch features

L2

v4

v6

ACL

L2

L2

v4

v6

Table shaping in RMT Table sharing in FlexPipe

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Map match action tables in a TDG to a switch pipeline while

respecting dependency and resource constraints.

The Compiler Problem

Table shaping Table sharing

Header widths Action ALU input

Memory Type

Table parallelismAction Memory

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First approach: Greedy

• Prioritize one constraint• Sort tables• Map tables one at a time

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3 Sort by # dependencies

First approach: Greedy

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• Prioritize one constraint• Sort tables• Map tables one at a time

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Too many constraints for Greedy

• Any greedy must sort tables based on a metric that is a fixed function of constraints.

• As the number of constraints gets larger, it’s harder for a fixed function to represent the interplay between all constraints.

• Can we do better than greedy?

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Second approach:Integer Linear Programming (ILP)

Find an optimal mapping.

Pros:• Takes in all constraints• Different objectives• Solvers exist (CPLEX)

Cons:• Blackbox solver• Encoding is an art • Slow

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ILP Setup

min # stagessubject to:

≥

≤

dependency constraints

table sizes assigned

memoriesassigned

table sizes specified

memories inphysical stage

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Experiment Setup

• 4 datacenter use cases from Intel, Barefoot

• Differ in tables, table sizes, and dependencies

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Example Use Case

A Typical TDG

IPv6-Mcast

EG-ACL1

EG-Phy-Meta

IG-Agg-Intf

IG-Dmac

IPv4-Mcast

IPv4-Nexthop

IPv6-Nexthop

IG-Props

IG-Router-Mac

Ipv4-Ecmp

IG-Smac

Ipv4-Ucast-LPM

Ipv4-Ucast-Host

Ipv6-Ucast-Host

Ipv6-Ucast-LPM

Ipv6-Ecmp

IG_ACL2

IG_Bcast_Storm

Ipv4_Urpf

Ipv6_Urpf

IG_ACL1

EG_Props

IG_Phy_Meta

Configuration for RMT

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Metrics: Greedy vs ILP

1. Ability to fit program in chip

2. Optimality

3. Runtime

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Setup: Greedy vs ILP

1. Ability to fit: FlexPipe– Variants of use cases in 5-stage pipeline.

2. Optimality: RMT– Minimum stage, pipeline latency, power

3. Runtime: both switches

Results: Greedy vs ILP

1. Can Greedy fit my program? – Yes, if resources aplenty (RMT, 32 stages)– No, if resources constrained (FlexPipe, 5 stages),

Can’t fit 25% of programs .

2. How close to optimal is Greedy? – 30% more time for packet to get through RMT pipeline.

3. Hmm.. looks like I need ILP. How slow is it? – 100x slower than Greedy – Reasonable if programs don’t change often.

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If we have time,we should run ILP.

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Use ILP to suggest best Greedy for program type.

Critical constraints• Dependency critical: 16 13 stages• Additional resource constraints less importantCritical resources• TCAM memories critical: 16 14 stages– Results for one of our datacenter L2/L3 use cases

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Conclusion• Challenge: Parallelism and constraints in

reconfigurable chips makes compiling difficult.• TDG: highlights parallelism in program.• ILP: better if enough time, fitting is critical, or

objectives are complicated. • Best Greedy: ILP can choose via notion of critical

constraints and critical resources.

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Thank you!

Research funded by AT&T, Intel, Open Networking Research Center.

ILP Run time

• Number of constraints? Not obvious. E.g., RMT– Min. stage: few secs.– Min. power: few secs.– Min. pipeline latency 10x slower

• Number of variables? How fine-grained is the resource assignment? E.g., FlexPipe– One match entry at a time: many days..– 100-500 match entries at a time: < 1 hr