A Micro-Power EEG Acquisition SoC With

Integrated Feature Extraction Processor for a Chronic

Seizure Detection System

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010

The paper presents a low-power SoC that performs EEG acquisition and feature extraction required

for continuous detection of seizure onset in epilepsy patients. The SoC corresponds to one EEG

channel, and, depending on the patient, up to 18 channels may be worn to detect seizures as part of

a chronic treatment system. The SoC integrates an instrumentation amplifier, ADC, and digital

processor that streams features vectors to a central device where seizure detection is performed via

a machine-learning classifier. The instrumentation- amplifier uses chopper-stabilization in a topology

that achieves high input-impedance and rejects large electrode-offsets while operating at 1 V; the

ADC employs power-gating for low energy-per conversion while using static-biasing for comparator

precision; the EEG feature extraction processor employs low-power hardware whose parameters are

determined through validation via patient data. The integration of sensing and local processing

lowers system power by 14x by reducing the rate of wireless EEG data transmission. Feature vectors

are derived at a rate of 0.5 Hz, and the complete one-channel SoC operates from a 1 V supply,

consuming 9 J per feature vector.

Epilepsy and seizure detection

Figure below shows an 18-channel EEG showing onset of patient seizure ; electrical onset occurs 7.5

sec before the clinical onset, which is characterised by muscle reflexes causing the large excursion

artifacts.

Taking the recording in Fig. above as an example, approximately 7.5 sec before the start of clinical

symptoms, a subtle but characteristic change in the EEG can be observed. If this electrical onset can

be detected, an advanced signal can be generated to indicate an eminent seizure

Seizure Detection Algorithm The figure below illustrates the detection algorithm. First, the EEG channels are processed to extract

specific bio-markers that are relevant for seizure detection. Clinical studies have determined that

seizure onset information is contained in the spectral energy distribution of the patient’s EEG [9].

Accordingly, in this SoC the spectral energy of each channel is extracted to seven frequency bins over

a two second window in order to form a feature vector. Up to 18 channels may be used, resulting in

a complete feature vector of up to 126 dimensions. In order to distinguish between seizure and non-

seizure EEG, machine learning is introduced through the use of a support vector machine (SVM)

classifier. The classifier must first be trained by providing it feature vectors that are labelled as

corresponding to seizure or non-seizure.

SOC TEST RESULTS The EEG acquisition and seizure detection SoC is implemented in a 0.18 m CMOS process with five-

metal–two-poly (5M2P) layers. The choice of technology among the options available was driven

primarily by the need for low leakage and the need for poly–poly capacitors, which are required by

the ADC and I-amp. A die photograph of the prototype IC is shown below. The entire device operates

from a single 1 V supply. The Instrumentation-amp has an effective area of approximately 0.30 mm .

The power consumption of the Chopper Stabilized-LNA, which is the most critical stage is, 3.5 W. Its

CMRR is 60 dB, and its integrated noise over a 100 Hz bandwidth is 1.3 V.

CONCLUSION The paper discusses the rationale, design, and results for a SoC performing continuous EEG

acquisition and feature extraction which is required for a chronic seizure detection system for

epilepsy patients. An important focus of this work is processing of the raw bio-potentials to extract

physiologically important information and represent this as a concise feature vector. Patient

idiosyncrasies and the presence of numerous complex background processes motivates the need to

apply machine learning on the feature vectors on a patient-by-patient basis in order to achieve high

sensitivity, specificity, and latency of the detection. The need to process a large amount of highly

distributed data in order to extract specific subtle variances applies generally in brain monitoring

applications. Since processing and communication of the entire data through the system imposes

excessive power cost, ultra-low-power local processing is critical to make the overall system viable.

Finally, the instrumentation needs for low-power EEG acquisition strongly affect the total power. As

a result, it is important to use targeted analog processing where possible to avoid the limitations

imposed by electrode, environment, and physiological disturbances. The presented SoC performs

EEG acquisition, digitization, and feature vector extraction. Each SoC corresponds to one electrode

channel, and up to 18 channels may be required depending on the patient. Each SoC operates from a

1 V supply and consumes 9 J to derive a feature vector. Feature vectors are derived at a rate of 0.5

Hz.

A Batteryless 19uW MICS/ISM-Band Energy

Harvesting Body Sensor Node SoC for ExG

Applications

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 1, JANUARY 2013

This paper presents an ultra-low power battery-less energy harvesting body sensor node (BSN) SoC

fabricated in a commercial 130 nm CMOS technology capable of acquiring, processing, and

transmitting electrocardiogram (ECG), electromyogram (EMG), and electroencephalogram (EEG)

data. This SoC utilizes recent advances in energy harvesting, dynamic power management, low

voltage boost circuits, bio-signal front-ends, subthreshold processing, and RF transmitter circuit

topologies. The SoC is designed so the integration and interaction of circuit blocks accomplish an

integrated, flexible, and reconfigurable wireless BSN SoC capable of autonomous power

management and operation from harvested power, thus prolonging the node lifetime indefinitely.

The chip performs ECG heart rate extraction and atrial fibrillation detection while only consuming

19uW, running solely on harvested energy. This chip is the first wireless BSN powered solely from a

thermoelectric harvester and/or RF power and has lower power, lower minimum supply voltage (30

mV), and more complete system integration than previously reported wireless BSN SoCs.

SYSTEM OVERVIEW

A wireless BSN chip powered by energy harvested from human body heat using a thermoelectric

generator (TEG) is proposed. This, in conjunction with ULP circuits, intelligent duty cycling of power-

hungry blocks (e.g. the transmitter), and a programmable power management system allows for

indefinite operation of the chip. To demonstrate, we present a chip targeting ExG applications. To

achieve flexible data acquisition and processing while operating the node solely from harvested

energy, we propose a system architecture, illustrated in Fig below, which comprises four

subsystems. First, the energy harvesting/supply regulation section boosts a harvested supply input

as low as 30 mV up to a regulated 1.35 V using an off chip storage capacitor. It provides five

regulated voltage supplies to the rest of the chip, and generates a bandgap reference. Second, the

four-channel AFE subsystem provides bio-signal acquisition with programmable gain and sampling

rate, amplifying bio-signals as low as a few uV’s while consuming <4uW/channel . A variable gain

amplifier (VGA) maximizes the signal at the input to an 8-bit successive-approximation (SAR) analog

to digital converter (ADC), reducing the ADC resolution requirement. Third, the acquired data is sent

to a subthreshold digital processing subsystem that also performs mode control and power

management (including power/clock-gating of blocks and dynamic voltage scaling (DVS)) based on

the available energy on the storage capacitor. The digital section includes a custom digital power

management (DPM) processor, general purpose microprocessor (MCU), programmable FIR, 1.5 kB

instruction SRAM/ROM, 4 kB data memory FIFO, and dedicated accelerators for ECG heart rate (R-R)

extraction, atrial fibrillation (AFib) detection, and EEG band energy calculation. The DPM is

responsible for power management, node control, data flow management, and overseeing all

processing on-node. Finally, a sub-mW 400/433MHz MICS/ISM band frequency-multiplying

transmitter (TX) performs BFSK transmission up to 200 kbps. The TX has low instantaneous power

consumption to avoid the need of large filtering capacitors on the supplies and is intelligently duty-

cycled to achieve low average power consumption.

Table below shows a performance comparison table with recent BSN SoCs. This work is the first

wireless bio-signal processing chip enabling battery-free operation. The chip can be powered from

an input as small as 30 mV, enabling thermal energy harvesting. For on-chip power management we

augment power and clock-gating by using the DPM, a custom chip controller, to intelligently handle

energy consumption based on the available energy. The closed-loop power management ‘stoplight’

scheme enables potentially indefinite operation while the node is worn. Our 5.5 kB of on-chip

memory remains operational down to a subthreshold voltage of 0.3 V and is compatible with the

flexible subthreshold datapath. In the heart-rate extraction mode where the transmitter is duty-

cycled, the entire chip, including regulation, only consumes 19 W. To the best of the authors’

knowledge, this system has lower power, lower minimum input supply voltage, and more complete

system integration than other reported wireless BSN SoCs to date. The figure below shows the

current breakdown for a heart rate extraction algorithm run on the SoC.

A Wireless Biomedical Signal Interface

System-on-Chip for Body Sensor Networks

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 2, APRIL 2010

In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that

has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-

property blocks include low-power analog sensor interface for temperature and pH, a data

multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data

encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip

components. The chip has been fully evaluated and tested by connection to external sensors, and it

satisfied typical system requirements.