Body Nets Presentation
-
Upload
saeidhossini -
Category
Documents
-
view
219 -
download
0
Transcript of Body Nets Presentation
-
7/27/2019 Body Nets Presentation
1/20
-
7/27/2019 Body Nets Presentation
2/20
Body Area Networks (BAN)
A network of low capability sensors (physiological, environmental
and activity monitoring)
Sensors communicate with each other through wireless media
Base Station is a gateway for the sensors to the internet
SpO2
EKG
EEG
BP
Base
Station
Motion
Sensor
Base Station
Sensors
Environmental sensors
Physiological sensors
Activity sensors
-
7/27/2019 Body Nets Presentation
3/20
-
7/27/2019 Body Nets Presentation
4/20
Cyber-Physical Security
Interaction through
sensing
Feedback
Use this toprovide
security
Signal
Processing
Cryptographic
primitives
Cyber-Physical
Security
Low
CapabilityThe term Cyber-physicalimplies interaction of computing
world with the physical environment
-
7/27/2019 Body Nets Presentation
5/20
Related Work
The idea of using signals from environment to provide security was first
proposed in [1] and [2]
[3] proposed an algorithm to generate security keys from localized
measurements of Inter Pulse Interval signals.
In our previous work [4] we proposed a secure key agreement protocol PKA
(Physiological value based Key Agreement)
1. S. Cherukuri, K. Venkatasubramanian, and S. K. S. Gupta. BioSec: A Biometric Based Approach for Securing Communication inWireless Networks of Biosensors Implanted in the Human Body. pages 432439, Oct 2003. In Proc. of Wireless Security & Privacy
Workshop 2003.
2. K. Venkatasubramanian and S. K. S. Gupta. Security for Pervasive Health Monitoring Sensor Applications. pages 197202, Dec 2006.
In Proc. of the 4th Intl. Conf. on Intelligent Sensing & Information Processing.
3. C. C. Y. Poon, Y.-T. Zhang, and S.-D. Bao. A Novel Biometrics Method To Secure Wireless Body Area Sensor Networks for
Telemedicine And M-Health. IEEE Communications Magazine, 44(4):7381, 2006.
4. K. K. Venkatasubramanian, A. Banerjee, and S. K. S. Gupta. Plethysmogram-based secure inter-sensor communication in body area
networks. Military Communications Conference, 2008. MILCOM 2008. IEEE, pages 1-7, Nov. 2008.
-
7/27/2019 Body Nets Presentation
6/20
Contributions
Study the feasibility of implementation of CPS in BAN Implement PKA CPS in FPGA
Implementation challenges of CPS in the resource
constrained environment of a BAN
Approach PKA overview
Design Goals for implementation Implementation details
Trade-offs in design goals
-
7/27/2019 Body Nets Presentation
7/20
PKA
Index
PeakValues
PV
FFT
Values
PeakValues Index
PV
FFT
Values
SENSOR 1 SENSOR 2
TimeTime
FFT FFT
Peak Detection
Index
Peak Detection
Index
Quantize Quantize
Polynomial Generation
and evaluation
Fs = [fs1 fs2 .. fsn]
Fr = [fr1 fr2 .. frn]
fs1
p(fs1)
fsn
p(fsn)
p(fs2)
fs2cfi,di
Adding Chaff
Transmit Vault R
Receive Vault
p(x)
Lagrangian
Interpolation
Transmit
Acknowledgement
Receive
Acknowledgement
Sensing Sensing
Extensive experiments with Plethysmogram data
Data obtained from 10 volunteers Data collected using Smith Medical pulse oximeter
boards
Processing done in MATLAB environment
-
7/27/2019 Body Nets Presentation
8/20
Design Goals
Accuracy: Signal Processing require complex computation
Resource poor sensors in BAN force a lot of approximations
Approximations should not lead to loss of security
Minimum Resource Usage: Resource limited BAN
Successful operation of a CPS would require resource utilization within
limits
Latency: Applications are often time critical
CPS may not provide high overheads
-
7/27/2019 Body Nets Presentation
9/20
Implementation Details
FFT PeakDetection
Quantization
Polynomial
Evaluation
Chaff
Point
Mixing
FFTPeak
DetectionQuantization
Lagrangian
InterpolatorVault
Vault
Sender
Receiver
Challenges
Floating Point representation
FFT implementation
Peak Detection
Polynomial Convolution
-
7/27/2019 Body Nets Presentation
10/20
-
7/27/2019 Body Nets Presentation
11/20
FFT Computation
-
7/27/2019 Body Nets Presentation
12/20
32 bit
Comparator
RegA
RegB
Coeff1Coeff2Coeff3
Clock
A>B
RegB
RegA
32 bit
Subtractor
32 bit
ComparatorB-A
Threshold
32 bit
Positive
EdgeTriggered
Shift
Register
Bank
On block indicates clock inputOn block indicates reset that
resets on 0
Slope
Detector
Threshold
Detector
12
Peak Detection
Anywhere else indicates a
connection
Indicates 32 bit word
-
7/27/2019 Body Nets Presentation
13/20
Compute
LevelsRegA
Levels RegAL1
L2
Ln
RegALm
L1
L2
Quantization
Random
Number
Generator
Chaff
Points
Features,
Projections
Mix
VaultChaff Point
Generation
& Mixing
RegA
Calculate
xnMultiplier
Coefficient
Adder
Projections
PolynomialEvaluation
Feature Generation & VaultManagement
-
7/27/2019 Body Nets Presentation
14/20
Lagrangian Interpolation
0
32 bit
Multipl
ier
32 bitAdder
32 bit
Multipl
ier
32 bitAdder
32 bit
Multipl
ier
32 bitAdder
32 bit
Multipl
ier
32 bitAdder
32 bit
Multipl
ier
32 bitAdder
32 bit
Multipl
ier
32 bitAdder
32 bit
Multipl
ier
32 bitAdder
0 0
p zerosp+1 coefficients of
polynomial A
p+1 coefficients of
polynomial B
p zeros
Clock
2p+1 coefficients of resultant polynomial C =
convolution(A,B)
BankA
BankB
0 0
0p
C1
p
C 0
C
pD
1pD
0D
BankC
-
7/27/2019 Body Nets Presentation
15/20
Compliance with design goals Accuracy:
FFT computation percentage difference = 0.94 %
Peak detection had inaccuracies but it did not harm
the operation of the protocol
Parameters Matlab VHDL
Average number of peaks 30 26.5
Number of common peaks for sensornodes in the same BAN
12 10
Number of common peaks for sensorsnodes in different BAN
2 1.7
0 20 40 60 80 100 120 140 1600
2
4
6
8
10
12
14
Peak Index
PeakValues
VHDL features compared with Matlab features
MATLABVHDL
0 20 40 60 80 100 120 140 1600
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
FFT coefficient Index
FFT
co
efficientvalues
Plot of the FFT coefficients calculated by VHDL and by Matlab
VHDLMATLAB
-
7/27/2019 Body Nets Presentation
16/20
Compliance with design goals
Module ClockCycles
MemoryFootprint(KB)
Transmitter 6433.15 47.35
Receiver 11779.80 45.3
Latency:
The total time taken for the execution of PKA at the sender side is 32.2 msec andthat on the receiver side is 59 msec after the measurement phase of the
physiological signal (assuming 20 MHz clock).
Minimal Resource Usage:
Memory footprintof a VHDL
implementation as the number of bits
that are being used by all the variables
that are declared in the implementation.
Available memory footprint = 28 MB
(XC18V02) Spartan 2 family
-
7/27/2019 Body Nets Presentation
17/20
Trade Offs
Accuracy vs. Minimal Resource Usage IEEE 754 floating point unit not implemented
Limiting resource utilizations causes reduction in accuracy
We could set any polynomial order in Matlab benchmark however in the FPGA implementation there are
restrictions.
Security complexity trade-off.
Latency vs. Minimal Resource Usage
Parallelized FFT implementation not considered
Single butterfly structure used for FFT operation
Latency increased (NlogN clock cycles required)
Trade Offs
-
7/27/2019 Body Nets Presentation
18/20
Conclusions
We showed the feasibility of implementation of CPS inBAN
Propose generic design goals
We bring out the implementation challenges of CPS in a
BAN
Discuss trade-offs between the design goals
Implement PKA in motes
-
7/27/2019 Body Nets Presentation
19/20
Thank Youhttp://impact.asu.edu
http://impact.asu.edu/http://impact.asu.edu/ -
7/27/2019 Body Nets Presentation
20/20
20
Software Implementation
Inherent similarity in capabilities
No support for floating point operations
No support for Signal processing applications
Advantages
Only algorithmic specification of components suffice
Has 32 bit fixed point ALU (gate level specification of components not required)
Disadvantages
Severely depleted of resources implementation Low RAM (10 KB) efficient storage of chaff points necessary
Low clock speed (8 MHz)Design decisions taken for VHDL are also applicable here.