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Transcript of [email protected] ENGR-43_Lec-12a_FETs-1.pptx 1 Bruce Mayer, PE Engineering-43: Engineering...
![Page 1: BMayer@ChabotCollege.edu ENGR-43_Lec-12a_FETs-1.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical.](https://reader036.fdocuments.us/reader036/viewer/2022062620/5519bad055034667578b4972/html5/thumbnails/1.jpg)
[email protected] • ENGR-43_Lec-12a_FETs-1.pptx1
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Bruce Mayer, PERegistered Electrical & Mechanical Engineer
Engineering 43
FETs-1(Field Effect Transistors)
![Page 2: BMayer@ChabotCollege.edu ENGR-43_Lec-12a_FETs-1.pptx 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical.](https://reader036.fdocuments.us/reader036/viewer/2022062620/5519bad055034667578b4972/html5/thumbnails/2.jpg)
[email protected] • ENGR-43_Lec-12a_FETs-1.pptx2
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Learning Goals
Understand the Basic Physics of MOSFET Operation
Describe the Regions of Operation for a MOSFET Device
Use the Graphical LOAD-LINE method to analyze the operation of basic MOSFET Amplifiers
Determine the LARGE-SIGNAL Bias-Point (Q-Point) for MOSFET circuits
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx3
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Learning Goals
Use SMALL-SIGNAL models to analyze various FET Amplifiers
Calculate Performance Metrics for various FET Amplifiers
Apply FETs to the Design and Construction of CMOS Logic Gates
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx4
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Transistor What is it?
Transistor is a contraction for “Transfer Resistor”
These devices have THREE connections:• Input• Output• Control
The transistor’s Fluidic-Analog is a Metering (Needle) Valve (a Faucet)
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx5
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
The concept of voltage-controlled resistance
An independent Voltage Applied to the Control connection (the “Gate) regulates the flowof Current Thru the device
Gate
Drain (or Source)
Source (or Drain)
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx6
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Flavors of FETS
Junction Field Effect Transistor → JFET • A Normally ON
transistor
Reverse Biasing two PN Junctions will “Pinch Off” a Conducting Channel
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx7
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Flavors of FETS
Depletion ModeMOSFET • Another Normally
ON transistor
Applying a Gate Voltage Drives Carriers OUT of the conducting Channel to turn off the transistor• No direct Gate↔Channel Connection
– An Isulated Gate Field Effect Transistor (IGFET)
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx8
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Flavors of FETS
Enhancement Mode MOSFET • Normally OFF
transistor• Another IGFET
Applying a Gate Voltage Attracts & Creates carriers to FORM a conducting Channel to turn ON the transistor
These Make Great Switches
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx9
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MOSFET What does that mean?
M → Metal O → Oxide S → Silicon F → Field E → Effect T → Transistor
• Short for “Transfer Resistor”
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx10
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Enhancement Mode - IGFET Insulated Gate
Field Effect Transistors are Normally-Off devices
Applying a Positive Voltage to the Gate will attract e− to the Channel• This will eventually
“invert” a thin region below the gate to N-type, creating a conducting channel between S & D
IGFETs are Great Switches• Used in almost all
digital IC’s
Back-to-Back PN Jcns Between “source” & “drain”
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx11
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MOSFET Nomenclature & Dims
We will consider only Enhancement FETs
n+ ≡ Heavily Doped n-Type
An n-Channel (nFET) enhancement mode FET
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx12
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MOSFET: Current & Speed
In General the performance of an Enhancement Mode MOSFET• Current Carrying
Capacity Increases with Increasing Width, W• On/Off Switching Speed Increases with
Decreasing Gate Length, L– As of 2011 the minimum (best) value
for L was about 22 nm
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx13
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MOSFET On/Off Operation
Source Drain
SiO2 Insulator (Glass)
Gate
holes
electrons
5 volts
electrons to be transmitted
Step 1: Apply Gate Voltage
Step 2: Excess electrons surface in channel, holes are repelled.
Step 3: Channel becomes saturated with electrons.
Electrons in source are able to flow across channel to Drain.
P
N N
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx14
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
nMOSFET Circuit Symbol n-Channel MOSFET
• electrons move from Source→Drain to produce the Drain Current
PN Junction forms between Substrate and Channel when FET is “ON”
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx15
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MOSFET Operation: CutOff As seen in previous
diagrams, unpowered MOSFETS have two OPOSING PN junctions• Channel→Source• Channel→Drain
With NO Potential applied to the gate No current can flow
From the Previous slide the Minimum Gate Voltage required for current-flow is called the “Threshold” Voltage, Vto or Vth
A MOSFET with VGS < Vth is “CutOff”• i.e.; The MOSFET is
Off, and the Drain Current, iD = 0
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx16
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MOSFET Circuit in CutOff The Diagram at
Right shows an nMOSFET in CutOff
For vGS<Vto the PN Jcn between the Drain & Body is Reversed Biased by vDS and NO Current flows• Vto is typically 0.5-5
Volts
Mathematically this is simple; in CutOff, the Drain Current
toGSD Vvi for0
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx17
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Power MOSFET Data Sheet
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx18
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
CutOff Summarized
VGS < Vto → No Drain Current Flows
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx19
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MOSFET IN Triode (Ohmic) Region
In this case the nMOSFET Voltage conditions:
Electrons are ATTRACTED to the Positive-Gate and a thin Conducting Channel Forms
In this Region the Drain Current depends on BOTH vDS and vGS • Fluid Analogy → needle valve
toGStoGSDS VvVvv and
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx20
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
nMOSFET in Triode Operation
When vGS > Vto a conducting channel forms below the gate
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx21
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Triode Operation
When vGS > Vto a conducting channel forms below the gate.• That is the “type” of the silicon is
INVERTED from p-Type to n-Type– Thus this conducting Channel is often called an
“Inversion Layer”
The greater vGS The more the conducting the channel becomes
The Channel resistance is a fcn of vGS
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx22
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Triode Operation In the Triode
Region, iD increases for• Increasing vGS
• Increasing vDS
Thus current thru the device depends on the voltage at ALL three connections as long as vDS < (vGS − Vto)
• The Three-Connection dependency is why this region is called TRIODE
toGStoGSDS VvVvv and
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx23
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Triode Operation In Triode Operation,
the iD curve is a concave-down Parabola given by
• Where
The Device Transconductance Parameter, KP, Depends on the
Construction of the FET• KP for nFETs is
typically 10-100 µA/V2
toGStoGSDS VvVvv and
22 DSDStoGSD vvVvKi
2
KP
L
WK
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx24
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
PinchOff In order to form a
complete channel, every point, x, along the channel must have a voltage difference greater than Vto
That is, need
The greater this qty, the thicker the conducting Layer
Now as vDS is increased eventually at x = L where vchan = vDS
The Channel Thickness goes to ZERO. This is called PINCH-OFF
tochanGS Vxvv
x
tochanGS VLvv
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx25
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
PinchOff Illustrated The layer is
THICKEST at the Source and ZERO at the Drain when
Thus Have PinchOff when
At this Point the channel is Very Thick at the Source-End, and Zero-Thick at the Drain End →
toDSGS
tochanGS
Vvv
VLvv
or
GStoDS vVv
Pinched Offat Drain
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx26
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
TriOde Region Summarized
vDS ≤ (vGS − Vto) → iD = f(vDS , VGS)
Start of TriOde → Channel Formation
Finish of TriOde →
DrainPinchOff
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx27
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
PinchOff iD Saturation
As vDS increases the “PinchOff Point”, xpop, Moves BACKWARDS towards the Source
Once the channel Pinches Off, the drain current, iD, NO Longer increases with increasing vDS
In other words, for a given vGS, the Current “Saturates” (stays constant) After PinchOff as shown below
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx28
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
nMOSFET complete vi Curve
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx29
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MOSFET Operation Summary1. Cut-Off Region – In this
region the gate voltage is less than the Threshold voltage Vto and therefore very little current flows.
2. Triode Region – In this mode the device is operating below pinch-off and is effectively a variable resistor.
3. Saturation Region – This is the main operating region for the device. The drain voltage has to be greater than the gate voltage minus the Threshold voltage.
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx30
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Operation in Saturation Notice that in SAT iD
varies with vGS
• Note that vDS does NOT appear in this Equation
• vDS (on vi curve) does NOT affect iD after Channel-PinchOff
• In SAT a MOSFET is true 3-terminal device; current depends ONLY on the CONTROL Signal, vGS
2toGSD VvKi
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx31
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Saturation Summarized
vDS ≥ (vGS − Vto) → iD ≠ f(vDS)
PinchOffMoved BACK from Drain
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx32
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Triode↔Saturation Boundary At the boundary
Line the nMOSFET just Barely Pinches Off at the Drain end thus:
By KVL Substituting Find
Or at the Boundary
toGD Vv
Boundary Line
DSGSGD vvv
toDSGSGD Vvvv
toDSGS Vvv
Sub for vGS into iD,sat Eqn
2
2
totoDSD
toGSD
VVvKi
VvKi
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx33
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
nFET KVL
DSGSGD vvv or
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx34
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Triode↔Saturation Boundary Then then iD along
the Boundary
The Boundary is described by a Concave-UP Parabola that passes thru the origin
2DSD Kvi
Boundary Line
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx35
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Example 12.1 make vi Plot
Use Parameters from Example 12.1 to plot in MATLAB the vi Curve for an nMOSET
The Parameters• W = 160 µm• L = 2 µm (pretty large)• KP = 50 µA/V2
• Vto = 2V
Plot has multiple operating regions → must concatenate
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx36
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
The completed Plot
0 1 2 3 4 5 6 7 8 9 100
5
10
15
20
25
30
35
vDS (Volts)
iD (
mA
)
nMOSFET vi Curve - Ex 12.1
VGS<Vto
vGS=3V
vGS=4V
vGS=5V
vGS=6V
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx37
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MATLABCode-1
% Bruce Mayer, PE% ENGR43 * 14Jan12% file = nMOSFET_Plot_ex12_1_1201.mW = 160; % µmL = 2; % µmKP = 50; % µA/sq-VVto = 2' % V%% calc Parameter KK = (W/L)*KP/2; % µA/sqV)%% set vGS values that exceed CutOff at 2VvGS = [3, 4, 5, 6];%% calc boundary Triode/Sat boundary by finding iD at the START of sat% regioniDsat_uA = K*(vGS-Vto).^2; % in µAiDsat_mA = iDsat_uA/1000%% show cutoff linevDSco = linspace(0,10, 200);iDco = zeros(200);% DeBug Command => plot(vDSco, iDco, 'LineWidth', 3)% % Calc iD in Triode Region for vGS>Vto (Pinched off at Drain)%* use eqn (12.6) in textvDSsat = sqrt(iDsat_uA/K) % must take care with units%plot(vDSsat,iDsat_mA, '--*', 'LineWidth', 3), grid, xlabel('vDSsat'), ylabel('iDsat')disp('showing Triode-Sat Boundary - Hit any key to continue')pause%
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx38
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MATLABCode-2% then iD in triode region
vDSt1 = linspace(0, vDSsat(1)); % VvDSt2 = linspace(0, vDSsat(2))vDSt3 = linspace(0, vDSsat(3))vDSt4 = linspace(0, vDSsat(4))iDt1_mA = K*(2*(vGS(1)-Vto)*vDSt1-vDSt1.^2)/1000; % mAiDt2_mA = K*(2*(vGS(2)-Vto)*vDSt2-vDSt2.^2)/1000; % mAiDt3_mA = K*(2*(vGS(3)-Vto)*vDSt3-vDSt3.^2)/1000; % mAiDt4_mA = K*(2*(vGS(4)-Vto)*vDSt4-vDSt4.^2)/1000; % mA%%% DeBug Command =>plot(vDSt1,iDt1_mA, vDSt4,iDt4_mA)%% use TwoPoint Plots in SatiDsat1 =[iDsat_mA(1),iDsat_mA(1)] iDsat2 =[iDsat_mA(2),iDsat_mA(2)]iDsat3 =[iDsat_mA(3),iDsat_mA(3)]iDsat4 =[iDsat_mA(4),iDsat_mA(4)]vDSsat1 = [vDSsat(1), 10]vDSsat2 = [vDSsat(2), 10]vDSsat3 = [vDSsat(3), 10]vDSsat4 = [vDSsat(4), 10]%
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
MATLABCode-3%
% Now Concatenate to ocver Triode & Saturation RegionsiD1 = [iDt1_mA,iDsat1]vDS1 = [vDSt1, vDSsat1]iD2 = [iDt2_mA,iDsat2]vDS2 = [vDSt2, vDSsat2]iD3 = [iDt3_mA,iDsat3]vDS3 = [vDSt3, vDSsat3]iD4 = [iDt4_mA,iDsat4]vDS4 = [vDSt4, vDSsat4]%%% Finally Make Plotplot(vDSco, iDco,'b', vDS1, iD1,'c', vDS2, iD2,'g', vDS3, iD3,'m', vDS4, iD4,'r', 'LineWidth', 3),... grid, xlabel('vDS (Volts)'), ylabel('iD (mA)'), title('nMOSFET vi Curve - Ex 12.1'),... gtext('VGS<Vto'), gtext('vGS=3V'), gtext('vGS=4V'), gtext('vGS=5V'), gtext('vGS=6V')
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[email protected] • ENGR-43_Lec-12a_FETs-1.pptx40
Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
pMOSFET A “pMOS” FET is the
“Complement” to the nMOS version.
The channel is normally n-Type and a hole-populated conducting Channel is formed by applying a NEGATIVE vGS
Basically the pMOS version looks like the nMOS FET with voltage-polarities inverted
Channel
pMOSFETCircuitSymbol
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
p & n MOSFET Comparison
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
All Done for Today
3 & 4Connection
nFET
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
Bruce Mayer, PERegistered Electrical & Mechanical Engineer
Engineering 43
Appendix
Diode vi Curves
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
2
KP
L
WK
oxnCKP
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis
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Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis