Bluetooth IC TC35661 Application Note for Hardware Edition ......TC35661 Application Note for HW...

TC35661 Application Note for HW

©2015 TOSHIBA Corporation 2015-08-27 1

Bluetooth® IC TC35661

Application Note for Hardware Edition

Rev 1.00

The Bluetooth® word mark and logos are registered trademarks owned by Bluetooth SIG, Inc.

ARM is a registered trademark of ARM Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.


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Contents 1. About This Document ............................................................................................................................................. 3 2. System Configuration Example .............................................................................................................................. 4 3. Reference Board Appearance and Baseboard Connection..................................................................................... 5

3.1. Reference Board Outline View ........................................................................................................................ 5 3.2. How to Connect with the Baseboard ............................................................................................................... 6

4. Reference Board Circuit.......................................................................................................................................... 7 4.1. Reference Board schematics ............................................................................................................................ 7 4.2. Reference Board Parts List ............................................................................................................................. 8 4.3. Reference Board Layout pattern ................................................................................................................... 10

5. Pattern Layout Guide ........................................................................................................................................... 12 5.1. Introduction ................................................................................................................................................... 12 5.2. Board Layout Notes ....................................................................................................................................... 12

5.2.1. For Set Board .......................................................................................................................................... 12 5.2.2. RF Portion ............................................................................................................................................... 12

5.3. Ball Assignment and GND Boundary ........................................................................................................... 13 5.4. Coplanar Strip Line ....................................................................................................................................... 14 5.5. Reference Board Antenna Characteristics .................................................................................................... 15

5.5.1. Chip Antenna .......................................................................................................................................... 15 5.5.2. Pattern Antenna ..................................................................................................................................... 16

5.6. Reference Board Characteristics ................................................................................................................... 18 6. RFIO Impedance Data .......................................................................................................................................... 24

6.1. TC35661SBG 0.5mm-pitch Package ............................................................................................................. 24 6.1.1. Impedance Data ...................................................................................................................................... 24 6.1.2. DUT (Reference) ..................................................................................................................................... 25

6.2. TC35661IDBG/DBG 0.8mm-pitch Package .................................................................................................. 26 6.2.1. Impedance Data ...................................................................................................................................... 26 6.2.2. DUT (Reference) ..................................................................................................................................... 27

7. RF Parameter Adjustment ................................................................................................................................... 28 7.1. 26 MHz Crystal Oscillator Adjustment ......................................................................................................... 28

7.1.1. How to Change the Crystal Oscillator Adjustment ............................................................................... 28 7.1.2. Crystal Oscillator Parameter ................................................................................................................. 30 RESTRICTIONS ON PRODUCT USE .................................................................................................................... 31


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1. About This Document This document is a design guide for schematics and PCB layouts of TC35661. The schematics are based on a circuit design of our evaluation board and reference board, and they include our

reference design of the RF part with the PCB antenna. This document also shows the frequency adjustment method of crystal oscillator circuit.


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2. System Configuration Example [Case] Host interface = UART, Reference Clock = OSC Connection, external EEPROM connection, chip antenna Each supported functions depend on ROM version. Please see the supported function sheet. The application circuits shown in this document are provided for reference purposes only. Especially, a thorough

evaluation is required on the phase of mass production design. Toshiba dose not grant the use of any industrial property rights with these examples of application circuits.

TC35661

DVDDA_1

DVDDA_2

DVDDB

LVDD33D

LVSS33_1

LVDD33A

A1

A6

H7

N.M

0Ω H5

H4

AVDD33PA

G5

G2

LVSS33_2

10pF

1000

pF

AGND

0.22

µH

0.22

µH

DVDD33

CDVSS_1

CDVSS_2

CDVSS_3

CDVSS_4

GND

0.1µ

F

10µF

G4

E5

E6

F5

F6

DVDD33USBA8

AGND

LDOUT12A

AVDD12SYN

AVDD12SG

G8

F1

18pF

0.1µ

F

AGND AGND AGND

G1

GND

1µF

AVDD12XE1

0.1µ

F

AGND AGND

1µF

AVSS12ADCF3

AVSS12SYNF2

AVSSSG1_1H1

AVSSSG1_2H3

AVSS12XE2

AGND

CVDD_1A7

GND GND

CVDD_2H6

0.1µ

F

1µF

VPGMC2

AGND

RFIOH21.0nH

AGND

3pF

AGND

2pF

1 4

2 3 5

AGNDAGND

100k

Ω

1.5p

F

5.1n

H

FeedFixing

AGND AGNDAGND

Antenna

RF connector

SAW FilterOUT IN

AGND

GND

XOIN

XOOUT

D1

D2

0Ω

3

2

4

1

15pF

15pF

AGND

AGND

AGNDTRSTXB3

TCKD6

TMSB1

TDIC5

TDOC4

TRCKC3

GPIO6E7

GPIO7F8

GPIO8F7

GPIO9D7

RESETXD5

GPIO0C7

USBDPB7

USBDMB8

GPIO15B5

GPIO14B6

GPIO16A5

X’tal

GPIO17A3

GPIO18B4

GPIO10B2

GPIO11A2

GPIO12C6

GPIO13D8

CLKREQC8

TMODE1C1

TMODE2D3

TRTESTAE3

TRTESTBE4

TRTESTCG3

TRTESTDF4

4

EEPROM

321

SDASCLWPVCC

GNDA2A1A0

5678

10kΩ

10kΩ

GND

AGND

GND

VDD33

GND

0.1μ

F

GPIO1A4

SLEEPCLKE8

UARTTX

UARTRX

RTS

CTS

RESETX

GPIO0

GPIO1

SLEEPCLK

GPIO10

GPIO11

GPIO12

GPIO13

GPIO16

GPIO17

GPIO5G6

GPIO4G7

GPIO3G8

GPIO5

GPIO4

GPIO3

GPIO2H8

GPIO2

10µF

Figure 2-1 Application Circuit Example


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3. Reference Board Appearance and Baseboard Connection This is about reference board using TC35661 0.8mm-pitch package. 3.1. Reference Board Outline View From Figure 3-1 to Figure 3-4, these outline views are reference board of TC35661 0.8mm-pitch package.

Figure 3-1 TC35661 Reference board (component side, chip antenna)

Figure 3-2 TC35661 Reference board (connector side, chip antenna)

Figure 3-3 TC35661 Reference board (connector side, pattern antenna)

Figure 3-4 TC35661 Reference board (connector side, pattern antenna)

TC35661IDBG

EEPROM

RF connector

Chip antenna

26 MHz Crystal

B to B connector

Pattern antenna


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3.2. How to Connect with the Baseboard To operate the reference board, need to be connected to the baseboard via interface board.

Figure 3-5 TC35661 Reference board, interface board and baseboard

Figure 3-6 TC35661 Interface board (connector side)

B to B connector

Interface board

Reference board

Baseboard


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4. Reference Board Circuit 4.1. Reference Board schematics

Figure 4-1 TC35661 reference board circuit


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4.2. Reference Board Parts List

Table 4-1 Parts List

No. Part number Name Value Size Supplier

C1 GCM155R11C334K Laminated ceramic capacitor 0.33 μF 1005 Murata Manufacturing

C2 GCM188C71A105K Ceramic capacitor 1 μF 1608 Murata Manufacturing

C3 GCM21BR70J106K Laminated ceramic capacitor 10 μF 2125 Murata Manufacturing



C6 GRM1552C1H2R0C Laminated ceramic capacitor 2 pF 1005 Murata Manufacturing

C7 GRM1552C1H100J Laminated ceramic capacitor 10 pF 1005 Murata Manufacturing




C11 LQG15HS1N0S Multilayer chip inductor for RF 1.0 nF 1005 Murata Manufacturing















C27 GRM1554C1H1R5C Laminated ceramic capacitor 1.5 pF 1005 Murata Manufacturing


CD1 CRS08 Schottky barrier diodes TOSHIBA

CD2 CRS08 Schottky barrier diodes TOSHIBA

CD3 PG1111C Chip LED Green 1608 STANLEY

IC1 TA48LS033F LDO regulator TOSHIBA

IC2 TC35661IDBG Bluetooth LSI TOSHIBA

IC3 S-24CS02AFT-TBH-G EEPROM Seiko Instruments

IC4 BU4228F Reset IC ROHM

J1 MM8130-2600 Connector with switch Murata Manufacturing

J2 48037-002 USB connector type A MOLEX

J3 14 5602 020 000 829 H+ Plug 0.4mm-pitch HIROSE ELECTRIC

L1 MLZ1608DR22DT SMD inductor 0.22 μH 1608 TDK


L3 GRM1552C1H3R0C Multilayer chip inductor for RF 3 pH 1005 Murata Manufacturing



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No. Part number Name Value Size Supplier

L5 LQW15AN5N1C Winding chip inductor for RF 5.1 nH 1005 Murata Manufacturing

R1 ERJ2GEJ102X Thick Film Chip Resistors 1 kΩ 1005 Panasonic

R2 ERJ2GEJ152X Thick Film Chip Resistors 1.5 kΩ 1005 Panasonic

R3 ERJ2GE0R00X Thick Film Chip Resistors 0 Ω 1005 Panasonic



R6 ERJ2GEJ220X Thick Film Chip Resistors 22 Ω 1005 Panasonic






R13 ERJ3GEYJ104V Thick Film Chip Resistors 100 kΩ 1608 Panasonic




R17 ERJ2GEJ153X Thick Film Chip Resistors 15k Ω 1005 Panasonic

R18 ERJ2GEJ153X Thick Film Chip Resistors 15k Ω 1005 Panasonic


SW1 MHS121 Slide switch FUJISOKU

SW2 MHS121 Slide switch FUJISOKU

X1 NX3225SA-26.000000MHz Crystal oscillator 26.000000 MHz

3.3 x 2.6 NIHON DEMPA KOGYO

E1 ANT098030CGS2442MB1 Chip antenna TDK

FL1 SAFEA2G44AA0F00 SAW Filter Murata Manufacturing


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4.3. Reference Board Layout pattern The reference board is 2-layer structure. This is chip antenna version pattern.

Figure 4-2 TC35661 reference board layout pattern (component side)

Figure 4-3 TC35661 reference board layout pattern (L1)


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Figure 4-4 TC35661 reference board layout pattern (L2)

Figure 4-5 TC35661 reference board layout pattern (component side silk)


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5. Pattern Layout Guide 5.1. Introduction Inside TC35661, analog and digital circuits are mixed. Among analog circuit, especially RF circuit has very weak signal (for example IC receiver sensitivity: -90dBm) so isolate

from noise from not only external IC but also digital circuit and its power supply. For set board, need isolation digital noise from HOST CPU etc. To prevent noise from other devices and the power supply line, need setting signal line in the inner layer of the board

and/or isolation between power supply and GND. 5.2. Board Layout Notes 5.2.1. For Set Board Please review and fully confirm placement of the IC in the whole board and antenna direction. How to take and GND power line, please refer to the taking of GND and power of our reference board.

It is assumed that when you take a certification BT logo on the set, test with RF cable or antenna. Please consider using the (antenna switch) antenna connector.

5.2.2. RF Portion Please refer to next page for the boundary of the analog and digital sections. Separate VDD/GND of analog from

VDD/GND of digital as far as possible. Do not overlap solid GND of analog with solid GND of digital as far as possible. There is a possibility that noise through

the parasitic capacitance corresponding to the area of overlap, generated from the digital circuit is jumping to the circuit in RF. Design RF line to be 50Ω impedance from RFIO pin to antenna. Please pull out in a straight line as much as possible. Please be placed so as to prevent the signal line and power

approaches. Please refer to Figure 5-2 for example pulling out, coplanar strip line.

It is recommended that between the antenna and the withdrawal of the RF line, using the antenna connector.


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5.3. Ball Assignment and GND Boundary This figure shows the ball assignment and GND boundary. Please refer to this figure to design layout.

Figure 5-1 TC35661 ball assignment and GND boundary

Yellow (D1, D2, D4, E1 to E4, F1 to F4, G1 to G5 and H1 to H5): Regulator and RF circuit Gray (E5, E6, F5 and F6) and pink (A7 and H6): GND of digital block Orange (G6 to G8, H7 and H8): Digital I/O port related DVDDB power supply Purple (A1 to A6, B1 to B6, C1 to C8, D3, D5 to D8, E7, E8, F7 and F8): Other digital I/O Please separate GND by blue line on the board.

Analog Potion Digital Potion


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5.4. Coplanar Strip Line This figure shows the coplanar strip line example with GND.

Figure 5-2 Coplanar strip line example

信号線 GND線GND線

GND層

スルーホール

IC side Antenna side

Through hole GND line GND line Signal line

Through hole

GND layer


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5.5. Reference Board Antenna Characteristics

Figure 5-3 Antenna coplanar strip line example

5.5.1. Chip Antenna

Figure 5-4 Antenna characteristics (TX_V)

Figure 5-5 Antenna characteristics (TX_H)

TDK Chip ANT

RX_H/TX_V

2.4 2.44 2.485

TDK Chip ANT

RX_V/TX_V

2.4 2.44 2.485

TDK Chip ANT

RX_H/TX_H

2.4 2.44 2.485

TDK Chip ANT

RX_V/TX_H

2.4 2.44 2.485


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Figure 5-6 Antenna characteristics (TX_H’)

5.5.2. Pattern Antenna

Figure 5-7 Antenna characteristics (TX_V)

TDK Chip ANT

RX_H/TX_H'

2.4 2.44 2.485

TDK Chip ANT

RX_V/TX_H'

2.4 2.44 2.485

Pattern_ANT

RX_H/TX_V

2.4 2.44 2.485

Pattern_ANT

RX_V/TX_V

2.4 2.44 2.485


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Figure 5-8 Antenna characteristics (TX_H)

Figure 5-9 Antenna characteristics (TX_H’)

Pattern ANT

RX_H/TX_H

2.4 2.44 2.485

Pattern ANT

RX_V/TX_H

2.4 2.44 2.485

Pattern AN T

RX_H/TX_H'

2.4 2.44 2.485

Pattern ANT

RX_V/TX_H'

2.4 2.44 2.485


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5.6. Reference Board Characteristics This list shows EV results of reference board.

Table 5-1 Reference board EV results list

Test Item Sub Item Packet bit ch. Condition Unit

Bluetooth® Spec. w/ SAW

min max R02

TRM/CA/01/C Output Power

DH5 PRBS9

0

peak

[dBm] -6 4

0.5

39 -0.1

78 -0.1

0

average

-0.1

39 -0.6

78 -0.6

TRM/CA/10/C EDR Relative

Transmit Power

P(DPSK)-P(GFSK)

2-DH5 PRBS9

0

min.

[dBc]

-4 1

-0.5

39 -0.5

78 -0.5

0

average -4 1

-0.5

39 -0.5

78 -0.5

3-DH5 PRBS9

0

min.

[dBc]

-4 1

-0.5

39 -0.5

78 -0.6

0

average -4 1

-0.5

39 -0.5

78 -0.5

TRM/CA/05/C 20dB Bandwidth

DH5 PRBS9

0

[kHz] 1000

925.6

39 924.1

78 923.8


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min max R02

TRM/CA/06/C Adjacent Channel Power

DH1 PRBS9 39

-5 MHz

[dBm]

-40

-58.6

-4 MHz -57.2

-3 MHz -54.6

-2 MHz

-20

-51.9

2 MHz -53.1

3 MHz

-40

-56.3

4 MHz -58.8

5 MHz -60.2

TRM/CA/11/C EDR Carrier Frequency

Stability

ωi

2-DH5 PRBS9 39

ave.

[kHz] -75 75

2.7

min. -2.9

max. 8.1

3-DH5 PRBS9 39

ave.

[kHz] -75 75

3.6

min. 0.7

max. 8.1

ωi+ωo

2-DH5 PRBS9 39

ave.

[kHz] -75 75

4.8

min. 4.5

max. 5.1

3-DH5 PRBS9 39

ave.

[kHz] -75 75

4.6

min. 4.4

max. 4.9

ωo m ax

2-DH5 PRBS9 39

ave.

[kHz] -15 15

2.0

min. -4.2

max. 7.7

3-DH5 PRBS9 39

ave.

[kHz] -15 15

0.7

min. -4.4

max. 3.9


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min max R02

TRM/CA/07/C Modulation Characteristics DH5

11110000 39 ∆f1avg (11110000) [kHz] 140 175 161.7

10101010 39

∆f2max _min

(10101010) 115 133.2

∆f2min _ave

(10101010) 137.8

∆f2max _max

(10101010) 172.4

∆f2avg (10101010) 152.4

39 ∆f2avg /∆f1avg - 0.8 0.9

TRM/CA/08/C ICFT DH5 PRBS9 39 ave.

[kHz] -75 75 7.0

min. 3.0 max. 11.6

TRM/CA/09/C Drift

DH1 10101010

39 ave.

[kHz]

-25 25 -5.1 abs.max 25 9.5

DH5 39 ave. -40 40 -5.3

abs.max 40 10.0

Drift Rate DH1 10101010 39 abs.max. [kHz/

50 μs] 20 4.2 DH5 4.9


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min max R02

TRM/CA/11/C EDR Modulation Accuracy

RMS DEVM

2-DH5 PRBS9 39 ave.

20% 4.6%

min. 4.2% max. 5.0%

3-DH5 PRBS9 39 ave.

13% 4.7%

min. 4.2% max. 5.3%

Peak DEVM

2-DH5 PRBS9 39 ave.

35% 12.2%

min. 9.7% max. 15.4%

3-DH5 PRBS9 39 ave.

25% 11.7%

min. 9.6% max. 16.2%

99%DEVM 2-DH5 PRBS9 39 [%] 99 99.99999

3-DH5 99.99999

TRM/CA/12/C EDR Differential Phase Encoding 2-DH1 "PRBS9

100 packet" 39 [%] 99 100

3-DH1 100

TRM/CA/13/C EDR In-band Spurious

Emissions 3-DH5 39

-5 MHz

[dBm] -40 -52.1

-4 MHz -50.7 -3 MHz -46.9 -2 MHz -20 -40.2 -1 MHz

[dB] -26 -40.1 1 MHz -39.8 2 MHz

[dBm]

-20 -41.0 3 MHz

-40 -47.8

4 MHz -51.2 5 MHz -52.5


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min max R02

RCV/CA/01/C Rx Sensitivity Dirty DH5 PRBS9 0

BER = 0.1% dBm -70

-88.9 39 -87.8 78 -88.0

RCV/CA/07/C EDR Rx Sensitivity Dirty

2-DH5 PRBS9 0

BER = 0.007% dBm -70

-90.8 39 -89.9 78 -90.1

3-DH5 PRBS9 0

BER = 0.007% dBm -70

-81.7 39 -80.6 78 -80.7

RCV/CA/08/C EDR BER Floor Performance

2M 8000000bi

ts PRBS9 39 RFin =

-60 dBm [%] 0.0007 0

3M 8000000bi

ts 0

RCV/CA/06/C Max Input Power DH1 PRBS9 39 RFin= -10 dBm [%] 0.1 0

RCV/CA/10/C EDR Max Input Power 2-DH5

PRBS9 39 RFin= -10 dBm [%] 0.1 0.000000

3-DH5 0.000000

RCV/CA/03/C C/I Performance DH5 D wave: PRBS9 U wave: GFSK

PRBS15 39

-3 MHz

[dB]

-40 -44.4 -2 MHz -30 -42.7 -1 MHz 0 -6.3 0 MHz 11 7.5 1 MHz 0 -5.8 2 MHz -20 -38.9 3 MHz -9 -45.1 4 MHz -20 -45.3 5 MHz -40 -46.1


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min max R02

RCV/CA/09/C

EDR C/I Performance 2-DH5

D wave: PRBS9 U wave: GFSK

PRBS15 CO-channe

l: same signal

(pi/4DQPSK)

39

-3 MHz

[dB]

-40 -50.2 -2 MHz -30 -47.0 -1 MHz 0 -12.9 0 MHz 13 8.1 1 MHz 0 -12.7 2 MHz -20 -44.6 3 MHz -7 -50.7 4 MHz -20 -51.0 5 MHz -40 -51.1

EDR C/I Performance 3-DH5

D wave: PRBS9 U wave: GFSK

PRBS15 CO-channe

l: same signal

(pi/4DQPSK)

39

-3 MHz

[dB]

-33 -44.4 -2 MHz -25 -40.8 -1 MHz 5 -6.6 0 MHz 21 15.1 1 MHz 5 -6.0 2 MHz -13 -38.5 3 MHz 0 -44.9 4 MHz -13 -45.2 5 MHz -33 -45.4

RCV/CA/05/C Intermodulation DH1

0 -5 MHz

[dBm] -39

-23.7 +5 MHz -23.8

39 -5 MHz -23.4 +5 MHz -22.0

78 -5 MHz -22.9 +5 MHz -22.4


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6. RFIO Impedance Data 6.1. TC35661SBG 0.5mm-pitch Package 6.1.1. Impedance Data

Figure 6-1 0.5mm-pitch RFIO impedance (RX)

Figure 6-2 0.5mm-pitch RFIO impedance (TX)

Table 6-1 0.5mm-pitch RFIO impedance list

Frequency RX (S11) RX VSWR TX (S11) TX VSWR

2.402GHz 9.721Ω 20.599Ω 1.364nH 6.068 11.616Ω 17.918Ω1.186nH 4.856

2.441GHz 9.221Ω 23.784Ω 1.550nH 6.677 10.342Ω 21.222Ω 1.383nH 5.406

2.480GHz 8.960Ω 26.766Ω 1.717nH 7.222 10.438Ω 24.396Ω 1.565pF 5.901


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6.1.2. DUT (Reference) Measured by ungilding the pattern next to RFIO pin and adding semi-rigid cable throw 18pF as follows (Corrected electric length between semi-rigid cable and measure)

Figure 6-3 DUT circuit RF potion

18pF


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6.2. TC35661IDBG/DBG 0.8mm-pitch Package 6.2.1. Impedance Data

Figure 6-4 0.8mm-pitch RFIO impedance (RX)

Figure 6-5 0.8mm-pitch RFIO impedance (TX)


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Table 6-2 0.5mm-pitch RFIO impedance list

Frequency RX (S11) RX VSWR TX (S11) TX VSWR

2.402GHz 9.0802Ω 25.757Ω 1.7066nH 7.0067 10.477Ω 21.055Ω 1.3951nH 5.6532

2.441GHz 8.9700Ω 28.488Ω 1.8574nH 7.4324 10.010Ω 24.9753Ω 1.6284nH 6.2851

2.480GHz 9.1068Ω 30.832Ω 1.9786nH 7.6292 8.8392Ω 28.021Ω 1.7983pF 7.4762

6.2.2. DUT (Reference) This figure shows DUT for measure S parameter (RF board, IC mounted, pattern cut)

Figure 6-6 DUT for measure S parameter

Measured by removing C28 next to RFIO and adding semi-rigid cable throw 18pF as follows (Corrected electric length between semi-rigid cable and measure)

Figure 6-7 DUT circuit RF potion

18pF


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7. RF Parameter Adjustment 7.1. 26 MHz Crystal Oscillator Adjustment 7.1.1. How to Change the Crystal Oscillator Adjustment To adjust 26 MHz crystal oscillator, please refer this chapter. 1. Operate the HCI Tester 2. Check the current RF parameter using “LOC_DBUS_READ”

Click “Help” -> “LOC_DBUS_READ”

Choose register to be checked.

The following window shows an example of checking “OSC tuning.”

OSC tuning parameter is stored in a register of which Dev addr = 0x5, addr = 0x06

Check the value on main window. The value is indicated in 16 bit Hex data. In the following window, the parameter value is indicated as “value = 0x0100”


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3. Set RF parameter using “Channel3_LOC_DBUS_WRITE”

Click “Help” -> “Channel3_LOC_DBUS_WRITE”

4. Set RF parameter

The following window shows an example to change the parameter from 0x0100 to 0x0180.

5. Check the result of “LOC_DBUS_WRITE” on main window.

In the following window, the result is indicated as “(LOC_DBUS_WRITE)st = 0x00 (LOC OK)”


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The written data can bechecked using “Channel3_LOC_DBUS_READ” comand. (Note) Although “LOC_DBUS_WRITE” can be executed during Chiron is working, ARM 7 might freeze depends on

the command execution timing.

7.1.2. Crystal Oscillator Parameter Frequency of Crystal oscillator l (fine adjustment with internal capacitance array)

Dev addr = 0x05 addr = 0x06 (middle 2 digits) Default value: 10 (as at 26th Oct 2011. Shown as “0x0100” In 4 digits) Max value: 1F (0x01F0) Min value: 00 (0x0000, internal capacitance = 0) Range is around 2 to 4 kHz per 1bit (It depends on board design and external capacitance.) RF frequency example

Figure 7-1 Variable frequency range

-30

-20

-10

0

10

20

30

0 5 10 15 20 25 30

delta

Rai

o Fr

eq. [

kHz]

bit value

Radio Frequency Range with Crystal Triming


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RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information

in this document, and related hardware, software and systems (collectively "Product") without notice.

• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.

• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.

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