BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.
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Transcript of BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.
![Page 1: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/1.jpg)
1
BJT Transistor Modeling - I
Electronic CircuitsFirst Term Second Year (11CS Batch)
![Page 2: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/2.jpg)
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Model
A model is the combination of circuit elements, properly chosen, that best approximates the actual behaviour of a semiconductor device under specific operating conditions.
Small Signal BJT Model
re Model Hybrid Parameter Model
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Small Signal AC Analysis
1. Set all dc sources to zero and replace them by a short-circuit equivalent circuit.
2. Replace all capacitors by a short circuit equivalent.
3. Remove all elements bypassed by the short circuit equivalents introduced by steps 1 and 2.
4. Redraw the network in a more convenient and logical form.
![Page 4: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/4.jpg)
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AC Analysis
Consider the following BJT circuit
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AC Analysis
Step 1,2,3:
Step 4: Transistor Small Signal ac
Equivalent Circuit
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The Important Parameters: Zi, Z0, Av , Ai
Input Impedance (Zi):
Two-PortSystem
Ii
ZiVi
+-
I0
Z0 V0
+-
i
ii I
VZ
![Page 7: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/7.jpg)
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Input Impedance (Cont.)
Two-PortSystem
RSense
VS
Vi Zi
Ii
+
-
sense
isi R
VVI
i
ii I
VZ
![Page 8: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/8.jpg)
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Example: For the system of the following Fig., determine the level of input impedance.
Two-PortSystem
RSense
VS Vi = 1.2 mv Zi
Ii
+
-
2mv
1k +
-
Solution: A8.0101
102.1102
R
VVI 3
33
sense
isi
k5.1A8.0
mv2.1
I
VZ
i
ii
![Page 9: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/9.jpg)
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Output Impedance (Z0)
sense
00 R
VVI
0
00 I
VZ
The output impedance is determined at the output terminals looking back into the System with the applied signal set to zero.
The output impedance of a BJT amplifier is resistive in nature and,depending on the configuration and placement of the resistive elements, Z0 can vary from a few ohms to a level that can exceed2 M.
![Page 10: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/10.jpg)
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Example: For the system of the following Figure, determine the level of output impedance.
Solution:
A16100020
106801
R
VVI
3
sense
00
k5.421016
10680
I
VZ 6
3
0
00
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Amplifier Gain• Gain– A multiplier that exists between the input and
output of a circuit.– For example, if the gain of an amplifier is 100,
then the output signal is 100 times as great as the input signal under normal operating conditions.
• Types of Gain:– Voltage gain, AV
– Current gain, Ai
– Power gain, Ap
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Voltage Gain
The small signal ac voltage gain is defined as
For the system of the above Fig., a load has not been connected to the output terminal, the gain is therefore referred to as no load voltage gain (AvNL).
For the transistor amplifiers, the no load gain is greater than the loaded voltage gain.
i
ov V
VA
![Page 13: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/13.jpg)
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Using the Voltage Divider Rule
AvNL VS Vi
Zi
Ii
+
-
Rs +
-
+
-
V0
si
sii RZ
VZV
si
i
s
i
RZ
Z
V
V
i
0
s
i
s
0v V
V
V
V
V
VA
s
vNLsi
i
s
0v A
RZ
Z
V
VA
s
![Page 14: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/14.jpg)
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Example: For the BJT amplifier of the following Fig., determine Vi, Ii, Zi and Avs.
Solution:
BJT amplifierAvNL = 320
Vs = 40mv Vi
Zi
+ Rs
+
-
+
-
V0 = 7.68v
-
1.2k
mV24320
68.7
A
VV
V
VA
vNL
0i
i
0vNL
A33.13k2.1
mV24mV40
R
VVI
s
isi
,k8.1A33.13
mV24
I
VZ
i
ii
192)320(k2.1k8.1
k8.1
ARZ
ZA vNL
si
ivs
![Page 15: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/15.jpg)
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Current Gain (Ai)
BJTamplifier RL V0
+
-
I0
Vi Zi
+
-i
0i I
IA
From the circuit
i
ii Z
VI and
L
00 R
VI
Li
i0
ii
L0
i
0i RV
ZV
ZV
RV
I
IA
L
ivi R
ZAA
![Page 16: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/16.jpg)
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Example: For the given BJT circuit, determine:(a) Ii
(b) Zi
(c) V0
(d) I0
(e) Ai.
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The re Transistor Model
(a) Common Base (PNP) Configuration Ie
Ic =Iere
Ie Ic
Ee I
mV26r
ei rZ
0Z
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Voltage Gain:fV0 = -I0RL
= -(-Ic)RL
V0 = IeRL
and Vi = IeZi = Iere
Therefore,
BJTCommon-base
Transistoramplifier
RL V0
+
-
Vi Zi
+
-
Ic = IeIe
Z0 = I0
ee
Le
i
0v rI
RI
V
VA
e
Lv r
RA
For the current gain
e
e
e
c
i
0i I
I
I
I
I
IA
iA
![Page 19: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/19.jpg)
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Example: For a common-base configuration with IE = 4mA, = 0.98, and an ac signal of 2mV applied between the base and ammeter terminals:
(a) Determine the input impedance(b) Calculate the voltage gain if a load of 0.56 k is
connected to the input terminals.(c) Find the output impedance and current gain.Solution:(d) Input Impedance = Zi = re = 2610-3/(410-3 ) = 6.5
(b) 43.845.6
k56.098.0
r
RA
e
Lv
,Z0 (c) 98.0A i
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The re Transistor Model
Common Emitter Configuration:
Ic = Ib
IcIc
Ib Ib
(a) CE (NPN) Configuration (b) re Model
bc II bbbce IIIII
bbe II)1(I
Ie
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Ic = IbIi = Ib
vbe re vi
Ie
b
eb
b
ee
b
be
i
ii I
rI
I
rI
I
V
I
VZ
ei rZ
BJTCommon-
emitterTransistoramplifier
RL V0
+
-
Vi Zi
+
-
I0 = Ic = IbIi =Ib
Z0 =
Lb
LcL00
RI
RIRIV
ebiii rIZIV
eb
Lb
i
0v rI
RI
V
VA
e
Lv r
RA
b
b
b
c
i
0i I
I
I
I
I
IA
iA
![Page 22: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/22.jpg)
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Example: Given = 120 and IE = 3.2 mA for a common-emitter configuration with r0 = , determine:
(a) Zi
(b) Av if a load of 2 k is applied.
(c) Ai with 2 k load.
Solution: (a)
(b) Av = -RL/re = -2000/8.125 = -246.15
(c) Ai = = 120
,125.8mA2.3
mV26re 975125.8120rZ ei
![Page 23: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/23.jpg)
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re Model for the Common-Emitter Configuration
Note: r0 may be computed from the BJT output characteristics.
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Common Emitter Fixed Biased Configuration
(a) CE Fixed Bias Configuration(b) All capacitors and dc power supply removed
(c) Circuit with the substitution of the re model
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From Fig. (c) of the previous slide, the input impedance may be computed as
Zi = RB ||re ohms
or
eB
Bei rR
RrZ
In the majority of situations, RB 10re. In such cases
B
Bei R
RrZ
ei rZ
The output impedance is: Z0 = r0 ||RC
or
![Page 26: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/26.jpg)
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C0
C00 Rr
RrZ
If r0 10RC
C0 RZ
Voltage Gain:
C0
0Cb0Cb0 Rr
rRIr||RIV
Bute
ib r
VI
C0
0C
e
i0 Rr
rR
r
VV
or
![Page 27: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/27.jpg)
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C0e
0C
i
0v Rrr
rR
V
VA
If r0 10RC, then
0e
0Cv rr
rRA
or
e
Cv r
RA
Current Gain:
C0
b00 Rr
IrI
eB
iB
C0
00 rR
IR
Rr
rI
ButeB
iBb rR
)I)(R(I
eBC0
0B
i
0i rRRr
rR
I
IA
If r0 10RC and RB 10re , then
iA
B0
0Bi Rr
rRA
C
ivi R
ZAA
Also, note that
![Page 28: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/28.jpg)
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Example: For the given network(a) Determine re.
(b) Find Zi (with r0 = ).
(c) Calculate Z0 (with r = ).
(d) Determine Av (with r = ).
(e) Find Ai (with r = ).
(f) Repeat parts (c) through (e)including r = 50 k in all calculations and compare results.
Solution:(a) A04.24
k470
7.012
R
VVI
B
BECCB
mA428.2A04.241100I1I BE
![Page 29: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/29.jpg)
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71.10mA428.2
mV26
I
mV26r
Ee
(b)
k069.1
71.10100k470
k47071.10100
rR
RrZ
eB
Bei
(c) k3RZ C0
(d) 11.28071.10
k3
r
RA
e
Cv
(e) 100A i
(f)
k83.2Rr
RrZ
C0
C00
24.264Rrr
rR
V
VA
C0e
0C
i
0v
13.94rRRr
rR
I
IA
eBC0
0B
i
0i
![Page 30: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/30.jpg)
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Voltage Divider Bias
![Page 31: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/31.jpg)
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Input Impedance:
e21i r
1
R
1
R
1
Z
1
e21
21ei rRR
RRrZ
Output Impedance:
C00 R
1
r
1
Z
1
C0
C00 Rr
RrZ
If r0 10RC
C0 RZ
Voltage Gain:
C0
C0b0Cb0 Rr
RrIr||RIV
Bute
ib r
VI
C0
C0
e
i0 Rr
Rr
r
VV
0Ce
C0
i
0v rRr
Rr
V
VA
If r0 10RC
e
Cv r
RA
![Page 32: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/32.jpg)
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Current Gain:
eC0
0
i
0i r'RRr
r'R
I
IA
If r0 10RC
e0
0
i
0i r'Rr
r'R
I
IA
Where R’ = R1||R2
ei r'R
'RA
Also note that
C
ivi R
ZAA
![Page 33: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/33.jpg)
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Example: For the network shown in the Fig., determine:
(a) re (b) Zi (c) Z0 (r0 = ) (d) Av (r0 = )
(e) Ai (r0 = ) (f) The parameters of part (b) throughif r0 = 50 k.
Solution: (a)v81.2)22(
k2.8k56
k2.8V
vRR
RV CC
21
2B
v11.27.081.2VVV BEBE
mA41.1k5.1
11.2
R
VI
E
EE
44.18mA41.1
mV26
I
mV26r
Ee
![Page 34: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/34.jpg)
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k35.1
rRR
RRrZ
e21
21ei(b)
(c) k8.6RZ C0
(d) 76.36844.18
k8.6
r
RA
e
Cv
(e) ,k15.7k56k2.8
k56k2.8
RR
RR'R
21
21
(f)
04.73r'R
'RA
ei
,35.1Z i
98.5Rr
RrZ
C0
C00
3.324rRr
RrA
0Ce
C0v
3.64r'RRr
r'RA
eC0
0i
![Page 35: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/35.jpg)
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CE Emitter Bias Configuration
Fig. (a)
Fig. (b)
Applying KVL to the input Side of Fig (b) we getVi = Ibre + IeRE
orVi = Ibre + ( + 1)IbRE
and the impedance Zb
is: b
Eeb
b
ib I
R1rI
I
VZ
Eeb R1rZ or
![Page 36: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/36.jpg)
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Since >> 1, therefore + 1 . \ Zb re + RE
or Eeb RrZ
Since RE is often much greater than re, the above equationis further reduced to
Eb RZ
Returning to Fig. (b), we havebBi Z||RZ
The output impedance Z0 is determined as:C0 RZ
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CE Emitter Bias Configuration• Voltage Gain:
b
ib Z
VI
and CbC00 RIRIV
Cb
i RZ
V
b
C
i
0v Z
R
V
VA
Substituting Zb = (re + RE)
Ee
Cv Rr
RA
and for the approximation Zb RE
E
C
i
0v R
R
V
VA
![Page 38: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/38.jpg)
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CE Emitter Bias Configuration
Current Gain:
bB
iBb ZR
IRI
bB
B
i
b
ZR
R
I
I
Since
In addition, I0 = Ib
b
0
I
I
so thatbB
B
i
0i ZR
R
I
IA
bB
Bi ZR
RA
C
iii R
ZAA or
![Page 39: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/39.jpg)
39
Example: For the network of the given Fig., determine (using appropriate approximations):(a) re (b) Zi (c) Z0 (d) Av and (e) Ai.
Solution:(a) Testing RE > 10R2
(210)(0.68k) > 10(10k) 142.8k > 100k satisfied. V6.1
k10k90
k10V
RR
RV CC
21
2B
V9.07.06.1VVV BEBE
mA324.1k68.0
9.0
R
VI
E
EE
64.19
324.1
mV26
I
mV26r
Ee
![Page 40: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/40.jpg)
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(b) The ac equivalent circuit is shown here.From this circuit
The testing conditions r0 10(RC +RE ) and r0 10RC are both satisfied. Using the
appropriate approximations yieldsZb RE = 142.8 k
Zi = RB||Zb = 9k||142.8k = 8.47k
(c) Z0 = RC = 2.2k
(d) Av = -RC/RE = -3.24
(e) Ai = -AvZi/RL = 144.1
k9RR
RRR||R'RR
21
2121B
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Emitter Follower Configuration
Emitter Follower Configuration re Model for EF Configuration
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Emitter Follower Configuration
Input Impedance (Zi):
Zi = RB||Zb
With ZB = re + ( + 1)RE.
orZb (re + RE)
and Zb RE.
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Emitter Follower Configuration
Output Impedance (Z0):
b
ib Z
VI
and
b
ibe Z
V1I1I
Substituting for Zb gives
Ee
ie R1r
V1I
or
Ee
ie
R1
rV
I
![Page 44: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/44.jpg)
44
Emitter Follower Configurationbut
1
and
eee rr
1
r
so that
Ee
ie Rr
VI
If we now constructthe network defined By the above equation:
Ee
EeEe0 Rr
RrR||rZ
Since RE >> re, so
e0 rZ
![Page 45: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/45.jpg)
45
Emitter Follower ConfigurationVoltage Gain (AV):
From the circuit given belowWe have
eE
iE0 rR
VRV
eE
E
i
0V rR
R
V
VA
Since RE >> re
1AV
![Page 46: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/46.jpg)
46
Emitter Follower Configuration
From the Fig.
bB
iBb ZR
IRI
orbB
B
i
b
ZR
R
I
I
and be0 I1II
1I
I
b
0 or
so that
![Page 47: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/47.jpg)
47
Emitter Follower Circuit
i
b
b
0
i
0i I
I
I
I
I
IA
bB
B
ZR
R1
and since ( + 1) ,
bB
Bi ZR
RA
or
E
iVi R
ZAA
![Page 48: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/48.jpg)
48
Example: For the emitter follower network of the Fig., determine (a) re (b) Zi (c) Z0 (d) AV (e) Ai.
Solution: (a)
A42.20R1R
VVI
EB
BECCB
mA062.2I1I BE
61.12mA062.2
mV26
I
mV26r
Ee
(b) Zb = re + ( + 1)R = 334.56 kZi = RB||ZB = 132.72k
![Page 49: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/49.jpg)
49
(c) Z0 = RE||re = 12.56
(d) 1996.0rR
RA
eE
EV
(e) 67.39ZR
RA
bB
Bi
![Page 50: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/50.jpg)
50
Collector Feedback Configuration
![Page 51: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/51.jpg)
51
Collector Feedback Configuration
Input Impedance (Zi):
F
i0
R
VV'I
With V0 = -I0RC and I0 = Ib + I’
Since Ib is generally much largerthan I’,I0 Ib andV0 = -(Ib)(RC) = -IbRC
Bute
ib r
VI
and
![Page 52: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/52.jpg)
52
Collector Feedback Configuration
ie
CC
e
i0 V
r
RR
r
VV
Therefore
ie
C
FF
i
Fe
iC
F
i
F
0
F
i0 Vr
R1
R
1
R
V
Rr
VR
R
V
R
V
R
VV'I
The result is eeieiebi r'IrIr'IIrIV
iee
C
Feiebi Vr
r
R1
R
1rIrIV
![Page 53: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/53.jpg)
53
Collector Feedback Configuration
eie
C
F
ei rI
r
R1
R
r1V
e
C
F
e
e
i
ii
r
R1
R
r1
r
I
VZ
But RC is usually much greater than re and 1 + RC/re RC/re
So that
F
C
ei
R
R1
rZ
F
C
ei
RR1
rZ
![Page 54: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/54.jpg)
54
Collector Feedback Configuration
Output Impedance (Z0):
If we set Vi to zero as required to define Z0, the network will appear as shown below and
Z0 = RC||RF
![Page 55: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/55.jpg)
55
Collector Feedback Configuration
Voltage Gain (AV):
At node C:'III b0
For typical values, Ib >> I’ and I0 Ib.V0 = -I0RC = -(Ib)RC
Substituting Ib = Vi/re gives usC
e
i0 R
r
VV
and
e
C
i
0V r
R
V
VA
![Page 56: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/56.jpg)
56
Collector Feedback ConfigurationCurrent Gain (Ai):
Applying Kirchhoff’s law
Vi + VRF - V0 = 0
and Ibre + (Ib – Ii)RF + I0RC = 0
Using I0 Ib, we have
Ibre + IbRF – IiRF + IbRC = 0
Ib(re + RF + RC) = IiRF
Substituting Ib = I0/ from I0 = Ib yields
![Page 57: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/57.jpg)
57
Collector Feedback Configuration
FiCFe0 RIRRr
I
and
CFe
iF0 RRr
IRI
In general RF + RC >> re
CF
iF0 RR
IRI
CF
F
i
0i RR
R
I
IA
For RC >> RF,
C
F
i
0i R
R
I
IA
or
C
F
i
0i R
R
I
IA
![Page 58: BJT Transistor Modeling - I Electronic Circuits First Term Second Year (11CS Batch) 1.](https://reader034.fdocuments.us/reader034/viewer/2022050908/56649e455503460f94b3a524/html5/thumbnails/58.jpg)
58
Example: For the given network, determine (a) re (b) Zi (c) Z0 (d) AV (e) Ai.
Solution: (a)
(b)
(c) Z0 = RC||RF = 2.66k
A53.11RR
VVI
CF
BECCB
mA32.2I1I BE
21.11I
mV26r
Ee
5.560
RR1
rZ
F
C
ei
(d) AV = -RC/re = -240.86
(e) 50RR
RA
CF
Fi