Bit Error Rate Detection in High Energy Physics Experiments ...

BachelorarbeitTugba Karakaya

Bit Error Rate Detection in High Energy Physics Experimentsimplemented on an FPGA

Fakultt Technik und InformatikStudiendepartment Informatik

Faculty of Engineering and Computer ScienceDepartment of Computer Science

Tugba Karakaya

Bit Error Rate Detection in High Energy Physics Experimentsimplemented on an FPGA

Bachelorarbeit eingereicht im Rahmen der Bachelorprfung

im Studiengang Bachelor of Science Technische Informatikam Department Informatikder Fakultt Technik und Informatikder Hochschule fr Angewandte Wissenschaften Hamburg

Betreuender Prfer: Prof. Dr.-Ing. Bernd SchwarzZweitgutachter: Prof. Dr. rer. nat Jrgen Reichardt

Eingereicht am: 03. Juni 2016

Tugba Karakaya

Thema der ArbeitBit Error Rate Detection in High Energy Physics Experiments implemented on an FPGA

StichworteBitfehlerrate, Bitfehlerratentest, Field Programmable Gate Array, Pseudo-random Bit Stream,Mustergenerator, Linear Rckgekoppeltes Schieberegister, One-to-Many, Many-to-One, GigabitTransceiver Protokoll, Reed-Solomon Vorwrtsfehlerkorrektur, next generation Front End Con-troller, next generation Clock Control Module, Compact Muon Solenoid, Hadron Calorimeter,Monomode-Glasfaser, Multimode-Glasfaser

KurzzusammenfassungDie Front-End Elektronik, welche fr das Auslesen der Sensoren des Compact Muon Solenoid(CMS) Hadron Calorimeter (HCAL) eingesetzt wird, wird durch ein Back-End-System fernge-steuert. Da die Sensoren einer hohen Strahlung und einem starken magnetischen Feld ausgesetztsind, erfolgt die Kommunikation der beiden Systeme (Front-und Back-End) ber einen Licht-wellenleiter mit einer Bandbreite von 4,8 Gb/s in beide Richtungen. Um einen kontinuierlichenBetrieb zu gewhrleisten und die Diagnose von eventuellen Problemen zu ermglichen, ist einezuverlssige Kommunikation unerlsslich. Die Erkennung von Kommunikationsfehler ist zwin-gend fr die Steuerung des Systems erforderlich. Die vorliegende Arbeit befasst sich mit demDesign und der Implementierung einer Bitfehlerraten-Erkennung (BER) auf dem Field Program-mable Gate Array (FPGA) des next generation-Front-End-Controllers (ngFEC). Die Bitfehler-rate gilt als einer der grundlegenden Messverfahren bei der Leistungsermittlung von digitalenKommunikationssystemen. Der Bitfehlerratentest (BERT) besteht aus zwei Komponenten, demMustergenerator sowie dem Modul zur Erfassung von Fehlern. Die Leistung der BER-Technikin der Kommunikation zwischen dem Front-End und Back-End-System wird unter Verwendungeines generischen Zufallszahlengenerators (N-Bit PRBS) ermittelt. Das Fehlererkennungsmoduldas in der VHDL-Programmiersprache implementiert wurde, kommt fr die Fehlerauswertungauf dem Kintex-7 FPGA zum Einsatz. Als Entwicklungsumgebung wird das Xilinx ISE-Tooleingesetzt, dieses wurde fr die Implementierung des BERT Designs sowie dem darstellen derfunktionalen und statische timing Simulation der VHDL-Modellen verwendet. Die Ergebnisseder BER Messungen werden ber eigenstndige Skripte die auf einem Server ausgefhrt wer-den erfasst.Der BERT wurde in verschieden Prfstnden sowie in einem Bestrahlungstest inder CHARM-Facility verwendet. In dieser Arbeit wird auf die Ergebnisse die erzielt wurdeneingegangen.Tugba Karakaya

Title of the paperBit Error Rate Detection in High Energy Physics Experiments implemented on an FPGA

KeywordsBit Error Rate, BER Test, Field Programmable Gate Array, Pseudo-random Binary Sequence,Pattern generator, Linear Feedback Shift Register, One-to-Many Structure, Many-to-One Struc-ture, Gigabit Transceiver protocol, Reed-Solomon Forward Error Correction, next generationFront End Controller, next generation Clock Control Module, Compact Muon Solenoid, HadronCalorimeter, Single mode fiber optic, Multi mode fiber optic

AbstractThe front-end readout electronics of the Compact Muon Solenoid (CMS) Hadron Calorimeter(HCAL) detector is controlled remotely by a back-end control system due to high radiationand a strong magnetic field. The transmission of the digital communication between back-endand front-end is established over a 4.8 Gbps fiber optic channel. In order to ensure continuousoperation and to enable diagnosis of possible problems, the communication is required to bereliable, thus detection of errors is crucial for the control system. To this end, the present thesisdeals with the design and the implementation of a Bit Error Rate (BER) detection on the fieldprogrammable gate array (FPGA) of the next generation Front End Control (ngFEC) module.BER is well know as one of the basic measures of the performance of any digital communicationsystem [1]. The Bit Error Rate Test (BERT) scheme used in this thesis consists of two modules:a pattern generator and an error detection module.The performance of the BER technique in the communication between the front-end readout

and the back-end control system is evaluated using a generic N-bit PRBS generator and anerror detection module implementation in the VHDL programming language on the Kintex R-7(XC7K420T) FPGA. The Xilinx ISE tool (software) is used to develop the implementation ofthe BERT and provides the functional and timing simulation of the VHDL models. The BERcount measurements are done via scripts built on a server. The BERT is employed in varioustest stands and at the CHARM irradiation beam test. The results are presented and discussedin the present thesis.

iv

Contents

1 Introduction 11.0.1 Challenges of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.0.2 Objectives of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.0.3 Organizations of the thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Experimental Setup at LHC 72.1 The Large Hadron Collider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 The Compact Muon Solenoid Experiment . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Superconducting Solenoid . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.2 Inner Tracking System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.3 Calorimeters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.4 Muon Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2.5 Trigger and Data Acquisition systems . . . . . . . . . . . . . . . . . . . . 142.2.6 Particle Identification at CMS . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 The CMS Hadron Calorimeter Readout Control System . . . . . . . . . . . . . . 152.3.1 CMS HCAL back-end TCA crate . . . . . . . . . . . . . . . . . . . . . . 162.3.2 CMS HCAL front-end crate . . . . . . . . . . . . . . . . . . . . . . . . . . 222.3.3 The communication system between ngFEC (Back-end) and ngCCM (Front-

end) using the GBT protocol . . . . . . . . . . . . . . . . . . . . . . . . . 24

3 Implementation Concept 273.1 The perspective of the bit error rate testing (BERT) . . . . . . . . . . . . . . . . 27

3.1.1 Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.1.2 Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.1.3 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 Proposed BERT for the ngFEC firmware . . . . . . . . . . . . . . . . . . . . . . . 323.2.1 Pseudo-random Binary Sequence . . . . . . . . . . . . . . . . . . . . . . . 343.2.2 Linear Feedback Shift Register . . . . . . . . . . . . . . . . . . . . . . . . 343.2.3 The tap function, tap positions and initial seed . . . . . . . . . . . . . . . 373.2.4 Block diagram and VHDL simulation results of the LFSRs . . . . . . . . . 38

4 Implementation 434.1 Design Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.1.1 Design of the Pseudo-random Binary Sequence generator . . . . . . . . . . 494.1.2 Functional VHDL Simulations of the Pseudo-random Binary Sequence

generator module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544.1.3 Design of the error detection module . . . . . . . . . . . . . . . . . . . . . 574.1.4 Functional VHDL Simulation of the error detection module . . . . . . . . 61

4.2 Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.2.1 Synthesis Results of the 23-bit PRBS . . . . . . . . . . . . . . . . . . . . . 634.2.2 Timing Simulation of the 23-bit PRBS and the error detection module . . 634.2.3 Hardware analysis of the Pseudo-random Binary Sequence generator and

error detection module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

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Contents

5 Control System Test Results 695.1 Control System Test at DESY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.1.1 Back-end, front-end electronics and cabling . . . . . . . . . . . . . . . . . 715.2 Control System Test Results at DESY . . . . . . . . . . . . . . . . . . . . . . . . 72

5.2.1 ngFEC and HF-ngCCM communication path using single mode fiber opticcable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.2.2 ngFEC and HF-ngCCM communication path using multi-mode fiber opticcable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.2.3 ngFEC and HB/HE-ngCCM communication path using single-mode fiberoptic cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.3 Control System Test at CERN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755.3.1 Back-end, front-end electronics and cabling . . . . . . . . . . . . . . . . . 76

5.4 Control System Test Results at CERN . . . . . . . . . . . . . . . . . . . . . . . . 785.4.1 ngFEC and HF-ngCCM communication path using single mode fiber optic

cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

6 Conclusion 856.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Acronyms 87

Bibliography 89

vi

1Introduction

Elementary particle physics addresses fundamental questions like What are the constituents ofmatter? and How do they interact?. Understanding the forces and the constituents of matteris necessary to understand the universe and its development since the Big Bang. Within lessthan a billionth of a second after the Universe was formed, an enormous concentration of energytransformed into matter.Modern particle physics uses accelerators to create new particles in high-energy collisions and

to study the Big Bang by recreating conditions similar to the early universe in small volumes.The Large Hadron Collider (LHC), the worlds largest particle accelerator, is built to test theStandard Model1 of particle physics and find new particles which can provide answers to thefundamental questions in Nature and Universe. Proton-proton collisions in the LHC allow usto look back in time to the early universe, starting 1012 seconds after the Big Bang, i.e.approximately 13.75 billion years BC. As a result of these collisions, new particles are produced.These particles usually decay very quickly into lighter particles. At the LHC, their traces arerecorded by particle detector. With this purpose the multipurpose particle detectors are builtin the LHC ring: Compact Muon Solenoid (CMS) and A Toroidal LHC ApparatuS (ATLAS).The Deutsches Elektronen-Synchrotron (DESY) CMS Micro Telecommunications Computing

Architecture (TCA) group is participating in the implementation and testing of the new gen-eration front-end controller (ngFEC) for the upgrade of the CMS Hadron Calorimeter (HCAL)at the LHC. The ngFEC is designed to provide an increased reliability, faster data transmissionand higher power efficiency. Due to high radiation and powerful magnetic field, direct interven-tion during the LHC operation is not possible, therefore, the front-end readout electronics ofthe CMS HCAL has to be controlled remotely by a back-end control system. The transmissionof the digital communication between the back-end and the front-end modules over a 4.8 Gbpsoptical fiber must be reliable to ensure continuous operation and diagnosis of error sources.A bit error rate (BER) detection module is designed in the Field Programmable Gate Array(FPGA) of the FC7 board.The BER detection module, integrated into the GBT-ngCCM module of the Xilinx FGPA

(cf. Figure 2.10), consists of two modules: a generic Pseudo-random Binary Sequence (PRBS)generator using Linear Feedback Shift register (LFSR) implementation and a generic errordetection module. The PRBS implementation includes two different algorithms, variable initialseed (up to 31 bits) and feedback word size, and different tap versions to be compatible withlegacy CMS modules, such as HCAL forward (HF), HCAL barrel and HCAL encap (HB/HE)

1The Standard Model is a theory in particle physics from the 1970s which explains how the fundamental particlesinteract with each other, based on the four fundamental forces (the strong, the weak, the electromagnetic,and the gravitational forces ) [2].

1

1 Introduction

FC7 - Xilinx Kintex 7 FPGA

GBT bank

GBT link 1

GBT ngCCM

PRBS generator

DetectorComparator

& Error Counter

N

N

Transmitted PRBSSequence

Received PRBSSequence

serialTxWord

120

serialRxWord

120

84

84

StatusRegister

parallelTxData

parallelRxData

TRANSMITTER

RECEIVER

SerDes

ngFEC logic

CCMSERVER

PC TCA crate

Back-end Front-end

UDP

UDP

4.8 Gbps bidirectional optical link

ngCCM - igloo2 FPGA

bitwise error counter

word-wise error counter

Fig. 1.1: CMS HCAL ngFEC and ngCCM system control path communication including thengFECs firmware on the FPGA; ngFEC firmware illustrates where the BER modulesare included and placed; 4.8 bidirectional optical link illustrates the single-mode cablesfor 120 bit data transmission at a frequency of 40 MHz, established via the GigaBitTransceiver (GBT) protocol; the results of the error counters which are stored in thestatus registers can be monitored via the CCM server.

detector subsystems (cf. Chapter Section 2.2.3). The PRBS circuit for the HF generates a23-bit PRBS whereas the PRBS circuit for the HB/HE generates a 20-bit PRBS, which areincluded in the payload of the control link protocol Gigabit Transceiver (GBT) [3], [4], [5]. TheCERN-developed GBT is a serial protocol, used to establish serial multipurpose high-speedcommunication via an optical link between the ngFEC (back-end) and the ngCCM (front-end).The GBT protocol can provide data transfer rates up to 10 Gbps. The ngFEC and ngCCM-GBTimplementation operates over a 4.8 Gbps fiber channel. In addition to the generated PRBS, anerror detection module circuit is employed in the GBT-ngCCM of the ngFEC firmware to detectthe errors on the front-end side that can not be corrected by the Reed-Solomon (RS) forwarderror correction (FEC) [3]. The error detection module provides bitwise and word-wise errorcounters.

2

The error detection is needed in order to:

Detect the possible source of the errors in the front-end ngCCM VTRx module or in thelogic and hardware of the ngCCM board,

Detect clock synchronization issues between the front-end ngCCM and back-end ngFEC,

Ensure reliability of the response received from the ngCCM.

The ngFEC BERT implementation is tested at the DESY test stand. The implementation isthen, used at CERN to validate the optical transceivers. It is employed for the irradiation testin order to detect possible failures of the front-end electronics (FEE), and validate the opticaltransceivers of the communication link. The test results of the BER measurements are analyzedand possible improvements are discussed in Chapter 5.

1.0.1 Challenges of the thesis

To gain basic knowledge of the CMS Hadron Calorimeter Control System,

Work on the interface implementation of the electronics communication (on the ngFECfirmware) and the GBT protocol,

Employing the BER technique in the GBT communication protocol with given require-ments.

1.0.2 Objectives of the thesis

The objectives of the present thesis can be listed as follows:

Design and implement a generic N-bit Pseudo-random Bit Sequence (PRBS) generatorand a generic error detection module on a Kintex R-7 FPGA [6] in VHDL, and to carryout the measurement and analysis of the test results of the used BER technique.

Study the PRBS and LFSR based on Galois Field Arithmetic

Analyze the characteristics of the BER detection techniques that are implemented toensure reliable communication between the front-end and back-end modules over a 4.8Gbps optical fiber channel.

Study the link performance using a single-mode and multi-mode fiber optic cable at DESYin a non-radiated laboratory.

Study the link performance and validation of the optical transceivers at CERN in anirradiated area.

Verify that the PRBS pattern repeats after 2N 1 times and have all the possible 2N 1values.

3

1 Introduction

1.0.3 Organizations of the thesis

The present thesis conceptualizes the basic fundamentals of Bit Error Rate Detection techniquesand their implementation using a PRBS generator and an error detection module in the FC7Xilinx Kintex R-7 FPGA.

Chapter 2 describes the Large Hadron Collider, the CMS experiment and the CMS HCALreadout control system. The back-end and front-end electronics are described to gain abasic knowledge of the CMS Hadron Calorimeter Control System.

Chapter 3 discusses different types of pattern generator and error detection module schemesof the BER techniques. It also presents the structure of a digital communication systemand perspective of the BERT, where the definition of error, the types and the causes of er-rors were also introduced. The advantages of a PRBS generator using one-to-many LSFRis presented.

Chapter 4 discusses the design and implementation of a serial BERT for the commu-nication channel between the ngFEC and ngCCM. Moreover the functional and timingsimulation results of the system is presented.The following chart (cf. Fig. 1.2) summarizes the stages through which this design hasbeen carried out.

-Schematic Editor-VHDL

Functional VHDL simulation

VHDL synthesis

Logic optimisation, place and route

VHDL timing simulation

Static timing analysis

Programming of the componentson the FPGA

Hardware analysis

File A

File B

File C

Verification

Hardwareverification

Fig. 1.2: Design flow chart, modified from [7]

4

Chapter 5 describes the test stands at DESY and CERN. It presents the BERmeasurementand analysis including studies on the link performance.

Chapter 6 gives a summary of the thesis, and it presents future woks.

5

2Experimental Setup at LHC

2.1 The Large Hadron Collider . . . . . . . . . . . . . . . . . . . . . . . . 72.2 The Compact Muon Solenoid Experiment . . . . . . . . . . . . . . . 10

2.2.1 Superconducting Solenoid . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.2 Inner Tracking System . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.3 Calorimeters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.2.4 Muon Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.2.5 Trigger and Data Acquisition systems . . . . . . . . . . . . . . . . . . 142.2.6 Particle Identification at CMS . . . . . . . . . . . . . . . . . . . . . . 14

2.3 The CMS Hadron Calorimeter Readout Control System . . . . . . . 152.3.1 CMS HCAL back-end TCA crate . . . . . . . . . . . . . . . . . . . . 162.3.2 CMS HCAL front-end crate . . . . . . . . . . . . . . . . . . . . . . . . 222.3.3 The communication system between ngFEC (Back-end) and ngCCM

(Front-end) using the GBT protocol . . . . . . . . . . . . . . . . . . . 24

The first part of this chapter gives information about the technical fundamentals of particlephysics and the Large Hadron Collider (LHC). The second part of the chapter describes theCompact Muon Solenoid (CMS) experiment and the front-end and back-end electronics. Theseconcepts are essential for the context of the subsequent chapters.

2.1 The Large Hadron Collider

Accelerators [8] were first invented in the 1930s to study the structure of the atomic nucleus.Since then, they have been used to study numerous aspects of particle physics. There are twotypes of particle accelerators, a circular accelerator where the particles travel multiple timesaround a ring and, a linear accelerator where the particles travel in a straight line from one endto the other.A particle accelerator [9] uses electric fields to speed up and increase the energy of a beam

of charged particles. Magnetic fields are used to steer and focus the beams. Dipole magnets areused to bend the beam around curves in the ring and quadrupole magnets are used to focusthe beam. A tight beam is ensured due to the small quadrupole magnets. The charged particlesdo not travel in a continuous stream, but in closely spaced bunches which are generated andaccelerated by alternating positive and negatively charged electric fields along the accelerator.

7

2 Experimental Setup at LHC

Metallic chambers spaced at intervals along the accelerator resonate at a particular frequencyto allow the beam bunches to absorb energy as they pass through the electric field in the cavity.The worlds biggest and most powerful particle accelerator, the LHC [1012] is located on the

border between France and Switzerland on the outskirts of Geneva, at CERN, the EuropeanOrganization for Nuclear Research in Europe. The LHC, a two-ring-superconducting-hadronaccelerator and collider is mounted in the 26.7 km circular tunnel which is 100 meters belowground, partly under the Jura Mountains. The tunnel has eight straight sections and eight arcs,and lies on a plane inclined at 1.4% sloping towards the Leman lake. The tunnel was originallybuilt for the Large Electron-Positron Collider (LEP), which was operated until year 2000.

Table 2.1: LHC proton-proton collisions showing year of operation, injection energy and center-of-mass energy [13].

s is the kinetic energy, where the mass of two protons are

summed.

Years of the LHC operation type of a collision energy per beams

2009 proton-proton 0.45TeV 0.9TeV2010-2011 proton-proton 3.5TeV 7TeV

2012 proton-proton 4TeV 8TeV2015 proton-proton 6.5TeV 13TeV

The LHC is designed to collide two counter rotating beams of protons or heavy ions, withcenter of mass collision energies of up to 14TeV1 for protons. The LHC started on September10, 2008 and remains to be the latest addition to CERNs accelerator complex (cf. Fig. 2.1).The first collisions of protons occurred on the 23rd November 2009 with a center-of-mass energyof 900GeV. Between 2010 and 2011 the center-of-mass energy increased to 7TeV, and in 2012the pp collision beam was running with a center-of-mass energy of 8TeV. At the beginning of2013 the LHC collided protons with lead (Pb) ions before going into a long maintenance perioduntil the end of 2014. In 2015 the energy had increased to 6.5TeV per proton with increasedluminosity. The center-of-mass energy was now 13TeV. A center-of-mass energy very close to14TeV will be reached between 2015 and 2018 (cf. Table 2.1).An accelerator complex [9, 10, 1619] consists of a chain of accelerator machines as shown in

Fig. 2.1. Each machine accelerates the particles to increase their energy before being injectedinto the next machine in the sequence to further accelerate the particles. A bottle of hydrogengas is used as the proton source. First, the hydrogen nuclei (consisting of one proton and oneelectron) are stripped of their electrons by an electric field, leaving just the protons. The protonsare fed into the particle accelerator machine chain, the first being the linear accelerator LINAC2,which accelerates them to an energy of 50MeV. The beam of protons are then sent to the PSB,which is made up of four superimposed rings, where the protons are accelerated to 1.4GeV.From there the beam is injected into the PS and boosted to 25GeV. The PS also acceleratesheavy ions received by the Low Energy Ion Ring (LEIR). In the final step, before the protonsare injected into the LHC, they enter the SPS, the second largest-machine at CERN and thelast pre-accelerator in the accelerator chain complex, which pushes the beam to 450GeV. The

1Power unit is defined as the energy gained by a particle with the electrical charge of an electron, when it isaccelerated in the vacuum over a voltage of 1 volt. An electron volt (1 eV) [14] corresponds to 1.60221019J.The particle physics take advantage of the natural unit system, where c = 1, thus the mass has the samedimensions with the energy.

8

2.1 The Large Hadron Collider

Fig. 2.1: The CERN accelerator complex showing the pre-accelerators, accelerators and mainexperiments. The protons pass through the pre-accelerators before being injected intothe LHC. The pre-accelerators proceed in the order: the LINAC2, the Proton Syn-chrotron Booster (PSB), the Proton Synchrotron (PS) and finally the Super ProtonSynchrotron (SPS) [15].

protons are transferred to the clockwise and anticlockwise beam pipes of the LHC, which takes4 minutes and 20 seconds. The total injection time is about 20 minutes. The total energy perbeam is now equal to 6.5TeV. The PS as well as the SPS also provide protons for fixed targetexperiments like test beams, as used later in this thesis. Each beam contains bunches of hadrons.There are 2808 bunches inside each beam with 1.15 1011 protons, which pass by every 25 ns. Itcan produce on average 20 collisions per bunch crossing and 800 million collisions per second.There are four main interaction points in the LHC ring where the following experiments are

installed: the Compact Muon Solenoid (CMS), A Toroidal LHC Apparatus (ATLAS), a largeIon Collider Experiment (ALICE) and LHC beauty (LHCb), which are shown in Fig. 2.1 . Thereare also three small special-purpose experiments: LHC forward (LHCf), the Monopole & ExoticsDetector at the LHC (MoDEAL) and the Total Elastic and Diffractive Cross-Section Measure-ment (TOTEM). The ATLAS and the CMS experiments are general-purpose experiments withdifferent technical solutions and magnet-system designs. Both experiments have wide physicsprograms ranging from studying the Standard Model to searching for dark matter and otherphysics beyond the Standard Model.

9


2.2 The Compact Muon Solenoid Experiment

The CMS [20,21] is one of the two multi-purpose detectors at the LHC and is the second largestinternational scientific collaboration, currently involving 4300 particle physicists, engineers, tech-nicians, students and support staff from 182 institutes in 42 countries. The experiment is builtto measure the Higgs boson, electroweak symmetry breaking and possible new physics. Newphysics can be found by discovering new particles or considering deviations from the StandardModel. The detector is designed to identify photons, electrons and muons with a high momen-tum resolution. The CMS detector consists of a huge solenoid magnet with cylindrical coils of

Fig. 2.2: Schematic view of the CMS detector with the geometric and subsection components.Looking from the outside of the CMS to the central interaction point we have: the muonsystem, the hadron calorimeter, the electronic calorimeter, the silicon strip tracker andpixel tracker [22].

superconducting cable, which generate a magnetic field of 4 Tesla, equivalent to 100,000 timesthe earths magnetic field. It is 21m long, 15m wide and 15m high. Unlike the other detectorsin the LHC experiment which were built in-situ, the CMS was constructed at ground level in15 sections and lowered in parts into the underground complex at a point near Cessy in Franceand then assembled.Colliding beam detectors at high-energy physics experiments such as the CMS have an onion-

like structure with each layer consisting of a sub-detector as can be seen in Figure 2.2. The CMSsubdetectors are designed to measure the various type of characteristics of the particles createdin hadron collisions. The geometric information of the subcomponents of the CMS detector islisted in Table 2.2.The Cartesian coordinate system of the CMS has its origin at the Interaction Point: The x

axis points to the center of the LHC ring, the y axis points perpendicularly upwards to the

10


LHC plane and the z axis points to the direction of the anti-clockwise beam. The correspondingcylindrical coordinates are defined by the azimuthal angle and the polar angle. The azimuthalangle is measured in the xy plane beginning from x, whereas the polar angle is measuredin the rz plane beginning from z. In high energy physics instead of angle , [23, 24] is used,which is called pseudorapidity. The function of the production angle with respect to a beamaxis is defined as:

= log(

tan

2

)(2.1)

Table 2.2: Geometric information of the Compact Muon Solenoid (CMS) components and theirpurposes. Modified from [24].

CMS Parts Coverage Purposecopmonents in

Superconducting Solenoid 4 layers - Bending of chargedMagnet particle trajectories

inner Tracker pixel < 2.5 Measurement ofstrip < 2.5 charge and momentum

ECAL barrel < 1.479 Energy measurementendcap 1.479 - 3.0 of electrons and photons

preshower 1.653 - 2.6

HCAL barrel < 1.4 energy measurements ofendcap 1.3 - 3.0 hadronsforward up to = 5.0outer < 1.3

Muon System barrel < 1.2 Identification andendcap 0.9 - 2.4 measurement of muons

11


2.2.1 Superconducting Solenoid

The charged particles which emerge from the collision are affected by the strong magnetic fieldof the solenoid magnet, which bends them in a helical. The coil which is surrounded by themuon system with its iron yoke returns the magnetic flux. The tracker is located inside the coil.

2.2.2 Inner Tracking System

The innermost sub-detector of the CMS is designed to reconstruct precisely the trajectories ofthe charged particles. The reconstruction of charge, momentum and position of the particles canbe made by measuring the tracks of the charged particles. The inner tracking system consists of

Fig. 2.3: Sectional view of the CMS inner tracking system [25]. The lines represent the detectormodules and the pixel and silicon strip tracker.

a pixel and a silicon strip tracker which has the form of a barrel with two end caps. The layoutof the inner tracking system is described in Fig. 2.3. The pixel detectors are the nearest to theinteraction point where the particle flux is strongest. The silicon micro strip detectors are placedaround the pixel tracker. The various parts of the silicon strip tracker are listed as: Tracker InnerBarrel and Disc (TIB, TID), and Tracker Outer Barrel and End Cap (TOB, TEC).

2.2.3 Calorimeters

Calorimeters are detectors which measure the energy deposit of particles passing through them.The interaction starts a particle shower. The energy of the initial particle is then reconstructedfollowing the collection and measurement of the energy deposited by the shower[].The CMS hastwo calorimeter detectors, the electromagnetic calorimeter (ECAL) and the hadronic calorimeter(HCAL).

Electronic calorimeter

The main function of the CMS electronic calorimeter (ECAL) is to measure the energy depositof electrons and photons. The electronic calorimeter has three subcomponents: the ElectronicBarrel (EB), the Electronic Endcap (EE) and the Preshower (ES) detector. The EB consists of61,200 lead tungstate (PbWO4) crystals and the EE consists of 7324 crystals. The high density

12


Fig. 2.4: Layout of the ECAL [26] with its geometric information. Dashed lines demonstrate thepseudorapidity coverage of the calorimeter detectors.

crystals allow the calorimeter to be fast, radiation resistant and to have a fine granularity.Avalanche phototriodes (APDs) in the EB and vacuum phototriodes (VPTs) in the EE are usedto convert the scintillation light into electronic signals.

Hadronic calorimeter

The main function of the CMS (hadronic calorimeter) HCAL is to measure the energy depositof charged and neutral hadrons. The sampling calorimeter HCAL surrounds the ECAL. Thehadronic calorimeter consists of four subcomponents: the Hadronic Barrel (HB), the HadronicEndcap (HE), the Hadronic Outer (HO) and the Hadronic Forward (HF), which are shownin Fig. 2.5. The HB and HE are both sampling calorimeters including the brass absorber andscintillator tiles. They share the || range between 1.3 and 1.4. The scintillation light goesthrough wavelength shifting fibers (WLS) into the tiles and then reaches the hybrid photodiodes(HPD) as photo-detectors operating in high axial magnet fields.The tail catcher, the so called HO is the one HCAL subcalorimeter, placed outside the solenoid

magnet. The subcalorimeter is made of plastic scintillator and uses HPD readout, and coilabsorber.The HF is in the forward section of the HCAL and is made of two cylindrical steel structures

with an outer radius of 130.0 cm, which are located with the front face at 11.20m from theinteraction point. A 12.50 cm cylindrical hole is left free at the inner radius for the beam pipe.To operate in radiation harsh conditions, HF uses a Cherenkov-based, radiation-hardened tech-nology. As an active medium, quartz fibers(fused-silica core and polymer hard-cladding) werechosen because they can operate successfully in harsh A radiation environment. The collectedlight is converted into electrical signals via Photomultiplier tubes (PMT).

2.2.4 Muon Systems

The detection of muons is a fundamental tool to recognize interesting processes in a very highenergy collisions. The central role was decided from its earliest design objective and thereforemuon is chosen as THE middle name for CMS. The muon system has three functions:

13


Fig. 2.5: A schematic r-z, quarter slice (longitudinal slice) view of the CMS HCAL [27]. Thelocations of the HO, HF and the Front End Electronics (FEE) HB and HE are visible.

muon identification

momentum measurement

triggering

The three functions are enabled by the high-field solenoid magnet and its flux-return yoke.

2.2.5 Trigger and Data Acquisition systems

The proton-proton and heavy ions collisions at the LHC happen at a rate of 40 MHz, whichmeans every 25 ns a proton bunch crossing occurs. The collisions per proton bunch crossingresult in a data size of one Mbyte, which is handled by the CMS read-out system. A triggersystem is used for the selection of interesting data events, since it is not possible to store andprocess massive amounts of the data for analysis. The event rate is reduced in two steps calledthe Level-1 Trigger (L1T) with a maximum output rate of around 100 kHz and the High-LevelTrigger (HLT) with an output of around 400 Hz to the storage system. The L1T is based oncustom electronics whereas the HLT is based on commercial processors.The L1 Trigger uses coarsely segmented data from the calorimeters and the muon system,

while holding the high-resolution data in pipelined memories in the front-end electronics[]. L1Thardware is implemented in FPGA for flexibility, whereas Application-Specific Integrated Cir-cuits (ASIC) and Look-Up Tables (LUT) are used for requirements of speed, density and radi-ation tolerance.

2.2.6 Particle Identification at CMS

The particles emerging from a collision from an interaction point will decay further and finallyinteract with the sub-detectors of CMS. The sub-detectors described in the previous chapter

14

2.3 The CMS Hadron Calorimeter Readout Control System

distinguish the signatures of the different types of the particles, as illustrated in Fig. 2.6. Photonsmainly cause electromagnetic showers in the ECAL. On the basis of the calorimeters high depth,the photon energy is deposited in the ECAL and distributed over a few crystals. Electrons leavemost of their energy in the ECAL by electromagnetic showers. Relating to their electric charge,they induce hits in the inner tracker via ionization of the silicon. Muons are heavier than theelectrons and lose their energy by ionization. Due to the relevant energy in the CMS detector,there is minimum ionization and therefore the muon energy traverses the CMS losing a littleenergy. Hits are placed in the inner tracking and muon system. As muons, the hadrons loseenergy by ionization and interaction with the detectors. The hits occur in the inner trackersystem and a hadronic shower occurs, mostly in the HCAL, because of its larger interactionlength, whereas the neutral hadron produces only hadronic showers.

Fig. 2.6: Cross-section of the CMS showing the traces of the different particles traversing thedetector. Taken from [28]


The CMS apparatus operates under a harsh radiation environment and in a strong magneticfield. These conditions make it impossible to gain access to the CMS electronics while it isoperating. Moreover, opening the detector for an intervention requires a considerable effort andtime. Therefore, a reliable remote control and diagnosis system is required. The CMS back-endelectronics, which are located in the radiation protected area, use the Micro Telecommunica-tions Computing Architecture (TCA) [30] crate as an HCAL readout electronic control system.The ngFEC TCA crate [29] connects and organizes the control path between the CMS HCALngFEC control system and front-end readout modules (placed close to the detector). The cratessignificant task is to distribute the 40.0788MHz LHC clock signal to the front-end readout sys-tem.

The ngFEC TCA crate is comprised of the following components:

Twelve FPGA Mezzanine Card (FMC) Carrier (FC7) boards

15


ngFEC

Back-end

ngFE

Front-end

CCM Servergbt_ngCCM

PRBS generator

PRBS RX Checker

FC7

TTC AMC13

ngCCM

TxWord(Header, Slow

Fast Control&FEC)

RxWord(Header,Slow,

Fast Control&FEC)

UDP packets read / write

120- Bit

control system via

IPbus interface 4.8 Gbps

bidirectional optical control link QIE Bridge FPGA

LHC clock & fast control signals

recovery

120-Bit

LHC clock & fast control distributed through the backplane

LHC clock (40 MHz) generator

LHC clock & fast control BC0 and QIE reset

distribution

UDP packets read / write

slow control FPGAFPGA

Fig. 2.7: Detailed general layout of the CMS HCAL ngFEC system control path communication;the dotted lines indicates serial communications via single-mode fiber optic cable at afrequency of 40 MHz. Modified from [29].

An Advanced Mezzanine Card (AMC13XG) board [31]

TCA hub carrier (MCH) [32]

Two redundant power modules

Cooling units

The crate control (CCM) server forms the slow control signals and transmits them as UDPpackets to the FC7 boards via an Ethernet connection based on the IPBus protocol through theMCH. The TTC signals (fast control signals and the LHC clock signal) are distributed from theTCDS to the FC7 through the backplane by the AMC13XG board. Communication betweenthe FC7 and ngCCM is established via a CERN-developed gigabit transceiver (GBT) protocolusing optical fibers to transmit slow and fast control signals, as well as the LHC clock signal.These signals are stored in dual-port block RAMs in the Kintex R-7 (XC7K420T) FPGA [6] onthe FC7 board. Afterwards, the data is read, analyzed and sent to the database by the CCMserver. The communication between the back-end and front-end is illustrated in Fig. 2.7.

2.3.1 CMS HCAL back-end TCA crate

TCA stands for Micro Telecommunications Computing Architecture, which is a telecom-oriented open standard of the PCI Industrial Computer Manufacturers Group (PICMG). Itis designed for carrier-based next generation high performance telecommunication infrastruc-ture and computer systems in a small form factor such as the Advanced Mezzanine Card (AMC)modules and the TCA Control Hubs (MCH). AMC module is for the IO-functionality and theprocessing, while the MCH is for the power management, cooling and the diagnostic controlsystem of AMCs. TCA crates use a network topology called dual star, which allows the MCH

16


Cooling Units

EMMC

Power Modules

EMMC

Backplane

MCMC MMC MMC

AMC1 AMCn(max. 12)MCHs

interconnectionsFig. 2.8: A block diagram of the TCA system. Modified from [33].

to communicate with each AMC. The MicroTCA Carrier Management Controller (MCMC)placed on the MCH, communicates with the Module Management Controls (MMCs) on theAMCs and enhanced MMCs on power modules and cooling modules, via Intelligent PlatformManagement (IPMI) (cf. Fig. 2.8). An overview of the CMS ngFEC TCA is shown in Fig. 2.9.Due to features like a better power and cooling management, small form factor, hot swappingand faster backplane communications, the CMS back-end electronics infrastructure uses theMTCA.O standard.

The CMS ngFEC TCA features:

The crate can accommodate up to twelve AMCs. Due to its dual star topology, the twohubs in the center are connected to the other modules through the backplane. One ofthe hubs is placed next to the AMC13XG module, which recovers the LHC clock and thefast controls, and distributes them through the backplane of the crate. The second hub isplaced next to the MCH, which provides the management and communication with theCCM server by providing gigabit Ethernet connectivity to each AMC.

Continuous operation of the crate is guaranteed, even when AMCs are replaced, removedor inserted (hot swapping)

If a sudden temperature variation occurs while the crate is in operation the custom-developed crate control system adjusts fan rotation speed levels automatically. An electri-cal disturbance will cause the crate to switch itself off.

CCM Server

The CCM Server is a low level control software connected directly to the ngFEC TCA crate,diagnostic databases and the high-level Data Acquisition (DAQ). The CCM Server holds theconfiguration parameters and can enable the front-end modules. It reads the sensor information

17


PSU

PSU

AMC

MCH

CCMServer

ngFEC TCA crate

FC7

TTC

Fig. 2.9: CMS next generation Front-end Controller (ngFEC) Micro Telecommunications Com-puting Architecture(TCA) including the back-electronics

such as temperature and voltage, and counter information such as the PRBS error counters. Italso provides write commands, which for example, reset the counters, such as the PRBS errorcounter.

TCDS and TTC

The timing-trigger control (TTC) signal comprises the LHC clock (40.0788 MHz), CMS triggerprimitives, readout electronics reset, error counter information, and the bunch crossing infor-mation (the first bunch of beam orbit indicator BC0 with a bunch space of 25ns), which areimportant when reconstructing information into physics information. The TTC signals are de-livered by the trigger (timing) control distribution system (TCDS) to the AMC13XG board.

AMC13XG

AMC13XG is a small form factor AMC board, which is plugged into the second MCH housingin the TCA crate. It recovers the LHC clock and the fast controls from the SFP+ connectorand distributes them through the backplane to the FC7.

ngFEC

The FC7 [34] board, which is called ngFEC [35], is an FMC carrier AMC board powered bya Kintex R-7 FPGA and carries two Faster Technologys (FT) S14 FPGA Mezzanine Carrier(FMC) [36] Quad-SFP boards. Each FT S14 FMC has 4 SFP+ links with a transfer speed of upto 10 Gbps, but only three are used. By using two of such FMCs, 6 SFP+ links are controlled,which means that a single FC7 board can control six front-end crates (ngCCM boards) via thesingle-mode fiber cables. The board is used to distribute the LHC clock, reset signals, powerenable, fast and slow controls to the front-end crate and collects temperature, voltage levels,current, error and diagnostic information such as power enable from the front-end crate.

18


The FC7 board is designed with a Kintex R-7 because the FPGA provides an ideal balanceof performance of the FPGA clock rate, low power consumption, high-speed I/O, capacity, se-curity and reliability. Due to these features the FPGA is suitable for a variety of testing andperformance of embedded applications such as in custom triggering, hardware clocked test se-quencing, controlling and monitoring in high-energy physics. It is also optimized for the bestprice-performance compared to previous generations of FPGAs. Due to its digital signal pro-cessor (DSP) power, it is widely used in next-generation communication applications [37].

ngFEC firmware

The FC7 top logic of the ngFEC firmware is designed in two main logic parts: the system logicand the ngFEC logic as shown in Fig. 2.10. The system logic core provides the basic functionalityto the FC7 board. It provides the logic for the Ethernet communication, an IPBUS protocolincluding the User Datagram Protocol (UDP), between the server computers and ngFEC, andinter-integrated circuit (I2C) master/slave communication model for the various sensors placedon the board. A -controller logic over SPI to communicate with the Micro TelecommunicationsComputing Architecture (TCA) and clock distribution CDCE modules are also provided. ThengFEC logic, on the other hand, handles communication with the CCM Server and the front-endelectronics. The ngFEC module is a bridge between the I2C bus and the server, which storesthe commands and front-end, and decodes them according to the IPBus protocol. The Trigger,Timing and Control (TTC) decoder deserializes the clock and control signals. The GBT-ngCCMcode handles the data transfer to and from the ngCCM platform. This code includes output pinsfrom the received and input pins from the transmitted GBT Word. The GBT bank implementsa logic which is for receiving and transmitting the GBT word via enhanced small form-factorpluggable (SFP+) connectors through fiber links between the ngFEC and ngCCM.The implementation of the BERT module (PRBS generator and the error counter) is included

in the ngFEC logic. The two main parts with the PRBS generator and the error counter is shownin Fig. 2.10. The implementation of the ngFEC logic is discussed in more detail in the following.

TTC - ngFEC communication:The LHC clock and fast control signals from the TCDS are sent to the AMC13XG, wherethe fast control signals are serialized and sent with the LHC clock through the TCAbackplane to the FC7. The signals are then deserialized by the TTC decoder logic, whichis designed in the ngFEC logic. The FCLK pin is used to distribute the clock via theAMC13XG board to TCA backplane. Fast control signals are distributed from the dif-ferential pins on the backplane at double data rate.

CCM Server - ngFEC communication:The gigabit Ethernet connection between the server and the AMC boards is establishedthrough the MCH and the backplane. The recovered IPBus UDP packets are stored in theblock RAM buffers and processed by the ngFEC logic.

ngFEC - ngCCM communication:The communication between the ngFEC and the front-end module ngCCM is establishedvia the GBT protocol. The GBTx is a radiation tolerant chip designed by CERN, whichcan be used for the high-energy physics experiments and provides communication speedsof up to 10 Gbps. The GBT is a serial protocol used for multipurpose high-speed (4.8Gbps) communication via optical links between the FC7 and the ngCCM. A 120-bit GBT

19


frame is transmitted and received at the LHC clock frequency. The GBT frame encodingscheme consists of a 4-bit header, 84-bit data (4-bit slow control, 80-bit LHC, slow and fastsignals) and 32-bit Reed Solomon (RS) forward error correction (FEC). The 4-bit headeris to align the data and to indicate whether the controller is in data or idle status. The 32-bit RS FEC is to ensure reliable communication between the FC7 and ngCCM path. Thisalgorithm can correct up to 16 error bits, which can occur under the extreme conditionsin the CMS detector, such as electrical induction and particle interference. In addition tothe RS FEC, an N-bit one-to-many PRBS is included in the 84-bit data payload, whichis used to detect the errors that cannot be corrected by the RS FEC algorithm.

The ngFEC firmware, which is developed with Xilinx ISE software, is designed with two differentlow level hardware description languages. The main modules are developed in VHDL and insome cases Verilog is used, according to the developers preference.

20


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21


2.3.2 CMS HCAL front-end crate

The front-end (FE) crates including the electronics, readout modules and the next generationcrate control modules (ngCCMs) are placed close to the CMS detector. The crate and theelectronics must be able to operate in a harsh radiation environment and therefore the modulesare radiation-hard or tolerant. Instead of SRAM based FPGAs, flash based FPGAs are used inthe front-end crate. Unlike the SRAM based FPGAs, flash based FPGAs are non-volatile andretain their configuration data during irradiation [38] or if the power is switched off, therefore,flash based FPGAs dont require an additional non-volatile memory to reload the configurationdata and they also consume less power.

CMS HCAL FE Readout modules

The readout modules are comprised of Charge Integrator and Encoder (QIE10) applicationspecific integrated circuits (ASICs), which sum and convert analog signals into digital signalscollected by Hybrid Photo Diodes (HPD) with Silicon Photo Multipliers (SIMPs) or PhotoMultiplier Tubes (PMT), depending on the calorimeter. The digital signals are then sent tothe IGLOO R2 FPGA s [39] and are converted into optical signals by the CERN VersaLinkTwin Transmitters (VTTx). The CCM Server controls all the components via one I2C link(ProASIC3L [40] for the HF or ProASIC3 [41] for the HE). The front-end readout electronicsand the data communication path to the back-end electronics are illustrated in Fig. 2.11.

Back-end

Front-end

SIMPsor

PMTQIE FPGA VTTx

AMC13 HTR

Shielding

Light

Data Acquisition Calorimeter Trigger

optic cable

HB/HE uses the SIMPs and HF use the PMTQIE= Charge(Q) Integrator and Encoder, a series of ASICsGBTx= Gigabit Transceiver ASIC developed at CERN, serializes data for transmission to back-end electronics in counting roomVTTx= Versatile Link Dual Transmitter, optical transmitter developed by the CERNSIMPs=Silicon PhotomultipliersPMT= Photomultiplier TubesMicrosemi IGLOO2 FPGA= is the ngCCM synchronizes and formats data from several QIEsHTR=receive data from front-end, compute trigger information, transmit to L1 calorimeter triggerAMC= on L1 accept build events and transmit to DAQgbtx ????

Fig. 2.11: The flow of the CMS HCAL front-end [27] readout system to the back-end electronicsvia the data link, which includes the physics information; the HB/HE use SIPMs andthe HF uses PMT.

ngCCM

The CMS HCAL FE crate control is done by the ngCCM [42]. Each section of the CMS HCALhas its own individual ngCCM board according to its location and subsequent radiation level.The boards are:

HCAL forward (HF) ngCCM board

22


HCAL barrel and endcap (HB and HE) ngCCM boards

The HF ngCCM boards comprise of a ngCCM motherboard and a ngCCM serializer (SerDes)board. The ngCCM SerDes board emulates the GBTx chip and handles the GBT communica-tion. The ngCCM board carries an IGLOO2 FPGA, whose task is to recover the LHC clock, fast,slow and control signals via the GBT protocol implementation. The motherboard distributesthe fast control signals and the LHC clock and routes the slow control signals to the readoutmodules. Temperature and status information is sent via an I2C slave to the CCM server. Thefront-end electronics and their positions in the HCAL are shown in Fig. 2.12.CMS

2

Forward HCal (HF)

HCal Barrel(HB)

HCal Endcap (HE)

Outer HCal

frontend !electronics

Fig. 2.12: A view of the CMS detector showing the positions of the HCAL subcomponents andthe front-end electronics [43].

23


2.3.3 The communication system between ngFEC (Back-end) and ngCCM(Front-end) using the GBT protocol

The ngFEC provides a GBT protocol for the serial communication via the gigabit, bidirectionaloptical link between the ngFEC and the ngCCM. The GBT logic of the ngFEC firmware usesthe GBT encoding scheme described in Fig. 2.14.

Scrambler Gearbox

Encoder

Digital Communication System in the communication between FC7 and ngCCM

GBT bank

GBT Tx

InterleaverReed

SolomonFEC

MGT

MGT Tx

MGT Rx

Descrambler Gearbox

Decoder

GBT Rx

InterleaverReed

SolomonFEC

84

parallel TxData

parallel RxData

84

Tx_serial

1

Rx_serialFrameAligner 1

SERDES

TRANSMITTER

RECEIVER

GBT link N

120

TxFrame

RxFrame

120

3*40

3*40

TxWord

RxWord

88

88

Tx_FRAMECLK_40MHz

Rx_FRAMECLK_40MHz

Tx_WORDCLK_120MHz

Rx_WORDCLK_120MHz

Fig. 2.13: GBT-bank block diagram implemented in the FPGA for the transceiver. The FC7board contains two GBT-bank instances with six GBT links, which controls sixngCCM boards per one GBT-bank. Modified from [5].

4 Bit Header 32 Bit RS FEC84 Bit User data (PRBS ,Slow &Fast control)

120 Bit at LHC clock frequency 40.0788 MHz

Fig. 2.14: The GBT frame (cf. Fig.2.13 the TxFrame and RxFrame). Modified from [5].

The different components of the GBT core are integrated into a single module to facilitate thein-system implementation and the user support of the GBT. This module is called "GBT bank".Each GBT Bank contains 4 "GBT links". The ngFEC firmware uses the "GBT-Frame" encodingscheme due to the forward error detection and it can be used for the entire aforementionedlogical paths which meet the requirements of the CMS-HCALs upgraded back-end electronics.The GBT encoding/decoding process is presented in Fig. 2.13.The GBT link is composed of three components:

The GBT Tx adds a 4-bit header, scrambles the parallel TxData coming from the GBT-ngCCM circuit and encodes the parallel 88-bit by adding the 23-bit RS FEC and inter-leaving.

24


The multi-gigabit Transceiver (MGT) using the Xilinxs gigabit transceivers serializesand de-serializes the data from the GBT-ngCCM.

The GBT Rx aligns, decodes, de-interleaves and descrambles the incoming data.

It is important to have a good DC balance [44] in serial communication systems to preventbit errors occurring. The data over the fiber optic cable is first scrambled before encoding, anddescrambled after decoding to reduce the occurrence of long series of 0s and 1s, which wouldcharge the capacitors in the high pass filters [45].The RS FEC encoding and decoding schemes are used to recover the (burst of errors) lost bit

information, which can be caused by the ionizing radiation. The error correction scheme uses adouble interleaved RS(15,11) and is able to correct up to 16 consecutive erroneous bits in the88 bit data, while only adding 32 forward error correction bits [4, 44].A gearbox [4] is used as a non latency deterministic component in the GBT-Bank core, where

the read and write process is done. The scrambled, encoded data (120-bit) is generated at40 MHz in the TX FRAMECLK domain and then divided into three words of 40 bits whencrossing the TX WORDCLK domain (the MGT TX clock 120 MHz) by the GBT-TX gearbox(cf. Fig. 2.13). In the GBT-RX logic the three words of 40 bits are frame aligned and thengrouped together to 120-bit by the GBT-RX gearbox. The Frame aligner includes the writing(address)process, bit slip counter and barrel shifter. The barrel shifter is used to find the frameboundaries to acquire frame synchronization at power on or loss of synchronization. The serialincoming data is shifted until the frame header aligns with the word clock.

25

3Implementation Concept

3.1 The perspective of the bit error rate testing (BERT) . . . . . . . . . 273.1.1 Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.1.2 Bit Error Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.1.3 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 Proposed BERT for the ngFEC firmware . . . . . . . . . . . . . . . . 323.2.1 Pseudo-random Binary Sequence . . . . . . . . . . . . . . . . . . . . . 343.2.2 Linear Feedback Shift Register . . . . . . . . . . . . . . . . . . . . . . 343.2.3 The tap function, tap positions and initial seed . . . . . . . . . . . . . 373.2.4 Block diagram and VHDL simulation results of the LFSRs . . . . . . 38

Bit Error Rate (BER) [1,4648] is defined as the ratio of the received faulty bits to the totalnumber of transmitted bits in a communication system. The BER technique is a fundamentalmeasurement of the performance, and is a quality of an entire digital communication systemto ensure its reliability bit by bit [46]. There are two types of digital communication systems,serial and parallel. In this thesis, the focus is on the serial digital communication system, whichindicates that the binary digits are transmitted and received bit by bit at every clock cycle.Section 3.1 discusses the perspective of the BER Testing (BERT) in a communication system,

definition of an error, the counting of the bit error rate, and the BERT components. Section 3.2gives the structure of proposed BERT components implementation and the advantages of pre-ferred application.

3.1 The perspective of the bit error rate testing (BERT)

A digital communication system consists of three key components [1]: a transmitter, a communi-cation channel and a receiver as shown in Fig. 3.1. The transmitter modifies the raw informationof an input signal to match the characteristics of the communication channel. Depending on theapplication, a transmitter can be included with a source encoder, an encryptor, and a channelencoder or modulator.The objective of a receiver is to accept the signal from the communication channel and recover

the received signal. Usually the recovered bits are stored in a server, which can be monitoredat will.The communication channel is used to send the signal from the transmitter to the receiver,

which may be by air, wire lines, radio link or fiber optics. These physical mediums are prone to

27

3 Implementation Concept

Transmitter Receiver Communication Channel

Digital Communication System

Transmitted Signal

Received Signal

Server

Output Signal

Input Signal

Fig. 3.1: The key components of a digital communication system (modified from [1]). Thetransmitted and received signals are realized as serial bit streams.

errors, and the communication path can be corrupted by various mechanisms such as electricaldevices, automobile ignition, atmospherics, electrical lightning discharges or radiation.Any component, either the communicating devices or the communication channel, can be

a source of errors or distortion (cf. Fig. 3.1 ). Complex structure of modern communicationinterfaces re prone to device and timing imperfections. Therefore, a measure of accuracy iscrucial in order to ensure reliable operations of these systems. The accuracy and performanceof communication interfaces depend on their design choice, such as the types of waveforms,the signal and the transmission power, the function and characteristics of the channel, and themethod of modulation, demodulation, coding and decoding [1].BER is a fundamental measure of the communication systems performance, whose impor-

tance has been recognized [1]. It is the probability of error occurrence of received output signalcompared to the transmitted input signal.The BER is expressed as 1 in 10n, 110n or 1En. For many systems using fiber optic cables,

the standard maximum bit error rates are specified as 109 or 1012. This indicates that theoccurred errors are counted and presented as ratio such as 1 in 109 or 1012 (1E09 or 1E10),e.g. 1000000000000 bits are received and 1 bit is occurred as an error. BER depends primarilyon the signal to noise ratio (SNR) of the received signal which depends on the transmitted signalpower, the attenuation of the link, the link dispersion and the receiver noise [47].Individual implementation of BER measurement systems may require expensive commercial

equipments. An FPGA based BERT technique reduces cost and time required for BERT andcan be integrated to high-speed and high-capacity complex applications [46]. In comparison tomany other test techniques, BERT has the advantage of testing the entire system includingall the components in an end-to-end system. It detects the origin of the errors either in thecommunication channel or in the communicating devices.

3.1.1 Error

An error [49] in a digital communication system is described in a broad sense as the situationwhere a binary 1 or 0 is transmitted and an exactly the opposite binary is received. Lost bitsare counted as an another error source as well. On the one hand the lost bits have devastating

28


consequences if they are transmitted as a frame or block, and on the other hand it is easier forthe receiver to detect them.There are three types of error that may occur during the transmission [1]:

Single-bit errors,

Error bursts,

Bit slips.

As the name implies, a single-bit error occurs if a binary 1 is transmitted when a binary 0 hasbeen received. Single bit errors can also occur in groups for the given sequence. The errors canbe caused by noise or mismatch in the communication between the transmitter and receiver.They happen sporadically and, therefore, they are also referred to as random errors which makethem a main form of error for the most digital transmission systems.In digital transmission system, fiber optic cable disturbances can cause burst errors. An error

burst can be caused by a poor contact, electromagnetic or radiation inferences that lead to alarge number of single bit errors in very short time of period.The bit slip [1], is the loss or repetition of a bit or bits in a transmission, which is due to the

differing clock rates (speed) of the transmitter and receiver. Loss bits occur when the receiversclock is slower than the transmitters. If the transmitters clock rate exceeds the receivers, itcauses an overflow of a digital received buffer, where the bits are repeated. Such a bit slip resultsin a phase shift between the transmitted and received data. The bit slip detection is covered bythe GBT protocol implementation.Single-bit errors and error bursts should be counted as an error in the BER calculation. Bit

slip errors should be distinguished between the loss and the repeat bits and should countedseparately as errors [50,51].

3.1.2 Bit Error Rate

As the name implies, the Bit Error Rate (BER) is defined as the ratio of received error oc-currences to the total number of transmitted bits in a communication system for a given timeinterval:

BER =

instanceNt

(3.1)

where instance is the number of occurred errors in time t in the transmission, N is the totalnumber of transmitted bits in time t.

3.1.3 Bit Error Rate Test

A Bit Error Rate Test (BERT) is used to measure the performance and the quality of a trans-mitted signal through a single component or an entire system. The concept is to transmitthe predetermined generated stress patterns through the communication channel. The patternconsists of a sequence of logical ones and zeros generated by a pattern generator. Finally thereceived sequence is compared with its input, and differences are registered as errors, evaluatedand counted.It is important to notice that bit error measurements can only be evaluated if the sequence

of the generated pattern which is used for the measurement is completely known [52]. This

29


condition can not be fulfilled due to its random nature in the transmission. Therefore, thereproducible stress pattern with a good randomness properties (which are close to real ran-dom numbers) should be selected. Such conditions are fulfilled by the Pseudo-random binarysequences (PRBS). The reason why PRBS has the best advantages for BER testing and is awell-suited answer of these problems are discussed in Section 3.2.1. In the following, the keycomponents of the BERT, some common types of pattern generators (cf. Table 3.1) and BERtesting schemes are presented.The key components of the BERT and their applications are [50,53]:

A pattern generator to transmit a defined predetermined stress pattern to the testsystem under test.

An error detection module connected to the system under test through a communi-cation channel which compares the received stress pattern with the transmitted one andcounts any errors caused by the system under test.

Table 3.1: Various types of pattern generators with their descriptions [54].

Test pattern generator DescriptionPRBS Generates predetermined(Pseudo-random binary sequence) sequences of ones or zeros of N bits

All zeros Generates only zerocomposed sequences of N bits

Alternating 0s and 1s Generates composedones and zeros of N bits

The key components of a BER can be used alone or in pairs. Common ways to implementthe BERT [50,53]:

A loopback test on one end:Both components of the BERT can be implemented at one end in a communication inan FPGA (cf. Fig. 3.2). A single optic fiber cable plugged from the transmitter to thereceiver side of the transceiver is used for the loopback test. The transmitter side of thetransceiver transmits the test pattern sequence via the optic fiber cable. The receiver sideof the transceiver receives the PRBS via the optic fiber link. The error detection modulecompares the locally generated test pattern sequence with the received pattern and anydifference is counted as an error.

Both components at either ends:Both ends of the communication system have their own pattern generators and can locallygenerate their own stress patterns in the FPGAs (cf. 3.3 ). There are two different waysto realize this implementation with and without synchronization.

In order to synchronize [55] the receivers local pattern generator with the transmitter, thefirst generated stress pattern sent by the transmitter can be used as an initial seed valuefor the receiver. On receiving the first stress pattern correctly, both pattern generators

30


Board

Communication Channel

Detector

Comparator &

Error Counter

Pattern Generator

BERT in a Digital Communication System

Transmitted PatternSequence

Received PatternSequence

Server

FPGA

transceiver

Fig. 3.2: Bit error rate test based on a loopback test. The communication channel uses a bidi-rectional fiber optic cable.

are synchronized. The receiver is able to compare its own locally generated pattern tothe further generated pattern of transmitter for detecting the errors caused by the com-munication channel components. The synchronization is mostly done by handshake basedsynchronization

If the synchronization is not possible due to the different clock regions, which makes theimplementation complicated, a similar implementation principle as we discussed in theprevious paragraph can be implemented. The stress pattern is the initial seed for thereceivers internal pattern generator. The error detection module compares the receivedpattern with the internal test pattern generated next value of the received test pattern.The compared values should be the same, otherwise any difference is detected as an errorand counted. In this thesis, in order to make the circuit simple and compact, this versionof the implementation is employed.

The functionality of the loopback test is to verify the PRBS sequences in a single FPGA whereasthe latter is used for testing the entire system to detect the possible errors in between thecommunicating devices.

31


Board Board

Pattern Generator

BERT in a Digital Communication System

Detector

Comparator &

Error Counter

Pattern Generator

FPGA FPGA

DetectorComparator

& Error Counter

Server

Communication Channel



transceiver



transceiver

Fig. 3.3: Bit error rate test based on both components (Pattern generator and error detectionmodule) at either ends. The communication channel describes a bidirectional fiber opticcable.

3.2 Proposed BERT for the ngFEC firmware

The concept of the BERT in the Kintex R-7 FPGA is represented in Fig. 3.4. The figure shows asingle GBT bank implementation with one GBT link. The transmitter is connected to the PRBSgenerator of the GBT ngCCM logic. The receiver is connected to the error detection module andto the internal PRBS generator of the GBT-ngCCM logic. The GBT-ngCCM logic handles the84-bit data transfer to and from the ngCCM platform I/O via the GBT Bank implementation.Therefore, the implementation of the PRBS generator logic and the PRBS breaking in/outputpins are included to the GBT ngCCM logic. The output pins from the received and input pinsfrom the transmitted 84-bit GBT words are prepared in this implementation and, then, theyare sent via the GBT-bank logic thorough the fiber optics to the ngCCM IGLOO R2 FPGA(cf. Fig. 3.4) and vice versa.

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3.2.1 Pseudo-random Binary Sequence

A pseudo random binary sequence (PRBS) [52,56,57] is an algorithm for generating a sequenceof binary numbers. Pseudo means that the sequence of the binary numbers is deterministic andafter N elements sequence starts to repeat itself from the initial value whereas random meansin this sense that the current value is independent of any values in the sequence, therefore, it isalmost impossible to predict [58].A sequence aj, . . . , aN1 of N bit is called a binary sequence (BS), i.e. aj {0, 1} for j =

0, 1, . . . , N 1 and consists ofm ones and N-m zeros wherem is defined asaj [56].

The PRBS pattern, for testing the robustness of the links, is suggested by the InternationalTelecommunication Union Telecommunication Standardization Sector (ITU-T) Recommenda-tion 0.150. This particular recommendation can be supported by the fact that PRBS is deter-ministic while providing a random sequence. The advantage of using PRBS pattern for BERTis that the sequence of the PRBS pattern is completely known and therefore the pattern arereproducible which is a requirement for the end-to-end error measurements.The PRBS signal is approximated the spectrum of white noise and generates by a deterministic

random generator, which may have the values +1 and -1 and therefore an alternative to thewhite noise [59].

3.2.2 Linear Feedback Shift Register

The PRBS generator is based on a Linear Feedback Shift Register (LFSR) [6064] which is asequential shift register with combinational feedback to its input [] (cf. Fig. 3.5 ). The LFSRstructures are realized by the D-type flip flops (D-ff) and linear logic elements (XOR, XNORgates). Every D-ff in the register chain shares a common clock. In the theory of digital technology,the feedback is formed by the shift input calculated by the sum of selected output bits in modulo2. Practically, the feedback is formed by XORing or XNORing the output bits of the selectedstates of the register chain, and then inputting this to as the least significant bit of the registerchain (D-ff(0)). The selected states are referred to as taps and are chosen based on a primitivepolynomial. The LFSR operates as a shift register, if there is no tap between the states of theregister chain.The LFSR is used for:

Generating random numbers e.g. PRBS in integrated circuits,

Error detection and correction e.g. cyclic redundancy check,

Maximum-length sequence counters,

Data compression techniques,

Data integrity checksums,

Scramble and descramble the data stream in a serial communication system

Cryptology (encryption technology).

The states of the LFSR counter do not sequence in binary order and this characteristic isused as an advantage in the applications. A key application is that the LFSR counter is used asa generator of pseudo-random values to detect errors in communication systems [7, 60].

34


In serial communication systems, the data to be transmitted and received is XORed withthe selected outputs of the LFSR counter, which correspond to the scramble and descrambleprocess in the decoding/encoding. Even if the data contains long series of 0s and 1s, the DCbalance improved and thus the clocking informations can be recovered easily [60].The values of the generated PRBS sequence by an LFSR are determined by the selection of

tap the positions, initial seed value and feedback function (XOR, XNOR). If the LSFR reachesthe maximal length of 2N 1 (where N is number of registers D-ffs), it repeats from the initialstate from the beginning. Different combination of the taps could give the maximal length. Onlya maximum of 2N 1 can be reached because sequence of all 0s with XOR function and 1swith XNOR function causes a deadlock (prohibited) state.An LFSR consists of either XOR or XNOR feedback functions. Both feedback functions with

the selected taps go through the equal number of possible values until they reach the initialvalue, but have different generated PRBS sequences. Figure 3.5 of the PRBS generator, basedon the LFSR implementation, uses the XOR function which can be interchanged with the XNORfeedback functions.

feedback

beispiel

=1

D-ff N-1 D-ff 0D-ff d

Clock

1D 1D 1D 1D

R R R R

1D

R

1D

R

1D

R

1D

R

Reset

Q(N-1:0)Q(N-1) Q(0)

Fig. 3.5: Design circuit of a PRBS generator using LFSR implementation (xN + xd + 1) withthe D-FF chain; N indicates the number of the D-ffs and d indicates the tab whereXOR function takes place.

Due to the linearity of the generated sequences, the quality of the of the PRBS values gener-ated by LFSR is poor and, therefore, feedback in conjunction with non-linear feedback functionis used in the encryption technology. Otherwise the value of the sequences are predictable [7].The advantage of using LFSR for BERT is that the implementation has a simple structure

and a rather complex mathematical theory, hence it requires a simple hardware structure, andis used for high speed operations [65].There are two different design implementations of the LFSR [62,66]:

Many-to-one structure

One-to-many structure

Both structures can be implemented using both the feedback functions and equal number oflogic gates. In the following, the structure of Many-to-one and One-to-many are presented withthe equal number of logic gates and XOR feedback functions.

35


Many-to-one Structure

A Many-to-one shift register circuit combines two or more taps into one feedback to generatethe output sequence. An example of 8-bit LFSR with XOR feedback path is shown in Fig. 3.6.In this example, the taps are defined at bit 1, 2, 3 and 7. The LFSR has a two level (stage) oflogic that consists of three XOR gates.

D-ff 7 D-ff 0D-ff d1

Clock

1D 1D 1D 1D

R R R R

1D

R

1D

R

1D

R

1D

R

Reset

=1=1 =1

D-ff d2D-ff d3

Q(7) Q(0)Q(1)Q(2)Q(3)Q(4)Q(5)Q(6)Q(7:0)

Fig. 3.6: Design of an 8-bit Many-to-one shift register implementation (xN+xd+1)

One-to-many Structure

A One-to-many shift register uses only one feedback value with all the taps to generate theoutput sequence. An example of 8-bit LFSR with XOR feedback path is shown in Fig. 3.7. Inthis example, the taps are defined equal to the Many-to-one implementation. In contrast toMany-to-one implementation the feedback is realized within one logic level.

D-ff N-1 D-ff 0D-ff d1

Clock

1D 1D 1D 1D

R R R R

1D

R

1D

R

1D

R

1D

R

Reset

D-ff d2D-ff d3

=1 =1 =1

Q(7) Q(0)Q(1)Q(2)Q(3)Q(4)Q(5)Q(6)Q(7:0)

Fig. 3.7: Design of the 8-bit One-to-many shift register implementation (xN+xd+1)

The problem encountered in the Many-to-one implementation is that, with increasing thenumber of taps, the level of logics also increase which negatively affects the timing of the

36


implementation. The One-to-many implementation is the fastest because there is only one gatebetween each state in the combinational feedback path. Therefore, the timing depends on thepropagation through one gate. For this reason, in the present project, One-to-many structurefor generating the PRBS pattern is preferred and implemented.

3.2.3 The tap function, tap positions and initial seed

A number of tap combinations can be used for generating the maximal length of the LFSRsequences, and inappropriately chosen taps can cause a limited number of unique output se-quences. In finite field theory, the maximal length PRBS output is guaranteed by selecting aprimitive polynomial of degree N over Galois Field of two elements (GF(2)) [57,67]. The lengthof maximum period is defined as 2N 1. Every degree N has many primitive polynomials. Oneamong many primitive polynomials, which includes the minimum number of feedback logic,should be selected. These are referred to as trinomials and has the form:

xN + xd + 1, (3.2)

where d < N.The form of binary primitive k-nomial (k-term), where k {3, 5, 7}, polynomial of degree N

is as follows:xN +

xd + 1 (3.3)

where d takes the values from the k-nomial entries depended on their lengthN . A list of primitivek-nomials can be found in Ref. [68].In order to obtain a robust and modular design, a generic N-bit PRBS pattern can be gener-

ated using trinomial (2-tap version) and k-nomial (5-tap version) primitive polynomials. Thereare two ways of achieving this, the best way is to define a generic model in the entity of theVHDL model and the other way is to define a generic VHDL procedure in a separate package [62].In this thesis, both ways are preferred and implemented (cf. Chapter 4)1. This redundancy isimplemented to show that both versions can be employed in a BERT. The 2-tap version is usedin the standard communication which can be easily computed where the 5-tap version is usedfor cryptological applications [69].The following tables list the polynomials for the maximal length of the LFSR. Table 3.2 shows

a two feedback function (XNOR, XOR) and two tap version LFSR design whereas Table 3.3shows a one feedback function (XOR) and five tap version LFSR design. Table 3.2 is based ontrinomial primitive binary polynomials obtained from [52,57]:The inverter functionality is used to invert the output (if INV is true), which indicates that

XNOR, instead of XOR is used. Table 3.3 is based on a k-nomial primitive binary polynomi-als [68].The differences are demonstrated with the circuit diagrams (cf. Fig. 3.8, 3.9, 3.12 and 3.13)

and the VHDL functional simulations (cf. Fig. 3.10, 3.11 and 3.14).

1The experience of implementing the VHDL procedure with a separate package and functions is obtained withinthe thesis work by Author.

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Table 3.2: HF LFSR functions for the N-bit PRBS generator with the maximum length; if invis false, the initial seed is all 1s and XOR is used as tap function. If inv is true, theinitial seed is all 0s and XNOR is used as a tap function.

LSFR Polynomial Binary polynomial PRBS INV Referencelength with taps cycle StandardN length3 x3 + x2+1 110 23-1 true4 x4 + x3+1 1100 24-1 false For debugging7 x7 + x6+1 1100000 27-1 true Not Standard9 x9 + x5+1 100010000 29-1 false ITU-T O.15011 x11 + x9 + 1 10100000000 211-1 false ITU-T 0.15015 x15 + x14+1 110000000000000 215-1 true ITU-T 0.15017 x17 + x14+1 1010000000000000 217-1 false OIF-CEI-P-02.020 x20 + x3 + 1 10000000000000000100 220-1 false ITU-T 0.15023 x23 + x18+1 10000100000000000000000 223-1 true ITU-T 0.15029 x29 + x7+1 10100000000000000000000000000 229-1 true ITU-T 0.15031 x31 + x28+1 1000100000000000000000000000000 231-1 true ITU-T 0.150

OIF-CEI-P-02.0others all 0s to indicate unknown taps 2others-1 false

Table 3.3: HBHE LFSR functions for the N-bit PRBS generator with the maximum length; XORis used as a tap function and initial seed value is the same as the binary polynomialwith taps.

LSFR Polynomial Binary polynomial PRBS INVlength with taps cycleN length3 x3 + x1 + 1 001 23-1 false4 x4 + x1 + 1 0001 24-1 false7 x7 + x5 + x4 + x3 + x2 + x1 + 1 0011111 27-1 false9 x9 + x8 + x7 + x6 + x3 + x2 + 1 011100110 29-1 false11 x11 + x9 + x7 + x5 + x3 + x2 + 1 00101010011 211-1 false15 x15 + x13 + x8 + x7 + x6 + x5 + 1 001000011110000 215-1 false17 x17 + x13 + x8 + x6 + x5 + x2 + 1 00001000010110010 217-1 false20 x20 + x18 + x16 + x14 + x10 + x1 + 1 00101010001000000001 220-1 false23 x23 + x17 + x13 + x12 + x11 + x5 + 1 00000010001110000010000 223-1 false29 x29 + x22 + x16 + x15 + x11 + x3 + 1 00000001000001100010000000100 229-1 false31 x31 + x16 + x14 + x10 + x8 + x1 + 1 0000000000000001010001010000001 231-1 false

others all 1s to indicate unknown taps 2others-1 false

3.2.4 Block diagram and VHDL simulation results of the LFSRs

In the following, the circuit diagrams of the 4-bit and 7-bit PRBS generator for the HF and forthe HB/HE with a maximum length are presented in order to show the two design differences.

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Afterwards, the VHDL functional simulations are demonstrated. A 4-bit LFSR circuit illustrated

D-ff 3 D-ff 0

clk

1D

R

1D

R

1D

R

1D

R

reset

=1

HF

feedback (3)prbs_o (3:0)

feedback (2) feedback (1) feedback (0)

Fig. 3.8: Design of a 4-bit Pseudo-random binary sequence generator with a maximum lengthfor the HF detector readout control system.

D-ff 3 D-ff 0

clk

1D

R

1D

R

1D

R

1D

R

reset

feedback (3)

=1

HBHE

prbs_o (3:0)feedback (2) feedback (1) feedback (0)

Fig. 3.9: Design of a 4-bit Pseudo-random binary sequence generator with a maximum lengthfor the HBHE detector readout control system.

in Fig. 3.8 generates pseudo-random binary sequences using the XOR feedback function of the2nd and 3rd bits (cf. Table 3.2).Figure 3.9 illustrates another 4-bit LFSR circuit to generate pseudo-random binary numbers

via the XOR feedback function of the bits 0 and 3 (cf. Table 3.3). The 4-bit PRBS generatorswere use for debugging at the beginning of the implementation.The simulations presented in Fig. 3.10 and 3.11 show the PRBS pattern sequence consisting

of the maximum number of 15 states until the t = 462.500 ns with a clock frequency of 40MHz.At the beginning, an asynchronous reset is inserted until 87.500 ns. The asynchronous reset isused as a preset, which sets the initial seed. The setup value of the PRBS output bits are setto 0s. A scan of the initial seed value in the sequence is implemented in the test bench in orderto show that the LFSR reaches the maximum length of 2N 1.

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Fig. 3.10: Simulation of the 4-bit Pseudo-random binary sequence generator starting with theinitial seed of "1111"(cf. Table 3.2 and Figure 3.8). At t = 462.500 ns, the counterbegins from the initial value.

Fig. 3.11: Simulation of the 4-bit Pseudo-random binary sequence generator starting with theinitial seed of "0001"(cf. Table 3.2 and Figure 3.8). At t = 462.500 ns, the counterbegins from the initial value.

In the following, two different LFSR circuit with a pseudo-random binary sequence of 27 1are presented. A 7-bit LFSR circuit illustrated in Fig. 3.12 uses XNOR as a feedback functionof the bits 5 and 6 (cf. Table 3.2 above) whereas a 7-bit LFSR circuit illustrated in Fig. 3.13uses XOR feedback function of the bits 1, 2, 3 , 4 and 5 (cf. Table 3.3 above).The functional simulat

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