Bidirectional Asynchronous Generator and Battery Interface ...

Bidirectional Asynchronous Generator and

Battery Interface Circuit

by

Adél Coetzer

Thesis presented in partial fullment of the requirements forthe degree of Master of Engineering (Electrical) in the

Faculty of Engineering at Stellenbosch University

Supervisor: Prof. H.D.T. Mouton

Co-supervisor: Mnr. G.R. Turner

December 2016

Declaration

By submitting this thesis electronically, I declare that the entirety of the workcontained therein is my own, original work, that I am the sole author thereof(save to the extent explicitly otherwise stated), that reproduction and pub-lication thereof by Stellenbosch University will not infringe any third partyrights and that I have not previously in its entirety or in part submitted it forobtaining any qualication.

Date: . . . .December 2016

Copyright © 2016 Stellenbosch UniversityAll rights reserved.

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Stellenbosch University https://scholar.sun.ac.za

Abstract

In some instances additional power is required to support an electrical load onboard an aircraft. A ram air turbine (RAT) generator can be used to supplythe necessary power in conjunction with a storage unit such as a battery orsupercapacitors. The RAT is driven by the airow surrounding the sub-sonicaircraft and acts as the main power supply. The storage unit is charged whenthe RAT is supplying excess power or when the load is disconnected.

This thesis presents the design and implementation of a prototype circuitthat demonstrates the interface between a generator and a battery of elec-trochemical cells to an electrical load. To simulate the airow through theturbine an asynchronous machine is employed to turn the shaft of an asyn-chronous generator. The prototype circuit is designed such that the battery isconnected to a dc bus through a bidirectional dc-dc converter and the asyn-chronous machine interfaces with the dc bus through a bidirectional inverter.The load is connected between the positive and negative dc bus rails.

The dc-dc converter circuit functions to regulate the dc bus voltage byutilising a double control loop strategy with an inner and outer control loop.The inverter functions as a synchronous rectier and the power delivered to thedc bus from the generator is controlled as a function of the converter's batteryvoltage. The simulated and measured test results of the complete system arecompared and presented.

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Opsomming

In sommige gevalle benodig vliegtuie addisionele krag om 'n elektriese las vankrag te voorsien. 'n Klein lugaangedrewe turbine kan gebruik word om dieaddisionele krag te voorsien in samewerking met 'n stooreenheid soos 'n batteryof superkapasitor. Die stooreenheid word herlaai wanneer die lugaangedreweturbine oortollige krag lewer aan die stelsel of wanneer die las ontkoppel word.

Hierdie tesis bespreek die ontwerp en implementering van 'n prototipestroombaan wat die werking tussen 'n generator en battery demonstreer. 'nAsinkroon motor word gebruik om die lugvloei deur die turbine te simuleer endie dryfas van die asinkroon generator aan te dryf. Die battery word gekoppelaan 'n gs bus deur middel van 'n bidireksionele gs-gs omsetter en die generatorword gekoppel aan die gs bus deur middel van 'n bidireksionele ws-gs omsetter.Die las word gekoppel tussen die positiewe en negatiewe gs bus lyne.

Die gs-gs omsetter funksioneer om die gs busspanning te reguleer deurmiddel van 'n dubbelle beheerlus strategie wat bestaan uit 'n binneste enbuitenste beheerlus. Die ws-gs omsetter funksioneer as 'n sinkroon gelykrigterwaar die krag wat aan die gs bus gelewer word, beheer word as 'n funskie vandie gs-gs omsetter se battery spanning. Die gesimuleerde en gemete resultatevir die volledige stelsel word vergelyk en voorgelê.

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Acknowledgements

I would like to express my sincere gratitude to the following people and organ-isations:

My supervisor, Prof H.D.T. Mouton, and my co-supervisor, GeoreyTurner, for their continuous support, advice and guidance throughoutthis project.

The CSIR for providing the required lab facilities and in particular Ge-orey Turner for his assistance in the lab.

Adrian Adams from the CSIR, for allocating the funding required forthis project.

Prof. M.J. Kamper for his guidance on the modelling of induction ma-chines.

Kushal Ramdas from the CSIR, for his assistance with Altium Designer.

Christo Swanepoel for his continuous encouragement, love and supportthroughout the duration of this project.

My family and friends for their love and support.

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Contents

Declaration i

Abstract ii

Opsomming iii

Acknowledgements iv

Contents v

List of Figures ix

List of Tables xiii

Nomenclature xiv

1 Introduction 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Thesis Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Literature Review 5

2.1 Ram Air Turbines as Generators . . . . . . . . . . . . . . . . . . 52.1.1 Energy Management Strategies . . . . . . . . . . . . . . 52.1.2 Existing Power Generation Topologies . . . . . . . . . . 6

2.2 DC-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . 72.2.1 Pulse-Width Modulation . . . . . . . . . . . . . . . . . . 72.2.2 Bidirectional Converter Topology . . . . . . . . . . . . . 9

2.3 DC-AC Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . 102.3.1 Three-Phase Inverters . . . . . . . . . . . . . . . . . . . 102.3.2 Inverter Control Schemes . . . . . . . . . . . . . . . . . . 12

2.4 Asynchronous Machines . . . . . . . . . . . . . . . . . . . . . . 122.4.1 Principle of Operation . . . . . . . . . . . . . . . . . . . 132.4.2 Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . 162.4.3 Dynamic d-q Model . . . . . . . . . . . . . . . . . . . . . 18

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CONTENTS vi

2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 DC-DC Converter Design and Implementation 21

3.1 Basic Circuit Operation . . . . . . . . . . . . . . . . . . . . . . 213.1.1 Inductor Design . . . . . . . . . . . . . . . . . . . . . . . 253.1.2 Bus Capacitor Design . . . . . . . . . . . . . . . . . . . . 273.1.3 MOSFET Power Loss and Heat Sink Design . . . . . . . 293.1.4 Soft-start Circuit . . . . . . . . . . . . . . . . . . . . . . 323.1.5 Isolated Gate-Drive Circuitry . . . . . . . . . . . . . . . 36

3.2 PWM Controller Design . . . . . . . . . . . . . . . . . . . . . . 383.2.1 Carrier Waveform Generation . . . . . . . . . . . . . . . 393.2.2 Controller Plant . . . . . . . . . . . . . . . . . . . . . . . 403.2.3 Current Control Loop . . . . . . . . . . . . . . . . . . . 413.2.4 Current and Voltage Limiting Circuit . . . . . . . . . . . 493.2.5 Voltage Control Loop . . . . . . . . . . . . . . . . . . . . 50

3.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4 DC-DC Converter Simulation and Test Results 56

4.1 Test Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564.2 Start-Up Response . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.2.1 Gating Signal Implementation . . . . . . . . . . . . . . . 604.3 Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.3.1 Inductor Ripple Current . . . . . . . . . . . . . . . . . . 634.3.2 Gating Signals . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4 Eciency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5 Asynchronous Machine Modelling 68

5.1 Machine Parameter Estimation . . . . . . . . . . . . . . . . . . 685.1.1 Stator Resistance . . . . . . . . . . . . . . . . . . . . . . 695.1.2 Leakage Reactance . . . . . . . . . . . . . . . . . . . . . 695.1.3 Rotor Resistance . . . . . . . . . . . . . . . . . . . . . . 715.1.4 Magnetising Reactance . . . . . . . . . . . . . . . . . . . 715.1.5 Core Resistance . . . . . . . . . . . . . . . . . . . . . . . 72

5.2 Machine Characteristics . . . . . . . . . . . . . . . . . . . . . . 725.2.1 Torque-Speed Relationship . . . . . . . . . . . . . . . . . 725.2.2 Current-Speed Relationship . . . . . . . . . . . . . . . . 73

5.3 Dynamic Machine Model . . . . . . . . . . . . . . . . . . . . . . 755.3.1 Modelling Results . . . . . . . . . . . . . . . . . . . . . . 75

5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6 Inverter Design and Implementation 78

6.1 Basic Circuit Operation . . . . . . . . . . . . . . . . . . . . . . 786.1.1 Generator Voltage and Current . . . . . . . . . . . . . . 85


CONTENTS vii

6.1.2 IGBT Power Loss and Heat Sink Design . . . . . . . . . 876.1.3 Over-Temperature Protection . . . . . . . . . . . . . . . 916.1.4 Isolated Gate-Drive Circuitry . . . . . . . . . . . . . . . 936.1.5 Overvoltage Protection . . . . . . . . . . . . . . . . . . . 96

6.2 PWM Controller Design . . . . . . . . . . . . . . . . . . . . . . 976.2.1 Inverter Plant . . . . . . . . . . . . . . . . . . . . . . . . 986.2.2 Digital Signal Processor Interfacing . . . . . . . . . . . . 1016.2.3 Current Control Loop . . . . . . . . . . . . . . . . . . . 1066.2.4 Voltage Control Loop . . . . . . . . . . . . . . . . . . . . 112

6.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

7 Inverter Simulation and System Integration Test Results 118

7.1 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . 1187.1.1 Test Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . 1197.1.2 Start-Up Procedure . . . . . . . . . . . . . . . . . . . . . 119

7.2 PWM Generation and Gate Signals . . . . . . . . . . . . . . . . 1207.2.1 Reference Waveforms . . . . . . . . . . . . . . . . . . . . 1207.2.2 Triangular Carrier Waveform . . . . . . . . . . . . . . . 1237.2.3 Switching Signals . . . . . . . . . . . . . . . . . . . . . . 1237.2.4 IGBT Gate Signal . . . . . . . . . . . . . . . . . . . . . 124

7.3 Current Simulation and Test Results . . . . . . . . . . . . . . . 1257.3.1 Inverter Phase Currents . . . . . . . . . . . . . . . . . . 1257.3.2 Bus Current . . . . . . . . . . . . . . . . . . . . . . . . . 1307.3.3 Battery Current . . . . . . . . . . . . . . . . . . . . . . . 132

7.4 Bus Current and Battery Voltage Relationship . . . . . . . . . . 1337.4.1 Simulated Response . . . . . . . . . . . . . . . . . . . . . 1337.4.2 Measured Response . . . . . . . . . . . . . . . . . . . . . 134

7.5 Safety Features Testing . . . . . . . . . . . . . . . . . . . . . . . 1367.5.1 Over-Temperature Protection . . . . . . . . . . . . . . . 1367.5.2 Overcurrent Protection . . . . . . . . . . . . . . . . . . . 1367.5.3 Overvoltage Protection . . . . . . . . . . . . . . . . . . . 137

7.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8 Conclusions 138

8.1 Thesis Conculsions . . . . . . . . . . . . . . . . . . . . . . . . . 1388.2 Recommendations and Future Work . . . . . . . . . . . . . . . . 139

List of References 141

Appendices 146

A Complete Circuit Schematics 147

A.1 DC-DC Converter Circuit Schematics . . . . . . . . . . . . . . . 147A.1.1 Power Stage Schematics . . . . . . . . . . . . . . . . . . 147


CONTENTS viii

A.1.2 Control Stage Schematics . . . . . . . . . . . . . . . . . 150A.2 Inverter Circuit Schematics . . . . . . . . . . . . . . . . . . . . 152

A.2.1 Power Stage Schematics . . . . . . . . . . . . . . . . . . 152A.2.2 Control Stage Schematics . . . . . . . . . . . . . . . . . 154

B Printed Circuit Boards 157

B.1 DC-DC Converter Printer Circuit Boards . . . . . . . . . . . . . 157B.1.1 Power Stage PCB . . . . . . . . . . . . . . . . . . . . . . 157B.1.2 Controller PCB . . . . . . . . . . . . . . . . . . . . . . . 160

B.2 Inverter Printer Circuit Boards . . . . . . . . . . . . . . . . . . 161B.2.1 Power Stage PCB . . . . . . . . . . . . . . . . . . . . . . 161B.2.2 Controller PCB . . . . . . . . . . . . . . . . . . . . . . . 162


List of Figures

1.1 Block digram of a bidirectional battery and machine interface circuit. 1

2.1 Half-bridge converter circuit. . . . . . . . . . . . . . . . . . . . . . . 82.2 PWM signal (green line) generated using a control signal (red line)

and sawtooth carrier waveform (blue line). . . . . . . . . . . . . . . 82.3 Bidirectional dc-dc converter circuit. . . . . . . . . . . . . . . . . . 92.4 Three-phase voltage source inverter connected to a three-phase load. 102.5 PWM voltages generated in three-phase inverter applications. . . . 112.6 Ideal three-phase, two pole induction machine. . . . . . . . . . . . . 132.7 Single-phase equivalent circuit of an induction motor. . . . . . . . . 172.8 Dynamic d-q model of a squirrel cage induction motor for the (a)

q-axis component and (b) d-axis component. . . . . . . . . . . . . . 19(a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19(b) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1 Bidirectional dc-dc converter circuit. . . . . . . . . . . . . . . . . . 223.2 Current and voltage waveforms describing the operation of the con-

verter when the batteries are being charged at maximum current. . 233.3 Current waveforms describing the operation of the converter when

the batteries are sourcing maximum current. . . . . . . . . . . . . . 253.4 Waveforms indicating the capacitor current and voltage when the

batteries are being charged at the maximum current. . . . . . . . . 283.5 Pre-charge soft-start circuit implementation. . . . . . . . . . . . . . 333.6 Dead-time implementation. . . . . . . . . . . . . . . . . . . . . . . 353.7 Post-charge soft-start circuit implementation. . . . . . . . . . . . . 363.8 Power section of the isolated gate-drive circuit. . . . . . . . . . . . 363.9 Block diagram of the MOSFET gate-drive circuit. . . . . . . . . . . 373.10 Block diagram of converter's control circuit. . . . . . . . . . . . . . 393.11 Circuit outline of the triangular carrier waveform generation. . . . . 403.12 Bidirectional dc-dc converter circuit used for controller design. . . . 413.13 Current control loop block diagram. . . . . . . . . . . . . . . . . . . 423.14 Inductor current sensing circuit. . . . . . . . . . . . . . . . . . . . . 433.15 Bode plot of current controller without compensation. . . . . . . . . 443.16 Pole-zero compensation amplier. . . . . . . . . . . . . . . . . . . . 45

ix


LIST OF FIGURES x

3.17 Current controller bode plot. . . . . . . . . . . . . . . . . . . . . . . 483.18 Current control loop with additional gain factor KB. . . . . . . . . 483.19 Bifurcation diagram used for stability analysis. . . . . . . . . . . . . 493.20 Postive and negative active clamping circuit. . . . . . . . . . . . . . 493.21 Voltage and current control loop block diagram. . . . . . . . . . . . 523.22 Simplied voltage and current control loop block diagram. . . . . . 523.23 Reduced voltage and current control loop block diagram. . . . . . . 523.24 Bus voltage feedback circuit. . . . . . . . . . . . . . . . . . . . . . . 533.25 Bode plot of the voltage controller without compensation. . . . . . 533.26 Bode plot of voltage controller under load. . . . . . . . . . . . . . . 55

4.1 Converter prototype circuit test set-up. . . . . . . . . . . . . . . . . 574.2 Simulated dc bus voltage and inductor current during start-up. . . 584.3 Measured dc bus voltage and inductor current during start-up. . . . 594.4 Measured inductor current during start-up. . . . . . . . . . . . . . . 604.5 Measured oscillator signal used in gate-drive circuitry. . . . . . . . . 604.6 Measured gating signal from the controller and MOSFET gate for

Q2 during start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.7 Simulated step response of dc bus voltage and inductor current. . . 624.8 Measured step response of the dc bus voltage under ac coupling. . . 634.9 Simulated inductor current. . . . . . . . . . . . . . . . . . . . . . . 644.10 Measured inductor current without a load connected. . . . . . . . . 644.11 Measured inductor current with a 2.1 kW load connected to the dc

bus rails. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.12 Measured controller gating signals forQ1 andQ2 under steady-state

no-load conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.13 Measured inductor current and ac coupled battery voltage under

load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1 Per-phase equivalent circuit of an induction machine. . . . . . . . . 685.2 Approximate per-phase equivalent circuit of an induction machine. 705.3 Reduced equivalent circuit of an induction machine under no-load. . 715.4 Torque vs rated speed characteristic curve. . . . . . . . . . . . . . . 735.5 Stator current vs rated speed characteristic curve. . . . . . . . . . . 745.6 Three-phase stator voltages and currents at zero slip. . . . . . . . . 765.7 Stator and rotor currents at -5 % slip. . . . . . . . . . . . . . . . . 76

6.1 Bidirectional converter and inverter interface circuit. . . . . . . . . 796.2 PWM signal generation block diagram. . . . . . . . . . . . . . . . . 806.3 Inverter phase voltage and current for one half-bridge circuit. . . . . 816.4 Switch and diode currents for S1 and S2 over a single angular rotation. 836.5 Instantaneous and average dc bus current. . . . . . . . . . . . . . . 846.6 Instantaneous and fundamental line and phase voltages. . . . . . . 856.7 Instantaneous line current. . . . . . . . . . . . . . . . . . . . . . . . 86


LIST OF FIGURES xi

6.8 Average switching current approximation. . . . . . . . . . . . . . . 896.9 Temperature sensing circuit for the IGBT module. . . . . . . . . . . 916.10 PWM signal and error signal integration. . . . . . . . . . . . . . . . 926.11 Block diagram of the IGBT gate-drive circuit. . . . . . . . . . . . . 946.12 Block diagram of the inverter control circuit. . . . . . . . . . . . . . 976.13 Bidirectional inverter circuit. . . . . . . . . . . . . . . . . . . . . . . 996.14 Phase angle over generator operating frequency range. . . . . . . . 1006.15 Shaft coupling with magnetic pick-up for speed feedback. . . . . . . 1026.16 Magnetic pick-up interfacing with the dsPIC. . . . . . . . . . . . . 1036.17 Three-phase reference waveform generation with the dsPIC. . . . . 1056.18 DC bus current control loop block diagram. . . . . . . . . . . . . . 1066.19 DC bus current sensor feedback circuit. . . . . . . . . . . . . . . . . 1086.20 Bode plot of the open-loop response of the current control loop

without the compensator present. . . . . . . . . . . . . . . . . . . . 1106.21 Active integrator compensation circuit. . . . . . . . . . . . . . . . . 1106.22 Bode plot of the open-loop response of the complete current control

loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1116.23 Tracking back anti-windup scheme with an integral controller. . . . 1126.24 Voltage and current control loop block diagram. . . . . . . . . . . . 1136.25 Battery voltage feedback circuit. . . . . . . . . . . . . . . . . . . . 1146.26 Reduced voltage and current control loop block diagram. . . . . . . 1156.27 Bode plot of the open-loop frequency response of the voltage control

loop without compensation. . . . . . . . . . . . . . . . . . . . . . . 1156.28 Bode plot of the open- and closed-loop frequency response of the

voltage control loop. . . . . . . . . . . . . . . . . . . . . . . . . . . 116

7.1 Test set-up for generator and battery interface circuit. . . . . . . . 1197.2 Measured modulator reference waveforms at an increasing genera-

tor shaft speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217.3 Measured modulator reference waveforms at a shaft frequency of

25 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217.4 Measured modulator reference waveforms at a shaft frequency of

50 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227.5 Measured modulator reference waveforms after the operating shaft

speed range was exceeded. . . . . . . . . . . . . . . . . . . . . . . . 1227.6 Measured triangular carrier waveform. . . . . . . . . . . . . . . . . 1237.7 Measured PWM switching signals for one inverter half-bridge. . . . 1247.8 Measured controller and gate PWM switching signals. . . . . . . . . 1247.9 Simulated inverter phase currents at a 3.3 A dc bus current set-point.1267.10 Measured inverter phase currents at a measured dc bus current of

3.3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267.11 Simulated inverter phase current ripple. . . . . . . . . . . . . . . . 1277.12 Measured inverter phase current ripple. . . . . . . . . . . . . . . . . 128


LIST OF FIGURES xii

7.13 Simulated modulator reference voltage and phase current for oneinverter half-bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

7.14 Measured modulator reference voltage and phase current for oneinverter half-bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

7.15 Measured modulator reference voltage and phase current at a shaftfrequency of 34 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

7.16 Simulated dc bus current during generator start-up. . . . . . . . . . 1307.17 Measured dc bus current at the maximum set-point current. . . . . 1317.18 Measured dc bus current whilst charging the batteries. . . . . . . . 1327.19 Measured battery current whilst charging the batteries. . . . . . . . 1327.20 Simulated mean dc bus current and battery voltage. . . . . . . . . . 1347.21 Measured mean dc bus current vs battery voltage. . . . . . . . . . . 135

A.1 Schematic for the top-half of the dc-dc converter circuit. . . . . . . 148A.2 Schematic for the bottom-half of the dc-dc converter circuit. . . . . 149A.3 Control schematic for the dc-dc converter circuit. . . . . . . . . . . 151A.4 Schematic for the power stage of the inverter circuit. . . . . . . . . 153A.5 Schematic for the inverter digital control circuit. . . . . . . . . . . . 155A.6 Schematic for the inverter analog control circuit. . . . . . . . . . . . 156

B.1 PCB for the top-half of the dc-dc converter circuit producing +175 V.158B.2 PCB for the bottom-half of the dc-dc converter circuit producing

-175 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159B.3 Control PCB of the dc-dc converter. . . . . . . . . . . . . . . . . . 160B.4 PCB for the power stage of the inverter circuit. . . . . . . . . . . . 161B.5 PCB for the digital inverter control circuit. . . . . . . . . . . . . . . 162B.6 PCB for the analog inverter control circuit. . . . . . . . . . . . . . . 163


List of Tables

1.1 Bidirectional interface system parameters . . . . . . . . . . . . . . . 3

3.1 BSB DB12-40 battery specications. . . . . . . . . . . . . . . . . . 223.2 Converter circuit parameters. . . . . . . . . . . . . . . . . . . . . . 293.3 IRFP264 MOSFET parameter values. . . . . . . . . . . . . . . . . . 293.4 Pre-charge soft-start circuit component values. . . . . . . . . . . . . 333.5 Post-charge soft-start circuit component values. . . . . . . . . . . . 353.6 Component values used in oscillator gate-drive circuit. . . . . . . . 373.7 TLP250 characteristic values. . . . . . . . . . . . . . . . . . . . . . 373.8 Triangular waveform generator component values. . . . . . . . . . . 403.9 Component values for the current sense circuit. . . . . . . . . . . . 433.10 Component values for the current loop compensator. . . . . . . . . 473.11 Component values for the voltage loop compensator. . . . . . . . . 543.12 Stability analysis of the voltage control loop at various mean in-

ductor current operating points. . . . . . . . . . . . . . . . . . . . . 55

5.1 Three phase induction machine characteristic values. . . . . . . . . 695.2 Calculated machine parameters. . . . . . . . . . . . . . . . . . . . . 725.3 Machine parameters used for modelling. . . . . . . . . . . . . . . . 75

6.1 FS30R06W1E3 IGBT module parameter values. . . . . . . . . . . . 876.2 ACPL-333J gate driver characteristic values. . . . . . . . . . . . . . 946.3 Parameter values of the dsPIC30F4013 DSP. . . . . . . . . . . . . . 1016.4 Component values for the magnetic pick-up and dsPIC interfacing

circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036.5 Allegro ACS756 Hall eect sensor characteristics. . . . . . . . . . . 1076.6 Component values for the current feedback circuit. . . . . . . . . . 108

xiii


Nomenclature

Variables

fs switching frequency . . . . . . . . . . . . . . . . . . . . . . [ kHz ]

idc instantaneous dc bus current . . . . . . . . . . . . . . . . . [A ]

iL instantaneous inductor current . . . . . . . . . . . . . . . . [A ]

ma modulation index . . . . . . . . . . . . . . . . . . . . . . . [ ]

Abbreviations

ac alternating current

ADC analog-to-digital converter

DAC digital-to-analog converter

dc direct current

DSP digital signal processor

emf electromotive force

IC integrated circuit

IGBT insulated-gate bipolar transistor

LUT lookup table

mmf magnetomotive force

MOSFET metal-oxide-semiconductor eld-eect transistor

MPPT maximum power point tracking

NTC negative temperature coecient

PCB printed circuit board

PI proportional-integral

PWM pulse-width modulation

RAT ram air turbine

rms root mean square

VSD variable-speed drive

VSI voltage source inverter

xiv


Chapter 1

Introduction

1.1 Background

In order to support an electrical load on board an aircraft, additional power isrequired. For this application a ram air turbine (RAT) generator can be usedto supply the necessary power in conjunction with a storage unit such as abattery or supercapacitors. The RAT is driven by the airow surrounding thesub-sonic aircraft and acts as the main power supply providing average powerto a load. Generally the storage unit is only used to supply power duringtransient conditions [1]. If however the RAT is unable to supply the requiredpower due to a lack of airow, the storage unit supplies the necessary poweruntil it is depleted. The storage unit is charged when the RAT is supplyingexcess power.

A prototype circuit that demonstrates the interface between an air-poweredturbine generator and a battery of electrochemical cells to an electrical loadon board an aircraft is proposed. To simulate the airow through the turbinean asynchronous machine is employed to turn the shaft of an asynchronousgenerator. A speed-varying inverter will be used to control the voltage andfrequency applied to the stator windings of the driving machine, thus simulat-ing varying airow conditions. A deep-cycle lead-acid battery will be used asthe storage unit. The layout of the proposed circuit is shown in Fig. 1.1.

BidirectionalSwitched-Mode

dc-dcConverter

L

O

A

D

Bidirectional3-Phase

Switched-ModeInverter

M

Figure 1.1: Block digram of a bidirectional battery and machine interfacecircuit.

1


CHAPTER 1. INTRODUCTION 2

The battery is connected to a dc bus through a non-isolated bidirectional dc-dcconverter and the asynchronous machine interfaces with the dc bus through anon-isolated bidirectional inverter. The interface is required to transfer up to2 kW of electrical power between the battery and asynchronous machine. Theload is connected between the positive and negative dc bus rails. The proposednominal dc bus voltage is 350 V rail-to-rail. A reasonably high bus voltage isused to reduce the current within the dc bus, thus reducing self-heating whileimproving the eciency of the power distributed to the load.

The dc-dc converter is bidirectional to facilitate extended periods of re-generative braking (during which energy is returned to the battery). Theconverter is required to be current-controlled and voltage-regulated. As suchthe direction of current to or from the batteries will be regulated as a functionof the dc bus voltage.

The inverter circuit will function as a synchronous rectier to facilitate theow of current from the asynchronous machine to the dc bus whilst airborne.

1.2 Thesis Objectives

The thesis objectives can be divided into three parts. The rst objective is todesign, manufacture and test the bidirectional non-isolated current-controlledvoltage-regulated switched-mode dc-dc converter that is required to interfacea bank of batteries to a dc bus. The bidirectional transfer of up to 2 kWelectrical power between a nominally 350 V dc bus and a bank of batteries isto be demonstrated. The eciency of the converter is to be determined. Aclosed-loop control circuit is required for the design of the converter and willbe analysed before manufacturing the prototype circuit to ensure the stabilityof the design.

Secondly, the design, manufacture and testing of a bidirectional non-isolatedcurrent-regulated switched-mode inverter is required to interface a commer-cially available 3-phase asynchronous machine to a dc bus. A bidirectionaltransfer of up to 2 kW electrical power between a 3-phase asynchronous ma-chine and a nominally 350 V dc bus is to be demonstrated. The shaft ofthe inverter-connected asynchronous machine will be coupled to an identical3-phase asynchronous machine controlled by an o-the-shelf variable-speeddrive (VSD) to function as the air-driven turbine. Low-speed commerciallyavailable 3-phase asynchronous machines (400 V AC, 3 kW, 3000 rpm) willbe employed. A closed-loop control circuit will be designed and analysed toensure the closed-loop stability of the design. Table 1.1 shows a summary ofthe system parameters.

The last objective is to integrate and test the inverter, dc bus and dc-dcconverter interface. A bidirectional transfer of up to 2 kW of electrical powerbetween the inverter, converter and the load is to be demonstrated. Thebattery current due to the 2 kW load at the output of the dc-dc converter



Table 1.1: Bidirectional interface system parameters

Parameter ValueSystem power rating (bidirectional) 2 kWDC bus voltage operating range 340 V - 360 VNominal dc bus voltage 350 VMachine speed rating 3000 rpmMachine power rating 3 kWMachine voltage rating 400 V AC

should be shown to progressively decrease to zero as the mechanical powerapplied to the shaft of the inverter-connected machine is progressively raised,until such point as the power delivered by the inverter (less losses) equalsthat consumed by the load. Similarly, the battery current should be shown tofurther decrease (below zero) as the mechanical power applied to the shaft ofthe inverter-connected machine is progressively raised beyond that consumedby the load. Thus, the batteries should discharge while the batteries sourcepower to all or a fraction of the load's requirement, and should charge whilethe asynchronous machine sources power in excess of that consumed by theload.

1.3 Thesis Outline

The structure of the thesis is briey described below in terms of the contentprovided in each of the chapters.

Chapter 2 provides background information on the relevant literatureused in this thesis. Previous work regarding the use of ram air turbines asgenerators is discussed. Bidirectional converter and inverter topologies areinvestigated along with pulse-width modulation schemes that can be used tocontrol these circuits. The operation and development of an equivalent circuitfor an asynchronous machine are also presented.

Chapter 3 describes the basic circuit operation of the bidirectional dc-dcconverter circuit. A detailed design of the control circuit used for the converteris presented along with the frequency domain closed-loop stability analysis ofthe system.

Chapter 4 presents the time domain analysis of the dc-dc converter. Thesimulation results are compared to the measured results of the prototype cir-cuit, which was manufactured from the specications given in Chapter 3.

Chapter 5 derives the asynchronous machine parameters from the equiv-alent machine model and the datasheet information. The machine model issimulated and the results are compared to the given datasheet information inorder to conrm the credibility of the model. The generator operation of the



machine is also investigated.Chapter 6 describes the basic circuit operation of the inverter functioning

as a synchronous rectier. A detailed design of the control loops used tocontrol the inverter switching action is presented. Frequency domain analysisis used to conrm the closed-loop stability of the system. The implementationof additional safety features is discussed.

Chapter 7 details the integration of the inverter and dc-dc converter cir-cuit. The time domain simulation of the inverter circuit is compared with themeasured results from the prototype circuit. The dc-dc converter's bidirec-tional capability is investigated. The test results used to conrm the successfulintegration between the converter and inverter circuits are presented. Lastly,the safety features' testing procedures and results are given.

Chapter 8 concludes the thesis by presenting the overall system simulationand test results. Future work and recommendations are also considered.


Chapter 2

Literature Review

This literature review gives background information on some of the key ele-ments of the proposed project. The focus is on the use of ram air turbines asgenerators, the development of converter and inverter circuits and the mod-elling and operation of three-phase asynchronous machines.

2.1 Ram Air Turbines as Generators

Ram air turbine systems are most commonly used to supply emergency poweron-board aircraft when the main power supply fails but can also be used tosupply continuous power whilst airborne. The turbine usually drives an electricgenerator connected to a dc bus and is supported by a battery or other storagedevice to form a hybrid system [1]. Some of the key requirements of sucha system include high reliability, adequate load regulation and high overallsystem eciency.

2.1.1 Energy Management Strategies

Since the RAT speed will vary during ight, controlled converters are gener-ally required. These converters operate either to form a controlled interfacebetween the machine and the supply bus, or to regulate the machine excitation,or both [2]. In [1] and [3] two energy management strategies are investigatedto interface a RAT and a storage device: the conventional strategy and a dualstrategy.

The conventional strategy makes use of a current-controlled dc-dc converterto interface the dc bus and the storage unit. The RAT is used as a voltagesource and the excitation current of the generator is controlled to maintain aconstant dc bus voltage at the output of the rectier. The RAT is thus onlyused to supply the required average power to the load while the storage unitsupplies peak and transient power.

5


CHAPTER 2. LITERATURE REVIEW 6

In the dual-control strategy, the RAT's generator excitation voltage is con-trolled in order to regulate the current supplied to the dc bus, while the storagedevice with its dc-dc converter is used to regulate the dc bus voltage. This al-lows the use of maximum power point tracking (MPPT) but only if the powerdemanded by the load and storage device exceeds the maximum power that canbe supplied by the RAT. MPPT techniques are explained in detail in [4, 5, 6].The overall objective is to provide the optimal rotor speed with respect to theratio between the blade-tip speed and wind speed [7]. This will produce themaximum amount of machine torque and power. The dual strategy optimisesenergy transfer and is therefore the preferred control strategy.

MPPT is very popular in wind-power applications where the power deliv-ered by wind-driven generators are fed back into a grid or other storage unitwith a large storage capacity. In the case of a ram air turbine, the RAT is onlyused to supply the power required by the load and to charge the storage deviceto its recommended capacity. Thereafter, no more power must be deliveredto the system since there is no place to dump the excess power. If MPPT isused in RAT applications, the system must be designed such that it will exitMPPT mode if the load power requirement is less than the RAT's maximumpower.

2.1.2 Existing Power Generation Topologies

Various approaches have been investigated to generate power from a ram airturbine and is summarised in this subsection. In 2005 P.H. Mellor publisheda paper [8] on generating power from a RAT using a brushless permanent-magnet (PM) generator and an integrated xed-ratio gearbox. The machinewas controlled to produce optimal torque at low speeds, while at high speedsthe peak line voltage was limited to the desired dc bus voltage. A resolver tomeasure the degrees of shaft rotation was used for feedback along with machinecurrent measurements. An insulated-gate bipolar transistor (IGBT) moduleand a digital signal processor (DSP) based controller was used to control thegenerator. This design showed an overall system eciency of 84 %.

A dierent approach was used by P. Bolognesi in [2] where the generatorfor the RAT was a hybrid-excited dc machine consisting of both permanentmagnets and eld coils. The armature of the dc machine is directly connectedto the dc bus, while the excitations of the eld coils are controlled by means ofa chopper circuit to keep the dc bus voltage within the desired voltage range.Extensive modelling showed the validity of such a system.

In [1] the use of a hybrid system comprising of supercapacitors and a syn-chronous generator are proposed to generate power on board an aircraft. Abidirectional current-controlled dc-dc converter is used to interface with thedc bus and supercapacitors. To reduce current ripple and increase the ap-parent switching frequency, an interleaved converter was used consisting oftwo IGBT modules with triple buck-boost branches where the PWM signals



for each branch are 120 degrees phase shifted. Proportional-integral controllersare used to regulate the dc bus voltage. The stator currents of the synchronousgenerator are rectied through a three-phase diode-bridge rectier to producepower to the load. Both the conventional and dual energy-management strate-gies were tested and shown to have nearly equivalent dynamic behaviour.

Similar work was done by X. Roboam in [3] with a bigger focus on thedierence between the two energy management strategies. The only dierencewas shown to be that the dual strategy allows faster dc bus regulation andmaintains better system stability during transient operation.

A lithium-ion battery and RAT interface is presented in [9]. The turbineis connected to a synchronous generator through a speed multiplier. A dioderectier, connected to the dc bus, is used to rectify the three-phase statorvoltages. A bidirectional dc-dc converter is used for interfacing the dc bus andLi-Ion battery. Again, both the conventional and dual strategies were tested.The dc bus voltage ripple on the conventional strategy was shown to be lessthan for the dual strategy, while the dual strategy showed slightly better dcbus regulation.

2.2 DC-DC Converters

The proposed circuit for this thesis requires a switched-mode bidirectionaldc-dc converter to interface with the dc bus and battery storage device. Theintention is to control the converter current in order to regulate the dc busvoltage. In switched-mode converters this is achieved by controlling the onand o time of the switches. Dierent switching schemes exist but the mostwidely used scheme is pulse-width modulation [10] which employs switchingat a constant frequency.

2.2.1 Pulse-Width Modulation

Pulse-width modulation (PWM) varies the duty cycle of converter's switchesat a high frequency to obtain the desired average output voltage or current[10]. An example of a circuit that uses PWM to control the switches is shownin Fig. 2.1, where insulated-gate bipolar transistors (IGBTs) are used as theswitches. The signal to determine the state of a switch (on or o) is obtainedby comparing the control signal to a repetitive waveform with a constant fre-quency, referred to as the carrier waveform as shown in Fig. 2.2. The carrierwaveform can either be a sawtooth or triangular waveform [10]. The dier-ence between the desired and actual output is passed through a compensationamplier to generate the required control signal [11].



−

Vd

2

+

−

Vd

2

+

S1

+

-

voS2

Figure 2.1: Half-bridge converter circuit.

t

1

−1

t

Vd

2

−Vd

2

Figure 2.2: PWM signal (green line) generated using a control signal (red line)and sawtooth carrier waveform (blue line).

The duty cycle of a switch with constant control signal vcontrol is expressed by

D =tonTs

=vcontrol

Vc

, (2.1)

where Ts is the switching period which corresponds to the carrier waveformfrequency and Vc is the peak value of said carrier waveform.

PWM strategies can be divided between naturally sampled PWM andregular sampled PWM. Naturally sampled PWM is the earliest and moststraightforward strategy which compares a low-frequency control signal to ahigh-frequency carrier waveform and is used in analog controllers, as shown inFig. 2.2. Regular sampled PWM is used in digital control systems where thecontrol signal is sampled at a regular interval and the duty cycle is adjustedin proportion to the value of the sample.



2.2.2 Bidirectional Converter Topology

An in-depth study on the dierent switched-mode dc-dc converter topologiesare given in [12]. For a bidirectional converter the most commonly used topol-ogy consists of a half-bridge circuit that can either sink or source current fromor to the dc bus [13], [14]. A simple bidirectional half-bridge circuit is shownin Fig. 2.3 with metal-oxide-semiconductor eld-eect transistors (MOSFETs)as switches. Alternatively, IGBTs can be used as switches and should includefreewheeling diodes across them.

Vbat

LiL vm

Q2

Q1

C

+

−

Vdc

Figure 2.3: Bidirectional dc-dc converter circuit.

From rst principles it is known that the average voltage across an induc-tor under steady state conditions must equal zero [11]. Thus, the followingstatement with respect to Fig. 2.3 can be made:

Vbat = vm, (2.2)

where vm is the average mid-point voltage which can be calculated as

vm =

(t1(on)Ts

Vdc +t2(on)Ts

0

), (2.3)

where t1(on) and t2(on) is the on-time of switches Q1 and Q2, respectively. From(2.2) and (2.3) the relationship between the dc bus voltage and the batteryvoltage is thus

Vdc =Vbatt1(on)

Ts

=Vbat

D1

, (2.4)

where D1 is the duty cycle of Q1. The duty cycle of Q2 is

D2 =t2onTs

= 1−D1 = 1− Vbat

Vdc

, (2.5)

such that Q1 and Q2 is never on simultaneously. For ideal switches the aboveequation would suce to prevent short-circuit conditions. However, in real



life switches require a nite amount of time to change state. By introducingdead-time, cross conduction can be avoided. The dead-time inserts a smalltime delay before a switch is turned on in order to allow the other switch tocompletely switch o rst [15].

2.3 DC-AC Inverters

For the proposed project a bidirectional three-phase switched-mode ac-dc in-verter circuit is required to interface an asynchronous generator and dc bus.Two topologies exist for inverter circuits, namely current source inverters(CSIs) and voltage source inverters (VSIs). CSIs are only used in very highpower applications. For this literature review only VSIs will be consideredsince they are by far the most commonly used inverter topology [11].

2.3.1 Three-Phase Inverters

The basic topological structure of an inverter circuit is a half-bridge. A three-phase inverter requires three half-bridges where each half-bridge pole-pointconnects to one of the output load terminals as shown in Fig. 2.4. The switchescan either be IGBTs with freewheeling diodes or MOSFETs with built-in diodesto support bidirectional power ow [15].

idc

C

+Vdc

−Vdc

S1

S2

vAo

S3

S4

vBoiBo

S5

S6

vCoiCo

iAo

3-PhaseLoad

Figure 2.4: Three-phase voltage source inverter connected to a three-phaseload.

The principle of operation is similar to that of the circuit described in Section2.2.2 where the top and bottom switch of each phase leg are switched com-



plementary to each other. Considering the half-bridge circuit with switchesS1 and S2, when S1 is switched on the pole voltage vAo gets pulled high to+Vdc and when S2 is on vAo gets pulled down to −Vdc. By controlling theon-time of the switches the fundamental voltage across the load terminals canbe controlled. A PWM technique is thus generally also used in VSI circuits tocontrol the switches [16].

t

t

t

t

fA(t) fB(t) fC(t)

vAo

vBo

vABM

√3

M

Figure 2.5: PWM voltages generated in three-phase inverter applications.

Three-phase PWM is described in Figure 2.5. It shows three control sinusoidsfA(t), fB(t) and fC(t) indicated in red, green and black respectively, where eachwaveform is controlling one half-bridge. The three waveforms are phase shiftedby 120 degrees relative to each other to generate the required fundamentalthree-phase voltage waveforms at the load terminals. A triangular waveformis used as the carrier waveform and is indicated in blue. The two PWMvoltage waveforms vAo and vBo represent the two pole voltages from Fig. 2.4,respectively. If the load is connected in delta conguration, the voltage appliedacross one of the three load windings will equal the dierence between the twoinverter pole voltages vAo and vBo. The resulting PWM waveform is shown asvAB in Fig 2.5. If vAB is put through a low pass lter the resulting waveformis a sinusoid with a amplitude

√3 times greater than that of the fundamental

pole voltage waveforms indicated in Fig 2.5.The required dead-time to prevent a short-circuit between the dc bus rails

varies with the power rating of the inverter circuit. Typically the requireddead-time to ensure safe operating conditions is well below 1 µs [15].



2.3.2 Inverter Control Schemes

VSIs can be classied as either current- or voltage-controlled. A CCVSI hasthe advantage of inherent overcurrent protection.

Three main control schemes exist for inverters that drive ac machinesnamely scalar control, vector control and direct torque control [17]. Scalarcontrol techniques have been widely used in industry and are easy to imple-ment [16]. Volt/Hertz control is a scalar control technique where the ratiobetween the stator voltage and frequency is kept constant to ensure a con-stant air gap ux close to rated ux [18]. Volt/Hertz control is thus used involtage-controlled voltage-source inverters (VCVSIs). Scalar control gives in-ferior performance compared to vector control schemes in terms of their speedresponse. However, if the speed of the machine is not required to changerapidly, scalar control provides more than adequate performance [18].

Vector control allows an ac machine to be controlled as if it were a sepa-rately excited dc motor by transforming its phase currents into a synchronouslyrotating reference frame [19]. The two resulting currents are dc currents, onerepresenting the torque producing component of the stator current while theother corresponds to the ux producing component of the stator current. Bycontrolling these two currents the machine ux and torque can thus be con-trolled. Vector control, also known as eld-oriented control, provides excellentperformance but with the drawback of high complexity. Vector control schemesrequire a powerful microcontroller or DSP [16]. With vector control the innercontrol loop is always current controlled allowing it to function as a CCVSI.Dierent forms of eld-oriented control (FOC) exist such as indirect FOC [20]and direct FOC [21], [22].

Direct torque control (DTC) schemes control both the torque and statorux of the machine whereby the required ux and torque is compared to therespective estimated values to generate two error voltages. The error voltagesare constrained to lie between an upper and lower limit respectively, thusproviding hysteresis-band control [23]. A detailed description of DTC is givenin [17]. Direct torque control schemes have shown similar performance to thatof vector control schemes [16]. The combination of DTC and vector controlschemes also exist and is presented in [24].

2.4 Asynchronous Machines

This project will make use of two asynchronous machines, one to functionas a generator, the other to drive the shaft of the generator. The operationof asynchronous machines is investigated in order to model and develop thecontrol circuit for the inverter controlling the generator.



2.4.1 Principle of Operation

Asynchronous machines, also known as induction machines, are the most com-monly used type of ac machines in industry. The machine consists of a statorand rotor winding that are magnetically coupled to transfer energy betweenmechanical and electrical systems [19]. The rotor of an induction machine canbe classied as either a wound rotor or a squirrel-cage rotor. Wound rotor in-duction machines are fairly uncommon, thus for this study only squirrel-cagerotor induction machines are investigated. A squirrel-cage rotor is constructedsuch that the windings on the rotor are conducting bars short-circuited ateach end by conducting rings. Both the stator and rotor cores are made fromlaminated ferromagnetic material.

The fundamental principle of induction machines is that of a rotatingsinusoidally-distributed magnetic eld within the air gap of the machine. Thisis achieved by applying balanced sinusoidal three-phase voltages to the statorwindings and in return a synchronously rotating magnetic eld is produced.A summary of the analytical derivation [16] follows below.

−a

a

b

−b−c

c

Axis ofphase a

Axis ofphase c

Axis ofphase b

θe

Figure 2.6: Ideal three-phase, two pole induction machine.

Figure 2.6 shows an ideal three-phase, two-pole induction machine where thephase windings for the stator are indicated by concentric circular coils. Themachine can either be connected in delta or wye conguration. The three-phasewindings are 120 degrees displaced from each other (sinusoidally distributed)and the air gap in the machine is considered uniform.



When balanced sinusoidal three-phase voltages are applied to the windings theinstantaneous currents are

ia = Imaxcos(ωet), (2.6)

ib = Imaxcos(ωet− 120°), (2.7)

ic = Imaxcos(ωet+ 120°), (2.8)

where Imax is the maximum stator winding current, ωet is the frequency of theapplied excitation voltage and t denotes time. Each of the phase windings willindependently induce a sinusoidally distributed magnetomotive force (mmf)wave since

F = Ni, (2.9)

where F is mmf and N is the number of turns in a phase winding. Theresulting mmf expressions are given by

Fa = Niacos(θ), (2.10)

Fb = Nibcos(θ − 120°), (2.11)

Fc = Niccos(θ + 120°), (2.12)

where θ is the spatial angle. The total mmf at angle θ is given as

F(θ) = Fa(θ) + Fb(θ) + Fc(θ)

= Niacos(θ) +Nibcos(θ − 120°) +Niccos(θ + 120°).(2.13)

Substituting (2.6) through (2.8) in (2.13) results in

F(θ, t) = NImax [cos(ωet)cos(θ) + cos(ωet− 120°)cos(θ − 120°)

+ cos(ωet+ 120°)cos(θ + 120°)] . (2.14)

After simplifying (2.14) the expression becomes

F(θ, t) =3

2NImaxcos(ωet− θ). (2.15)

The air gap mmf wave from (2.15) is shown to be sinusoidally distributed,rotating at synchronous speed ωs where

ωs =2

polesωe. (2.16)



For a two-pole machine the angular frequency of the applied electrical excita-tion ωe is equal to the synchronous speed of the air gap mmf ωs. In revolutionsper minute the synchronous speed can be expressed by

ns =

(120

poles

)fe, (2.17)

since

fe =ωe

2π, (2.18)

where fe is the applied electrical frequency. The time-varying mmf wave willproduce an electric eld in accordance with Faraday's law:∮

c

E · ds = − d

dt

∫S

B · da. (2.19)

Equation (2.19) states that the induced electromotive force (emf) around aclosed contour is equal to the negative rate of change of the magnetic ux φpassing through an enclosed area [25] since

φ =

∫S

B · da. (2.20)

The rotor winding forms the closed contour and links the core ux N times,thus (2.19) reduces to

e = −Ndφ

dt= −dλ

dt, (2.21)

where λ is the ux linkage of the winding. The emf e will cause an inducedcurrent to ow in the rotor winding. When the current-carrying winding isexposed to a magnetic eld, torque is produced to rotate the rotor winding.This is referred to as the starting torque. If the torque on the load attachedto the shaft of the motor is less than the starting torque, the rotor will startto turn [16]. The rotor will turn in the same direction as that of the rotatingmmf wave in accordance with Lenz's law, which states that an induced emfproduces a current that will ow in the direction to oppose the change whichproduced it [25].

If the rotor were to rotate at synchronous speed, no induction would takeplace and hence no torque would be produced. At any other speed, rotorcurrent is induced and asynchronous torque is developed, hence the nameasynchronous machine. The dierence between the synchronous speed ns andthe rotor shaft speed nr is called the slip speed and is commonly referred toas the slip of the motor. Slip s in per unit is

s =ns − nr

ns

=ωs − ωr

ωs

=ωsl

ωs

, (2.22)



where ωsl is the slip frequency. Slip is generally expressed as a percentage ofthe synchronous speed. From (2.22) the rotor speed is

nr = (1− s)ns, (2.23)

or

ωr = (1− s)ωs. (2.24)

While the rotor is stationary, the slip is 1 per unit and the rotor now behavesthe same as a secondary winding on a transformer. The rotor frequency isthe same as the stator frequency until the rotor starts to turn. The relativemotion between the stator ux and rotor is responsible for the induced emf inthe rotor windings and the frequency of the induced emf in the rotor is

fr = sfe, (2.25)

where fe is the electrical frequency of the applied currents in the stator. If theper unit slip value is between 1 and 0 the asynchronous machine is operatedas a motor and hence electrical power is converted to mechanical power. From(2.24) a per unit slip value smaller than 0 indicates the rotor shaft speedis greater than the synchronous stator speed. To achieve this, torque hasto be applied to the shaft of the induction machine and thus the inductionmachine now functions as a generator. The stator terminals are then used asa voltage source to supply electrical power [26]. Applications include the useof an induction generator driven by a wind turbine and connected to a powersystem to provide renewable energy. This thesis will use an induction machineoperated at negative slip in order to supply power to a load.

2.4.2 Equivalent Circuit

A transformer functions by transferring power exclusively to windings throughinduction. An induction machine can thus be seen as a transformer witha rotating secondary winding [27]. Due to the similarity between inductionmachines and transformers, the model of an induction machine is similar tothat of a transformer. A single-phase equivalent circuit of a squirrel-cageinduction motor is shown in Fig. 2.7.

The stator side is modelled as an inductor Lls in series with a resistor Rs

to represent the leakage impedance. The air gap model consists of two shuntcomponents, a core-loss resistance Rc and a magnetizing inductance Lm. In-duction machines are usually operated at low slip and hence the frequency ofthe induced rotor emf is also low. Due to this, the core loss of the rotor mag-netic circuit is often ignored [27]. The rotor is modelled as leakage inductanceLlr in series with rotor resistance Rr. The rotor quantities are however referredto the stator side assuming a turns ratio of 1:1. The impedance of the rotorreferred to the stator is



−Vs

+

Rs

Is

Lls Llr

IrRr

SLmRc

Figure 2.7: Single-phase equivalent circuit of an induction motor.

Zr = Rr + jωslLlr. (2.26)

After substituting (2.22) in the above equation and simplifying, (2.26) becomes

Zr =Rr

s+ jωsLlr. (2.27)

The rotor reactance is now dened in terms of the stator frequency and canbe analysed as part of the stator equivalent circuit as shown in Fig. 2.7.

From the equivalent circuit the necessary power equations can be deter-mined. For a three-phase motor the input power is

Pin = 3VsIscos(θ), (2.28)

where θ is the phase dierence between the applied stator voltage Vs and thecurrent Is owing through the stator winding. The stator winding copper lossis

Pstator = 3Is2Rs. (2.29)

The power transferred across the air gap is

Pgap =3Ir

2Rr

s. (2.30)

The rotor copper loss is

Protor = 3Ir2Rr. (2.31)

The electromechanical power developed by the motor is thus

Pmech = Pgap − Protor = 3Ir2Rr

(1− s

s

)= (1− s)Pgap. (2.32)

The electromechanical torque produced can be calculated since mechanicalpower is equal to angular velocity times torque [26]. With reference to (2.24)the mechanical torque expression becomes

Tmech =Pmech

ωr

=Pgap

ωs

= 3Ir2 Rr

sωs

. (2.33)



The current owing in the rotor is thus responsible for creating the requiredmotor torque. The torque applied to the shaft of the motor will equal themechanical torque minus the friction, windage and other rotational losses.This equivalent circuit and derived equations of an induction machine can beused to model and predict the behaviour of induction machines.

2.4.3 Dynamic d-q Model

For a dynamic model of a three-phase machine, three equivalent circuits arerequired, one for each phase. In order to simplify and reduce the total numberof dierential equations, a variable transformation rst formulated by R.H.Park in the 1920's can be applied to the equivalent circuit. The Park trans-formation refers stator variables to a synchronously rotating reference framewith respect to the rotor. The transformation has since been generalised suchthat machine variables are referred to a frame of reference that is rotatingat an arbitrary angular velocity. The preferred transformation to analyse thedynamic behaviour of a balanced three phase machine is where both the statorand rotor variables are transformed to a synchronously rotating dq0 referenceframe that turns with the rotating magnetic eld. This transformation turnsthe voltage and current ac quantities into dc quantities allowing better analysisof the machine's transient responses [19].

The dq0 transformation transforms the three-phase abc system into two ro-tating components, namely the direct (d) and quadrature (q) axis. The q-axisis aligned with the a-axis and precedes the d-axis by 90°. A third component,the zero-sequence component, is also included to complete the transformationof the three phase variables. However, under balanced three phase conditions,no zero-sequence components are present [26]. The formulation of the dq0transform is explained in [28] and is given by

ξqd0 = K(φ)ξabc, (2.34)

where

K(φ) =2

3

cosφ cos(φ− 2π3) cos(φ+ 2π

3)

sinφ sin(φ− 2π3) sin(φ+ 2π

3)

12

12

12

. (2.35)

The inverse dq0 transform is used to transform the variables back to the abcreference frame and is given by

ξabc = K−1(φ)ξqd0, (2.36)

where

K−1(φ) =

cosφ sinφ 1cos(φ− 2π

3) sin(φ− 2π

3) 1

cos(φ+ 2π3) sin(φ+ 2π

3) 1

. (2.37)



The angle φ is equal to ωet for the synchronously rotating reference framewhere all variables are referred to the stator side.

The dynamic d-q model [29] of the equivalent circuit analysed in Section2.4.2 is shown in Fig. 2.8. The core-loss resistance is omitted for this model.Note, the rotor side is short-circuited as would be the case for a squirrel-cageinduction machine.

−vqs

+

Rs

iqs ωeλds

+ − Lls Llr

iqr (ωe − ωr)λdr

− +

RrLm λqrλqs

(a)

−vds

+

Rs

ids ωeλqs

− + Lls Llr

idr (ωe − ωr)λqr

+ −

RrLm λdrλds

(b)

Figure 2.8: Dynamic d-q model of a squirrel cage induction motor for the (a)q-axis component and (b) d-axis component.

From Fig. 2.8 the following dierential equations can be deduced:

vqs = Rsiqs +d

dtλqs + ωeλds, (2.38)

vds = Rsids +d

dtλds − ωeλqs, (2.39)

vqr = 0 = Rriqr +d

dtλqr + (ωe − ωr)λdr, (2.40)

vdr = 0 = Rridr +d

dtλdr − (ωe − ωr)λqr, (2.41)

where the ux linkages can be written as:

λqs = Llsiqs + Lm(iqs + iqr), (2.42)

λds = Llsids + Lm(ids + idr), (2.43)



λqr = Llriqr + Lm(iqs + iqr), (2.44)

λdr = Llridr + Lm(ids + idr). (2.45)

From [16] the derived torque expression for the developed motor torque in d-qform becomes:

Te =3

2Lm(iqsidr − idsiqr). (2.46)

In variable frequency applications the rotor speed ωr is not a constant and canbe related to the torque by

Te = TL + Jdωr

dt, (2.47)

where TL is the load torque and J is the rotor inertia.Equations (2.38) to (2.47) provide the complete model of an induction

machine and will be used for modelling purposes.

2.5 Summary

This chapter gave the foundation of the research covered in this thesis. Pre-vious work regarding the use of ram air turbines as generators was presented.Bidirectional converter and inverter topologies were investigated, along withpulse-width modulation schemes that are used to control both inverter andconverter circuits. The operation and development of the equivalent circuitfor an asynchronous machine were also presented.


Chapter 3

DC-DC Converter Design and

Implementation

This chapter describes the design of a non-isolated bidirectional current-controlledvoltage-regulated switched-mode dc-dc converter. To facilitate the regulationof the dc bus voltage, two control loops (an inner and an outer) are employed.A detailed design of the control circuitry is given and the closed-loop stabilityis investigated. The design of a two-stage soft-start circuit to limit the inrushcurrent from the battery to the dc bus during start-up is presented as well asthe design of the gate-drive circuitry.

3.1 Basic Circuit Operation

The dc bus voltage is required to be regulated in the range of 340 V to 360 V(350 V nominal), regardless of the direction of current ow through the bat-tery. The dc bus is divided between a positive (+175 V) and negative (-175 V)rail to achieve a nominal rail-to-rail voltage of 350 V. Each rail section has itsown bidirectional converter and is designed to function independently usingidentical controllers. The chosen converter topology is two bidirectional half-bridge circuits, one on top of the other, as shown in Fig. 3.1 with the midpointgrounded.

Twenty 12 V, 40 Ah rated deep-cycle lead-acid batteries are divided be-tween the two rail sections, each using ten batteries indicated by Vbat. Table 3.1shows the characteristic values of a single BSB DB12-40 battery with a oatinglife expectancy of 12 years. The internal battery resistance, equivalent seriesresistance of the inductor and the resistance of the switches are all accountedfor by one representative resistor in the converter denoted Rin in Fig. 3.1.

For the duration of this thesis small letter variables refer to instantaneousvalues while capital letter variables refer to average values.

If the average inductor current IL is positive, current is owing from the dcbus into the batteries, thus charging the batteries. A negative average induc-

21


CHAPTER 3. DC-DC CONVERTER DESIGN AND IMPLEMENTATION 22

Rin

Vbat

LiL vm

id2Q2

iQ2

id1Q1

iQ1

ic

C

+Vdc

idc

Rin

Vbat

LiLvm

id3Q3

iQ3

id4Q4

iQ4

C

−Vdc

Figure 3.1: Bidirectional dc-dc converter circuit.

Table 3.1: BSB DB12-40 battery specications.

Parameter Description ValueVb Rated battery voltage 12 VQAh Charge capacity 40 AhVbf Maximum oat use charge voltage 13.8 VVbc Maximum cycle use charge voltage (10 A max) 14.8 VRb Internal resistance at full charge 9.5 mΩ

tor current indicates current owing from the batteries into a load connectedbetween the dc bus rails. To ensure the 2 kW bidirectional power ow spec-ication is met, the maximum and minimum average inductor current IL isset to ±10 A corresponding to ±2.4 kW of power at the battery's side of theconverter. Also, the recommended maximum charging current of the batteriesis given in the datasheet as 10 A.

Discrete MOSFETs are used as the switches for Q1 through Q4 and theswitching frequency is set to 40 kHz.

With reference to Fig. 3.1, Fig. 3.2 shows the inductor voltage and currentfor the top-half of the converter circuit when the batteries are being chargedat a maximum mean current of 10 A. When switch Q1 is on (and Q2 is o)the voltage across the inductor is vL(max) = Vdc-Vbat = 55 V. Similarly, when



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

−200

−100

0

100

v L(V

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

89101112

i L(A

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

0

100

200

v Q1(V

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

0

100

200

v Q2(V

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

0

5

10

15

i Q1(A

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

0

5

10

15

Time (s)

i d2(A

)

Figure 3.2: Current and voltage waveforms describing the operation of theconverter when the batteries are being charged at maximum current.

switch Q2 is on (and Q1 is o) the inductor voltage is vL(min) = -Vbat = -120 V.



Since

vL = LdiLdt

, (3.1)

the inductor current changes linearly with time. However in order that theinductor conduct a current that is on average (typically averaged over 5 to 10switching cycles) constant, the time averaged voltage applied to the inductormust be zero. That is to say VL = 0. Thus

t1(on)(Vdc − Vbat) + t2(on)(0− Vbat) = 0, (3.2)

where t1(on) is the on-time of switch Q1 and similarly t2(on) is the on-time ofswitch Q2. During individual switching cycles, however, the inductor currentramps up linearly through the MOSFET ofQ1 from its minimum value (iL(min))to its maximum value (iL(max)) during the on-time of switchQ1. The on-time ofa switch with respect to the total switching period is more commonly referredto as the duty cycle and for Q1 the duty cycle is

D1 =t1(on)Ts

=Vbat

Vdc

=120

175= 0.6857, (3.3)

as derived in Section 2.2.2. Similarly the inductor current ramps down fromits maximum to its minimum value during the on-time of Q2. Thus the dutycycle of Q2 is given by

D2 = 1−D1 =t2(on)Ts

=Vdc − Vbat

Vdc

=55

175= 0.3143. (3.4)

The voltage across the drain and source of switches Q1 and Q2 are shown inFig. 3.2. Due to the direction of current when the mean inductor current ispositive, current can only ow through the MOSFET of Q1 and through thediode of Q2. These current waveforms are also shown in Fig. 3.2 where iQ1

denotes the MOSFET current through Q1 and id2 denotes the diode currentthrough Q2 as indicated in Fig. 3.1.

The bottom-half of the converter will function in a similar manner wherethe duty cycle of switch Q4 equals that of Q1 and the duty cycle for Q3 is thesame as Q2's. The inductor current and voltage waveforms also remain thesame.

If the mean inductor current of 10 A were to change to -10 A, the basiccircuit operation stays the same, however current will ow in the oppositedirection, thus supplying current to the dc bus. Due to the change of currentdirection, current will now ow through the diode of Q1 and through theMOSFET of Q2 as shown in Fig. 3.1 and Fig. 3.3. The voltage across theinductor and switches will remain the same as before. The duty cycles of theswitches also remain the same.



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

−12−11−10−9−8

i L(A

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

0

5

10

15

i d1(A

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

0

5

10

15

Time (s)

i Q2(A

)

Figure 3.3: Current waveforms describing the operation of the converter whenthe batteries are sourcing maximum current.

3.1.1 Inductor Design

Both inductors labelled L in Fig. 3.1 are wounded from Litz wire with a3.8 mm2 total cross-sectional area (120 strands of 0.2 mm diameter enam-elled copper wire) wound over an Arnold A-866142-2 powdered-iron toroidalcore. The current density in the wire at a maximum average inductor cur-rent of 10 A is 2.65 A/mm2. The inductor is designed to have a peak-to-peakcurrent ripple of approximately 22.5 % of the absolute maximum value of themean battery current, thus 2.25 A.

Since the voltage applied across the inductor is constant while either Q1 orQ2 is on, then, from (3.1) and (3.2):

vL∆t = L∆iL

= vL(max)t1(on)

= −vL(min)t2(on).

(3.5)

Rearranging and substituting (3.3) and (3.4) into the above equation yields



∆iL =vL(max)D1Ts

L

= −vL(min)D2Ts

L

=37.7Ts

L,

(3.6)

where vL(max) and vL(max) were already determined as 55 V and -120 V. Witha peak-to-peak inductor current ripple of 2.25 A and given that

Ts =1

fs=

1

40 kHz= 25 µs, (3.7)

the value of the inductor L is thus calculated from (3.6) and (3.7) as 420 µH.The inductance rating, also known as the AL value of a core, is used to de-termine the amount of turns required to achieve a specic inductance for thatparticular core. The AL value for the Arnold A-866142-2 core is given in thedatasheet as 142 nH/turn2. The required number of turns is thus:

N =

√L

AL

= 54.32 ≈ 55. (3.8)

To ensure the inductor core will not saturate, additional calculation are needed.From Ampere's Law [26] it is known that

Hc =NILle

, (3.9)

where Hc is the average magnetic eld intensity in the core and le is the meanux path (core) length. Converting (3.9) into Oersted by multiplying with theconversion factor of 4π

1000, results in a magnetic eld intensity of

Hc =4πNIL1000 le

=(0.4)π(55)(10)

19.612= 35.24 Oe. (3.10)

The following relationship applies provided the inductor core is not saturated:

Bc = µHc, (3.11)

where Bc is the magnetic core ux density and µ the permeability given as125 in the datasheet. The resulting ux density in Kilogauss is thus 4.41 KG.When comparing these values to the datasheet showing the B-H curve of theA-866142-2 core in Oersted and Kilogauss, it can be seen that the core will onlysaturate for a magnetic eld intensity greater than 100 Oe. The magnetic corewill thus not saturate for the designed conditions. The B-H curve is howevernot completely within the linear approximation range of the permeability atthis point.

The graph indicates a true ux density of approximately 3.4 KG resultingin a permeability closer to 90 when a mean current of 10 A ows through the



55 core windings which will inuence the amount of inductor current ripple.Inductance can also be calculated as [26]

L =N2µAc

lc, (3.12)

where Ac is the cross-sectional area of the core. From the above equation itcan be seen that a decrease in permeability (with all other variables remainingconstant) will cause a decrease in inductance. A lower inductance with thesame amount of voltage applied across it for the same duration of time willultimately result in a larger current ripple as deduced from (3.6). The currentripple at a mean inductor current of zero or close to zero will thus have apeak-to-peak value equal to 2.25 A as designed for, however at a mean inductorcurrent of 10 A the inductor ripple will rise to a value closer to 3 A.

3.1.2 Bus Capacitor Design

The assumption is made that the mean current IQ1 owing through switch Q1

equals the mean dc bus current Idc, which is either sourced by another circuitor sunk by a resistive load connected between the dc bus rails. Thus,

Idc = IQ1 = ILD1, (3.13)

where IL is the average inductor current and D1 is dened in (3.3). The meandc bus voltage is assumed constant at 175 V, hence only the ripple componentof iQ1 ows through capacitor C. At a maximum average inductor currentof 10 A, the corresponding currents iQ1 and ic are shown in Fig. 3.4. Thecapacitor current ic is negative simply due to the positive reference directionchosen for the current as indicated in Fig 3.1.

By denition current is equal to the rate at which charge ows, hence:

ic =dq

dt, (3.14)

where q denotes electric charge. In integral form the above equation becomes

q =

∫icdt. (3.15)

From Fig. 3.2 and Fig. 3.3 it can be seen that the maximum magnitude of thecapacitor current ic will remain the same whether the mean inductor currentis positive or negative. From (3.15) the net charge ∆q, while either switch Q1

or Q2 is on, is calculated as the time integral of the capacitor current ic duringthat time period. With reference to Fig. 3.4 and while Q1 is o and Q2 is on,the net charge is calculated as an area where

∆q = IQ1D2Ts = (ILD1)D2Ts = 53.88 µC. (3.16)



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

0

5

10

15

i Q1(A

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

−5

0

5

10

i c(A

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

175

Time (s)

v dc(V

)

Figure 3.4: Waveforms indicating the capacitor current and voltage when thebatteries are being charged at the maximum current.

From rst principles it is known that charge is also equal to capacitance timesvoltage, hence:

q = Cvc, (3.17)

where vc is the voltage across the capacitor. The ripple component on the dcbus voltage is chosen as 30 mV (approximately 0.02 % of the mean dc busvoltage). The value of the capacitor required at the dc bus is thus calculatedas 1796 µF from (3.16) and (3.17).

Two parallel connected 1000 µF, 200 V Panasonic electrolytic capacitorswere chosen for each of the dc bus capacitors C shown in Fig. 3.1. The resultingvoltage ripple on the dc bus as shown in Fig. 3.4 is thus 27 mV. The rmsvalue of the capacitor current ic shown in Fig. 3.4 was calculated in MATLABas 4.54 A. Since two parallel connected capacitors are used, the rms currentthrough each of them is 2.27 A. The datasheet gives the maximum operatingrms ripple current as 4.85 A for one capacitor. The rms ripple current is thuswell within the allowed operating range.

The nal component values used in the bidirectional dc-dc converter circuitis given in Table 3.2.



Table 3.2: Converter circuit parameters.

Parameter ValueVdc 175 VVbat 120 VRin 1 ΩL 419 µHC 2000 µF

3.1.3 MOSFET Power Loss and Heat Sink Design

The switches used for Q1 through Q4 are International Rectier's IRFP264MOSFETs. Table 3.3 shows the characteristic values of the chosen MOSFETs.

Table 3.3: IRFP264 MOSFET parameter values.

Parameter Description ValueVDSS Drain-to-source breakdown voltage 250 VRDS(on) Static drain-to-source on-resistance (VGS = 10 V) 75 mΩID Maximum continuous drain current (Tc = 25°) 38 AQg Maximum total gate charge 210 nCtc(on) Turn-on (rise) time 99 nstc(off) Turn-o (fall) time 92 ns

The calculation of MOSFET power losses for half-bridge topologies are de-scribed in detail in [30] and [31] where the diodes are assumed ideal. For thebidirectional dc-dc converter circuit two cases have to be investigated, one forpositive inductor current and one for negative inductor current.

CASE 1: Positive Inductor Current

Current can only ow from the dc bus into the batteries when switch Q1 isclosed since the diode in Q1 is reversed biased. Switching as well as conductionlosses are thus present. Due to the direction of the inductor current, currentwill however ow through the freewheeling diode of Q2 causing diode losses.

When a MOSFET transitions from on to o and similarly from o to on,there is a small time period (tc(on) and tc(off)) during which the switch hasa voltage across it as well as a current owing through it. This results inswitching losses. In Fig. 3.2 the current through Q1 is shown. The absolutemaximum and minimum inductor current is 11.125 A (iL(max)) and 8.875 A(iL(min)) respectively, which corresponds to an average maximum current of10 A with 2.25 A of ripple. The average switching losses for Q1 are thuscalculated as [31]



Pc(on) =1

2VdciL(min)tc(on)fs, (3.18)

and

Pc(off) =1

2VdciL(max)tc(off)fs. (3.19)

The total switching losses for Q1 are thus

Pswitch =1

2Vdcfs

(iL(min)tc(on) + iL(max)tc(off)

)= 6.66 W.

(3.20)

The conduction losses occur due to the on-resistance of the switches and aregiven by [31]

Pcond = RDS(on)I2Q(rms). (3.21)

When switch Q1 is turned on the voltage across the inductor changes almostinstantaneously from −Vbat to Vdc−Vbat while the current through the inductorrises gradually from iL(min) to iL(max) at a rate of

diLdt

= m =Vdc − Vbat

L=

VL(max)

L, (3.22)

The rms value of the current through Q1 is calculated as [31]

I2Q1(rms) =1

Ts

∫ Ts

0

i2Q1dt

=1

Ts

∫ D1Ts

0

(iL(min) +mt

)2dt

=1

Ts

[1

3m

(iL(min) +mt

)3]D1Ts

0

=1

3mTs

[(iL(min) +mD1Ts

)3 − i3L(min)

]= 68.9 A2,

(3.23)

where D1 was calculated in (3.3). The total losses for Q1 are thus

PQ1 = Pswitch + Pcond = Pswitch +RDS(on)I2Q1(rms)

= 6.66 W+ 5.16 W = 11.82 W.(3.24)

The power loss due to the forward voltage of the MOSFET's freewheelingdiode is

PD = VSDId, (3.25)



where Id is the mean current owing through the diode over one switchingperiod. The graph in the IRFP264 MOSFET datasheet shows a forward diodevoltage (VSD) of approximately 0.8 V at 10 A of current. The mean diodecurrent of Q2 is calculated as

Id2 = ILD2 = (10)(0.3143) = 3.143 A. (3.26)

Thus, the diode conduction power loss in Q2 is

PD2 = VSDId2 = (0.8)(3.143) = 2.51 W. (3.27)

The total power losses for the top-half of the converter circuit whilst chargingthe batteries are

PT = PQ1 + PD2 = 14.33 W. (3.28)

The total power losses of the bottom-half circuit are however also equal to PT

since the losses in Q4 are equal to that of Q1 and similarly the losses of Q3 areequal to that of Q2 due to the identical circuit operation described earlier. Thetop- and bottom-half of the converter circuit will be manufactured on separateprinted circuit boards, each with their own heat sink. The power losses for thetwo sections are thus not added together.

CASE 2: Negative Inductor Current

For the case where current will ow in order to charge the dc bus, the switcheswill operate dierently. Current will now ow through the diode of Q1 (causingdiode conduction losses) and through the MOSFET of Q2 (causing switchingas well as conduction losses).

First consider the losses in Q2. The switching losses in Q2 are identicalto the switching losses calculated for Q1 in (3.20) in the previous case (seecurrent waveforms in Fig. 3.3). The total switching losses for Q2 are thus also6.66 W.

The MOSFET conduction losses will dier from the previous case since theduty cycle of Q2 is dierent to that of Q1. Equation 3.22 describing the rateof change of the inductor current through Q2 is written as

diLdt

= m =−Vbat

L=

VL(min)

L. (3.29)

The rms current through Q2 is thus



I2Q2(rms) =1

Ts

∫ Ts

0

i2Q2dt

=1

Ts

∫ D2Ts

0

(iL(min) +mt

)2dt

=1

3mTs

[(iL(min) +mD2Ts

)3 − i3L(min)

]= 31.56 A2,

(3.30)

where iL(min) is -8.875 A and D2 is 0.3143. From (3.21) and (3.30) the con-duction loss for Q2 is calculated as 2.37 W resulting in a total power loss of9.03 W for Q2.

From (3.26) the mean current Id2 through the diode of Q1 is 6.857 A atan absolute mean inductor current of 10 A and duty cycle D1. Substitutingthe value for Id2 into (3.25), the diode conduction loss for Q1 is calculated as5.49 W. The total power losses for the top-half of the converter circuit whilstcharging the dc bus are

PT = PD1 + PQ2 = 14.52 W. (3.31)

The total power losses for the bottom-half of the converter circuit will be thesame as for the top-half.

From the two cases the most power is dissipated when current is owingfrom the batteries into the dc bus. The power losses from the operation of theswitches are converted into heat and thus an adequate heat sink is required.The heat sink is designed for the worst case scenario, thus the maximum totalpower of the two cases are used in the heat sink design which is 14.52 W. Therise in junction temperature due to the power dissipated in the MOSFETs anddiodes are given by [11]

∆Tj = PT (Rθjc +Rθcs +Rθsa) , (3.32)

where Rθjc, Rθcs and Rθsa are the junction-to-case, case-to-sink and sink-to-ambient thermal resistances of the MOSFETs. The assumed maximum rise injunction temperature is 50°C. From the datasheet Rθjc and Rθcs are given as0.45°C/W and 0.24°C/W respectively. The sink-to-ambient thermal resistanceis calculated as 2.75°C/W from (3.32). The size of the aluminium heat sinkavailable is 190 mm × 150 mm with a base thickness of 5 mm which givesa sink-to-ambient thermal resistance of 0.37°C/W [32], which is more thanadequate.

3.1.4 Soft-start Circuit

A two-stage soft-start circuit comprising pre- and post-charge mechanisms [33]are used to increase the dc bus voltage gradually to the desired 350 V rail-to-rail



voltage.First consider the top-half of the converter circuit of Fig. 3.1 used to gener-

ate the +175 V bus voltage. Initially the dc bus voltage is at ground potential.Without any soft-start mechanism in place, as soon as the circuit is switchedon, in-rush currents will charge the dc bus to the equivalent battery voltagethrough the MOSFET's freewheeling diodes. The pre-charge circuit shownin Fig. 3.5 is used to limit the battery in-rush current to 5 A by means offour parallel-connected 100 Ω resistors which are placed in series with theconverter's battery. At such time as the bus capacitor C is charged to theequivalent battery potential (≈120 V), the resistors are short-circuited by arelay to eectively remove the resistors from circuit. Table 3.4 show the valuesof the components used in the pre-charge circuit.

LM311R1

VC

D1

VE

D2

C1

R2

+Vdc

R3

VC

Rp

LiL

Half-Bridge

Converter

+Vdc

VbatRg

Q2

VE

Figure 3.5: Pre-charge soft-start circuit implementation.

Table 3.4: Pre-charge soft-start circuit component values.

Component Description ValueVC - 12 VVE - 0 VRp - 25 ΩQb 2N2219A NPN BJT Ic = 0.8 ARg - 10 kΩD1 Zener diode 5.6 VD2 1N4148 switching diode VF = 0.72 VC1 - 10 µFR1 - 1 kΩR2 - 220 kΩR3 - 12 kΩ



The relay action is controlled by an LM311 comparator. A 5.6 V Zener diodeis used as the reference voltage at the non-inverting input of the comparator,as shown in Fig. 3.5. A resistor divider circuit (R2 and R3) is used to scaledown the dc bus voltage to the inverting input of the comparator. Oncethe scaled dc bus voltage exceeds the reference voltage, the inverting outputof the comparator will change to a high state. This allows current to owthrough the LM311's output transistor, thus closing the relay switch to createa short-circuit across the four parallel connected power resistors represented byRp. Capacitor C1 was added to introduce a small time delay in order to avoidany false state changes at the comparator's output during start-up. With thegiven resistor values the relay will trip at a measured dc bus voltage of

Vdct =

(R2 +R3

R3

)Vref = 108.3 V, (3.33)

which is low enough to avoid the relay from tripping while the converter issupplying power to a load, since the load can cause the battery voltage todrop slightly.

As seen in Fig. 3.5 the pre-charge circuit is connected in series between theconverter's batteries and inductor. The rest of the converter circuit remainsunchanged and is shown in Fig. 3.5 as a block diagram. The pre-charge cir-cuit receives power from one of the ten 12 V batteries. To accommodate therequired current to turn the relay switch on and o properly, an additionalNPN BJT was added. Together with the LM311's output BJT they form aDarlington pair [34] where Rg is used to drain the capacitance.

A similar pre-charge circuit is used for the bottom-half of the convertercircuit to gradually charge the dc bus to -120 V. The only dierence is thescaled negative dc bus voltage feeds into the non-inverting input of the com-parator and a negative 5.6 V reference voltage is used at the inverting input.The complete circuit schematic is shown in Appendix A.1.1.

The next stage of the soft-start circuit is used to charge the dc bus from theequivalent battery potential to the respective +175 V and -175 V rails. Thepost-charge mechanism is designed to limit current spikes once the switchesstart switching. To achieve this, the on-times of the switches have to graduallyincrease thus allowing the post-charge mechanism to control the duty-cycle ofthe switches by adjusting the dead-time.

At the instant Q1 is switched o, there is a small but nite time delaybefore switch Q2 is switched on, namely the dead-time. During this timeperiod both switches remain o. The practical implementation of dead-timefor switches Q1 and Q2 are demonstrated in Fig. 3.6. The modulator referencesignal ve (which is generated by the control circuit) is indicated in black andthe triangular carrier waveform vc is indicated in green in Fig. 3.6. If nodead-time were implemented, both switches will have a duty cycle of 50 %. Anoset voltage Voffs is subtracted from ve to generate the modulator reference



Voltage ve1

vcve2ve

Time

Voltage vpwm1

vpwm2

Figure 3.6: Dead-time implementation.

voltage ve1 for switch Q1 and similarly Voffs is added to ve to generate themodulator reference voltage ve2 for Q2.

The on-time of the switches are determined as follows: if ve1 is greater thanvc, Q1 is on and if ve2 is less than vc, Q2 is on. The resulting PWM signalsfor Q1 and Q2 are shown in the bottom graph of Fig. 3.6. The implementeddead-time is seen to have reduced the duty cycles of both switches. Thedead-time is adjusted by changing the magnitude of the oset voltage Voffs.

The post-charge circuit functions by initially setting Voffs to a value largerthan the magnitude of the carrier waveform, thus both switches will have a dutycycle of zero. After the dc bus has reached the equivalent battery potential,the oset voltage is progressively ramped down over a period of approximately10 s to a minimum value, thus limiting the on-time and duty cycles of bothswitches, but allowing them to start switching.

The ramping down of the oset voltage is controlled by a capacitor andresistor circuit as shown in Fig. 3.7 with the component values given in Ta-ble 3.5.

Table 3.5: Post-charge soft-start circuit component values.

Component ValueVRef 5 VC2 470 µFD3 VF = 0.72 VR4 170 kΩR5 1.8 kΩR6 5.6 kΩ



VRef

C2

D3

R4

R5

R6

−

+

LM358N

R5

R6

Voffs

Figure 3.7: Post-charge soft-start circuit implementation.

As the voltage across C2 increases when charged through R5 and R6, Voffs

decreases until the minimum value of 0.44 V is reached. The minimum valuecorresponds to a dead-time of 1 µs and was chosen as such to eliminate anyMOSFET shoot-through currents. Resistor R4 is adjustable to increase ordecrease the dead-time.

3.1.5 Isolated Gate-Drive Circuitry

An isolated gate-drive circuit is employed to communicate the switching signalsgenerated by the converter's control circuit to the gate of each MOSFET.Galvanic isolation between the switches and the control circuit is essentialto prevent damage to the control circuit due to the large voltage excursionsencountered by the MOSFETs.

Each isolated gate-drive circuit comprises an optocoupler [11], a simplepush-pull oscillator circuit (oscillating at approximately 300 kHz), a smalltoroidal transformer (with split primary and secondary windings), and twofast rectier diodes. The oscillator supplies power to the optocoupler via thetransformer and fast rectier diodes as shown in Fig. 3.8, with the correspond-ing component values given in Table 3.6, while the optocoupler communicatesthe switching signals to the gate of a MOSFET.

S1 S2

R1 R1

C1 C1R2

VE

VC

T1

1:1

D1

D1

C2

VSC

VSE

Figure 3.8: Power section of the isolated gate-drive circuit.



Table 3.6: Component values used in oscillator gate-drive circuit.

Component Description ValueVC Battery supply voltage 12 VVE Battery supply voltage 0 VS1 PNP BC556 BJT Ic = 100 mAR1 - 220 ΩC1 - 100 pFR2 - 1 MΩD1 BAT85 Schottky diode IF = 200 mAC2 - 100 µFVSC Isolated supply voltage 12 VVSE Isolated supply voltage 0 V

An EPOS B64290 toroid was wounded with 10 turns of thin enamel copper wireon both sides to construct the transformer T1 with a turns ratio of one-to-one.The TLP250 was used for the optocoupler as it is equipped with under-voltagelockout protection. The characteristics of the TLP250 is given in Table 3.7.

Table 3.7: TLP250 characteristic values.

Parameter Description ValueVCC Supply voltage 10-35 VIO Output current ±1.5 AViso Isolation voltage 2500 Vtp Propagation delay time 150 nsCM Common mode transient immunity 5000 V/ µs

OscillatorPowerCircuit

VSC

VSE

PWMSignal

Rp

Anode

Cathode

TLP250

Vout

RG

RPD

D

Figure 3.9: Block diagram of the MOSFET gate-drive circuit.



Four gate-drive circuits as shown in the block diagram of Fig. 3.9 are required,one for each MOSFET. The value of the resistor Rp was chosen as 220 Ω tolimit the input current to the TLP250 to approximately 15 mA. A pull-downresistor RPD of 4.7 kΩ is used to drain the gate capacitance once the MOSFETswitches o. The gate resistor was chosen as 27 Ω. The maximum outputvoltage of the optocoupler with the described power circuit is 12 V, hence themaximum current the optocoupler is ever required to source is

IO =Vout

Rg

=12

27= 0.44 A. (3.34)

The datasheet of the TLP250 optocoupler species a maximum output currentof 1.5 A. The optocoupler will thus be able to source the above mentionedcurrent to the gate of the MOSFET.

The maximum voltage across any of the MOSFETs is the dc bus voltageof 175 V. With the turn-o time given as 92 ns in the MOSFET datasheetand the turn-on time as 99 ns, the minimum transient immunity required bythe optocoupler is 1902 V/µs. The 5000 V/µs rated transient immunity of theoptocoupler is thus sucient.

A detailed schematic showing the isolated gate drivers, pre-charge soft-startcircuit and complete converter circuit for both positive and negative dc busgeneration can be found in Appendix A.1.1.

3.2 PWM Controller Design

A block diagram of the two identical controllers (one for each half-bridge con-verter) is shown in Fig. 3.10. Two control loops are used; an inner currentcontrol loop which is enclosed by an outer voltage control loop. The controlleris structured such that the inner control loop measures and compares the meaninductor current IL to a set-point voltage vseti generated by the outer controlloop. The set-point voltage corresponds to a current reference where 1 V rep-resents 2 A of current. The output of the voltage controller vrefi is limited tovseti as shown in Fig. 3.10 to eectively limit the average inductor current. Theouter control loop measures and compares the dc bus voltage vdc to a xedset-point Vdc

∗ corresponding to a bus voltage of positive or negative 175 Vrespectively.

The current control loop is responsible for generating the PWM signals thatfeed the gates of the MOSFETs on the converter circuit. The output of thecurrent controller produces an modulator reference signal ve that is used forcomparison with the carrier waveform to generate the required PWM signals.The reference signal is limited as seen in Fig. 3.10 to ensure the amplitude ofthe reference signal never exceeds the amplitude of the carrier waveform. Itthus limits the duty cycle of the switches to a value below 100 %. The PWM



Vdc∗ Σ

+

−vfbv

VoltageController

vrefi

Limiter

vseti

Σ+

−vfbi

CurrentController

Limiter

PlantiL Bus

Plantvdc

CurrentSensor

VoltageSensor

ModulatorCircuitInner Loop

vε ve

Figure 3.10: Block diagram of converter's control circuit.

generation circuit is denoted in Fig. 3.10 as the modulator circuit and will bedescribed in more detail in the subsections that follow.

Frequency domain analysis is employed to design the voltage and currentcontrollers. However, a time domain analysis of the circuit is also requiredto linearise the system and to provide the necessary dierential equations toimplement a time domain simulation of the converter and controller in thenext chapter.

3.2.1 Carrier Waveform Generation

A 40 kHz triangular waveform is chosen as the carrier waveform to generatethe required PWM signals. A 4 MHz crystal-controlled square-wave oscillatoris scaled down to 40 kHz using two Hex D-type ip-ops, ve ip-ops fromeach in order to divide by 100. The resulting square-wave is integrated togenerate a triangular waveform. The dc component is removed (to prevent theintegration of a constant) by capacitively coupling the output of the integratorcircuit to the gain-stage op-amp (an LF353), which is also used to buer theoutput waveform. The circuit outline is shown in Fig. 3.11 and the componentvalues are given in Table 3.8. The triangular waveform at the output has apeak-to-peak value of 11 V.

The integrator is in actual fact a low-pass lter with a low corner frequencyof

fc =1

2πR3C2

= 159.2 Hz, (3.35)

to limit the dc gain while still functioning as an integrator at 40 kHz. Theproblem with using a pure integrator (by removing R3) is without any dcfeedback, the output voltage will tend to drift until the op-amp saturates dueto the op-amp's internal oset and bias currents. By adding R3, dc feedbackis provided and the output voltage is stabilised [35].

The not-gates used are provided by a 74HC14 hex inverting Schmitt trig-ger integrated circuit (IC) package containing 6 inverting buers. Both the



C1 C1

R1

X1

4 MHz

÷ 10

400 kHz

÷ 10

40 kHz

R2

C2R3

−

+

LF353N

R2C3

R3

C2

R4−

+

LF353N

R5

vtri

40 kHz

Figure 3.11: Circuit outline of the triangular carrier waveform generation.

Table 3.8: Triangular waveform generator component values.

Component ValueX1 4 MHzR1 10 MΩC1 22 pFR2 22 kΩR3 1 MΩC2 1 nFC3 100 nFR4 1.2 kΩR5 4.7 kΩ

74HC14 and 74HC174 IC packages require a supply voltage of 5 V.

3.2.2 Controller Plant

For the analysis and design of the controller only the top-half of the convertercircuit is used as shown in Fig. 3.12. The same control circuit is implemented inthe bottom-half of the converter. The plant portion of the converter includesthe current sense resistors used by the current control loop to generate thecurrent feedback measurement and is denoted by Rcs in Fig. 3.12.

With reference to Fig. 3.12 the equation describing the inductor current asa function of the mid-point voltage vm is given by

vm − Vbat − iL (Rin +Rcs) = LdiLdt

. (3.36)



Rin

Vbat

LiL vm

Q2

Q1ic

C

Rcs

+Vdc

idc

Figure 3.12: Bidirectional dc-dc converter circuit used for controller design.

The dierential equation for the inductor current is thus

diLdt

=vm − Vbat − iL (Rin +Rcs)

L, (3.37)

where

vm = s1vdc. (3.38)

The variable s1 dictates the state of switch Q1 where s1 = 1 indicates theswitch is on and s1 = 0 indicates Q1 is o. The mid-point voltage is thus ateither +Vdc or zero depending on the amplitude of the modulator referencevoltage with respect to the carrier waveform. If the reference voltage ve attime t is larger than the carrier waveform vtri, s1 = 1, otherwise s1 = 0.

For frequency domain analysis the eect of the battery voltage is omit-ted since it is considered a constant dc value. Hence, the mean voltage Vm

measured at the mid-point between switches Q1 and Q2 is given by

Vm = (sL+Rin +Rcs)IL, (3.39)

where IL is the mean battery and inductor current. Solving (3.39) the forwardtransfer function of the controller plant Gp(s), describing the mean inductorcurrent as a function of the mid-point voltage, is given by

Gp(s) =ILVm

=1

sL+Rin +Rcs

. (3.40)

3.2.3 Current Control Loop

The current control loop, shown in Fig. 3.13, functions to regulate the meaninductor current owing to and from the batteries by controlling the switchingactions of the MOSFETs. The time-varying modulator reference voltage ve is



compared (by means of a high-speed AD790JN comparator from Analog De-vices) to the triangular waveform described in Section 3.2.1, where the outputof the comparator provides the PWM switching signal.

IL∗

(Vseti)Σ

+

−Vfbi

Gc(s) KR Kdc Gp(s)

H(s)

ILVe D1

Figure 3.13: Current control loop block diagram.

A linear model of the modulator circuit is assumed, where the duty cycle ofthe PWM signal D is calculated as the ratio of the mean modulator referencevoltage Ve to the amplitude of the carrier waveform. Assuming the triangularcarrier waveform has a minimum value of 0 V and a maximum value of VR,the duty cycle D is:

D =Ve

VR

. (3.41)

To account for the linear PWM model constant KR is introduced in Fig. 3.13.From (3.41) the constant KR is expressed as the ratio of the duty cycle to themodulator reference voltage, thus

KR =D1

Ve

=1

VR

, (3.42)

where D1 is the duty cycle of switch Q1. With reference to Fig. 3.12 the meanmid-point voltage Vm is related to the duty cycle (as proven in Section 2.2.2)by

Vm = D1Vdc =Ve

VR

Vdc. (3.43)

For the design of the current controller the dc bus voltage is assumed constant,which is reasonable given that the current control loop is specically designedto respond signicantly faster than the voltage control loop. Constant Kdc isthus 175 V. From (3.43) the mid-point voltage is the duty cycle multiplied byKdc.

Ten parallel connected 0.68 Ω metal lm resistors were used for currentsensing. The feedback voltage Vfbi provided to the inverting input of thesummation in Fig. 3.13, is thus the product of the inductor current IL and thefeedback transfer function H(s). The current-sensing feedback circuit is shownin Fig. 3.14 with the corresponding component values given in Table 3.9.



Rcs

IL

R1R2

R1

−

+

LF353N

Vfbi

R2

Figure 3.14: Inductor current sensing circuit.

Table 3.9: Component values for the current sense circuit.

Component ValueRcs 68 mΩR1 4.7 kΩR2 34.5 kΩ

A dierential signal from the current sense resistors feed an LF353N op-ampthrough resistors to add the required gain. The transfer function H(s) is thusgiven by

H(s) =Vfbi

IL=

R2

R1

Rcs. (3.44)

A gain of 7.34 (R2

R1) is used such that at a maximum current of 10 A the

feedback signal will be 5 V. Similarly in the time domain the current loopfeedback voltage is given by

vfbi =R2

R1

RcsiL. (3.45)

With reference to Fig. 3.13, the open-loop transfer function is

Gol(s) = Gc(s)KRKdcGp(s)H(s), (3.46)

where Gc(s) is the compensation amplier. The frequency domain analysisof Gol(s) without the transfer function of the compensation amplier presentis shown in Fig. 3.15. In adherence with the Nyquist stability criterion, theopen-loop transfer function with compensation is required to have both posi-tive phase and gain margins in order for the closed-loop transfer function tobe stable (not oscillate). The phase margin should, preferably, be at least 30°[36]. Furthermore, the unity gain crossover frequency of the open-loop transferfunction should be chosen according to the desired performance of the system,but is generally designed to be at around one-fth of the system's switchingfrequency or lower [37].



−40

−20

0

20

Magnitude

(dB)

100 101 102 103 104 105−90

−45

0

Frequency (Hz)

Phase

(deg)

Figure 3.15: Bode plot of current controller without compensation.

As seen from Fig. 3.15 the phase margin is positive, the unity crossover fre-quency is at 2.99 kHz and the dc gain is 17.8 dB. The corner frequency is at390 Hz. A compensation amplier will increase the bandwidth as well as thedc gain. Ideally the dc gain should strive to innity thus an additional pole isrequired.

In order to improve the bandwidth as well as the dc gain a PI or pole-zerocompensator [38] is required. As the name suggests, the last mentioned consistsof a pole-zero pair, where the pole and zero are placed to achieve the requiredclosed-loop stability of the system. The pole-zero and PI compensators are verysimilar, the only benet of using a pole-zero compensator is the additional polepresent at high frequencies. This allows a roll-o of -40 dB per decade belowthe 0 dB which helps to improve the ltering of switching noise. A pole-zerocompensation amplier as shown in Fig. 3.16 is chosen as the compensatorGc(s) for the current control loop due to the good transient response and loadregulation that it provides.

The dierential equations describing the pole-zero compensator are derivedby assuming the amplier is an inverting amplier with the non-inverting inputgrounded. The inverting input voltage is dened as vfbi − vseti. From rstprinciples it is known that the currents owing into the amplier inputs sumto zero, thus

vfbi − vsetiR1

+ C1dvedt

+ C2dvc2dt

= 0, (3.47)

where the voltage across capacitor C1 is the reference voltage ve. The voltage



−

+

LF353N

ve

R1vfbi

C1

R2C2

R1

vseti

C1

R2

C2

Figure 3.16: Pole-zero compensation amplier.

across C2 is dened as vc2 and can also be expressed by

vc2 = ve − ic2R2 = ve − C2R2dvc2dt

. (3.48)

Solving the above dierential equation yields

dvc2dt

=ve − vc2C2R2

. (3.49)

Substituting (3.49) into (3.47) and rearranging results in the dierential equa-tion for the modulator reference voltage ve where

dvedt

=vseti − vfbi

C1R1

+vc2 − veR1R2

. (3.50)

Similarly for the frequency domain analysis the transfer function Gc(s) is de-rived below. Firstly,

Zf =

(R2 +

1

sC2

)|| 1

sC1

=

(sC2R2 + 1

sC2

)|| 1

sC1

=1

sC2

sC2R2+1+ sC1

=sC2R2 + 1

s2C1C2R2 + s(C1 + C2),

(3.51)

where Zf is the combined amplier feedback impedance. The transfer functionfor Fig. 3.16 is thus



Gc(s) =Ve

Vseti − Vfbi

=Zf

R1

=sC2R2 + 1

R1 [s2C1C2R2 + s(C1 + C2)],

(3.52)

and in standard form

Gc(s) =sC2R2+1C1+C2

sR1

(sC1C2R2

C1+C2+ 1

)=

1

R1(C1 + C2)

sC2R2 + 1

s(

sC1C2R2

C1+C2+ 1

) .

(3.53)

The dc gain in decibels is

Gcgain = 20log10

[1

sR1(C1 + C2)

]. (3.54)

The two time constants are

τ1 = C2R2, (3.55)

and

τ2 =C1C2R2

C1 + C2

, (3.56)

with corresponding corner frequencies of

f1 =1

2πτ1=

1

2π

(1

C2R2

), (3.57)

and

f2 =1

2πτ2=

1

2π

(C1 + C2

C1C2R2

). (3.58)

As seen from (3.53), the pole-zero compensator has an integrator pole whichwill give the required innite dc gain. The rst corner frequency f1 should beless than or equal to the corner frequency of the open-loop response (390 Hz)shown in Fig. 3.15 in order to increase the bandwidth. The inductor currentripple will impose a ripple voltage on the reference signal Ve. To ensure theripple on the reference voltage is ltered out properly (to produce a constantreference voltage), the desired bandwidth for the current controller is at around



one tenth of the switching frequency, thus at 4 kHz. The second corner fre-quency should be below the 0 dB line thus at a value equal to or higher than4 kHz. Substituting (3.57) into (3.58) gives

f2 =

(C1 + C2

C1

), (3.59)

where the desired corner frequency for f1 is chosen as 100 Hz and for f2 as5 kHz, resulting in a relationship between C1 and C2 of

C2 = 49C1. (3.60)

The value chosen for C1 is 10 nF and by taking the above equation into account,the closest value for C2 is 470 nF. From (3.57) the calculated value of R2 is3.4 kΩ. The bandwidth of the controller will change from 2.99 kHz to 4 kHzby adjusting the gain factor Gcgain. Since the roll-o of the controller is at-20 dB/decade when it crosses the 0 dB line the amount of gain required tochange the controller's bandwidth is calculated as

∆Gcgain = 20log10(4000)− 20log10(2990) = 2.53 dB. (3.61)

From (3.54) and (3.61) the value of R1 is calculated as 3.99 kΩ. After test-ing and simulation some of the values had to be adjusted slightly. The nalcomponent values are given in Table 3.10.

Table 3.10: Component values for the current loop compensator.

Component ValueR1 3.3 kΩR2 4.7 kΩC1 10 nFC2 470 nF

The closed-loop transfer function of the complete current controller shown inFig. 3.13 is

Gcl(s) =ILVseti

=Gc(s)KRKdcGp(s)

1 +Gc(s)KRKdcGp(s)H(s). (3.62)

To ensure the stability of the system with the compensation amplier present,the open-loop response of the current controller is investigated. Fig. 3.17 showsthe Bode plot of both the open- and closed-loop responses. The open-loopresponse shows a phase margin of 53.8 degrees and a unity gain crossoverfrequency of 3.2 kHz. The closed-loop response shows a dc gain of 6.04 dBcorresponding to a static loop sensitivity of 2.0 A of battery current per volt of



excitation applied to the set-point input Vseti. Thus, at an absolute maximumset-point voltage of 5 V, the battery current will rise to 10 A as desired.

−100

−50

0

50

100

Magnitude

(dB)

100 101 102 103 104 105−180

−135

−90

−45

0

Frequency (Hz)

Phase

(deg)

Open-loopClosed-loop

Figure 3.17: Current controller bode plot.

In Fig. 3.17 the gain margin is shown to be innite as the phase plot of theopen-loop response never crosses the -180 degree line. Since an innite gainmargin cannot be realised in practice, a bifurcation test [39] was undertakento determine a more realistic prediction of the gain margin. A gain variableKB was added to the compensation circuit as shown in Fig. 3.18 such that thetransfer function for the compensation amplier changed to KBGc(s).

Vseti Σ+

−Vfbi

Gc(s) KB Kd Gp(s)

H(s)

IL

Compensator

Ve VeB

Figure 3.18: Current control loop with additional gain factor KB.

The gain variable KB was linearly increased from one to 40 in a MATLABSimulink model of the converter circuit and controller. The result of the bi-furcation test is shown in Fig. 3.19. An additional gain of 22 was added to thecompensation circuit, where the output reference voltage VeB feeds the PWM



comparator, before the output voltage Ve of the controller Gc(s) was observedto bifurcate. This indicates a more realistic gain margin of 26.8 dB. A positivegain and phase margin suggest that the current control loop is stable.

0 5 10 15 20 25 30 35−0.5

0

0.5

1

KB

Ve(V)

Figure 3.19: Bifurcation diagram used for stability analysis.

3.2.4 Current and Voltage Limiting Circuit

An active clamp circuit [35] shown as a limiter in Fig. 3.10 is used to limitthe absolute maximum of the mean current demanded from the battery. Thisaction is realised by clamping the range of the set-point current dictated by thevoltage control loop to -10 A and +10 A. The clamp circuit in Fig. 3.20 showsboth positive and negative voltage clamping where the reference voltages canbe made adjustable.

−

+

LF353N

Rlim

Vin

−Vref

−

+

LF353N

+Vref

Vout

Figure 3.20: Postive and negative active clamping circuit.

Since the current control loop has a static loop sensitivity of 2 A per voltof excitation at the set-point input, the values for -Vref and -Vref are set toplus and minus 5 V respectively, to correspond to the current limit of -10 Ato +10 A. The input voltage Vin is the reference set-point vrefi produced bythe voltage control loop while the output voltage Vout is the limited set-pointvoltage vseti for comparison with vfbi. The resistor used for Rlim is 470 Ω andthe two diodes are BAT85 Schottky diodes.

The same circuit was used to limit the output of the compensation amplierGc(s) to -5 V and +5 V so as to clamp the range of the modulator reference



signal. With the triangular waveform at a 5.5 V amplitude (11 V peak topeak) and a maximum reference voltage of +5 V, the maximum duty cycleis limited to 95 %. Similarly the minimum duty cycle is limited to 5 % at aminimum reference signal of -5 V.

3.2.5 Voltage Control Loop

The voltage control loop functions to regulate the dc bus voltage vdc to thecorresponding voltage set-point Vdc

∗. The bus plant portion of the controllerblock diagram shown in Fig. 3.10 contains dc bus capacitors of the convertercircuit. The dc bus voltage is related to the rest of the converter circuitthrough the current owing into the capacitors and the capacitors themselves.The current owing into the capacitor as shown Fig. 3.12 is related to theinductor current by

ic = idc − s1iL, (3.63)

where s1 is again used to determine the state of switch Q1 as either on (s1 = 1)or o (s1 = 0). The current through the capacitor is also dened as

ic = Cdvcdt

= Cdvdcdt

. (3.64)

Combining (3.63) and (3.64) results in the dierential equation describing thedc bus voltage as a function of the inductor current and is given below as

dvdcdt

=idc − s1iL

C. (3.65)

With s1iL averaged over at least 5 to 10 switching cycles, s1iL is approximatelyequal to d1iL, where d1 is the instantaneous duty cycle of switch Q1. Equation(3.65) time averaged over 5-10 switching cycles now becomes

dvdcdt

=idc − d1iL

C. (3.66)

Both the inductor current iL and the duty cycle d1 are time-varying signalsresulting in a non-linear dierential equation for the dc bus voltage. For fre-quency domain analysis transfer functions are required to be linear. Thus(3.66) is linearised before applying the Laplace transform for frequency do-main analysis. A function can be linearised around a certain operating pointusing a rst order Taylor series approximation [40]. The approximation for(3.66) is thus

vdc = f (d1(0), iL(0)) +∂f

∂d1

∣∣∣d1=d1(0)iL=iL(0)

(d1(t)− d1(0))

+∂f

∂iL

∣∣∣d1=d1(0)iL=iL(0)

(iL(t)− iL(0)) ,

(3.67)



and in increment form

d∆vdc(t)

dt=

∂f

∂d1

∣∣∣d1=d1(0)iL=iL(0)

∆d1(t) +∂f

∂iL

∣∣∣d1=d1(0)iL=iL(0)

∆iL(t), (3.68)

where f is the dierential equation dvdcdt

given in (3.66). The operating point ofthe duty cycle d1 is around 0.6857 and denoted as d1(0). The operating pointfor the inductor current iL(0) is calculated as

dvdcdt

= 0 =idc − d1(0)iL(0)

C. (3.69)

Rearranging the above equation:

iL(0) =idc

d1(0). (3.70)

The operating point for the inductor current thus depends on the amountof current owing into the dc bus. Since this value will vary, the frequencyand time domain analysis are conducted at the maximum and minimum meandc bus current variation as well as at a mean dc bus current of zero. Afterevaluating (3.68) the linearised dierential equation for the dc bus voltage is

d∆vdc(t)

dt= −iL(0)

C∆d1(t)−

d1(0)

C∆iL(t). (3.71)

Multiplying both sides with C and taking the Laplace transform of the aboveequation, (3.71) becomes

− sCVdc(s) = Kd0IL(s) +Ki0D1(s), (3.72)

and after simplifying

Vdc(s) =Kd0IL(s) +Ki0D1(s)

−sC= Fp(s) [Kd0IL(s) +Ki0D1(s)] , (3.73)

where Fp(s) is used to dene the dc bus plant portion of the converter.The block diagram of the linearised control system is shown in Fig. 3.21 whereFc(s) denotes the controller for the voltage control loop. The feedback voltageVfbv shown in Fig. 3.21 is a scaled version of the bus voltage, where Ks is thescaling factor. The block diagram in Fig. 3.21 can be manipulated by movingthe branch point at IL(s) to D1(s) as shown in Fig. 3.22. By performing blockdiagram reduction the control system diagram reduces to the diagram shownin Fig. 3.23.

From Fig. 3.23 the open-loop transfer function of the voltage control loopis calculated as

Fol(s) =KsKRFc(s)Gc(s)Fp(s)

1 +KdcKRGc(s)Gp(s)H(s)[Ki0 +KdcKd0Gp(s)] , (3.74)



Vdc∗ Σ

+

−Vfbv

Fc(s)

Vseti

Σ+

−Vfbi

Gc(s) KRD1

Kdc Gp(s)IL

Kd0 Σ++

Fp(s) Vdc(s)

H(s)

Ks

Ki0

Vε

Figure 3.21: Voltage and current control loop block diagram.

Vdc∗ Σ

+

−Vfbv

Fc(s)

Vseti

Σ+

−Vfbi

Gc(s) KR

D1Kdc Gp(s) Kd0 Σ

++

Fp(s) Vdc

KdcH(s)Gp(s)

Ks

Ki0

Vε

Figure 3.22: Simplied voltage and current control loop block diagram.

Vdc∗ Σ

+

−Vfbv

Fc(s)Gc(s)KR

1 +KdcKRGc(s)Gp(s)H(s)Ki0 +KdcKd0Gp(s) Fp(s) Vdc

Ks

Vε

Figure 3.23: Reduced voltage and current control loop block diagram.

and the closed-loop transfer function as

Fcl(s) =Vdc(s)

Vdc∗ =

1Ks

Fol(s)

1 + Fol(s). (3.75)

The measured dc bus voltage is scaled down through a dierential amplierfunctioning as an attenuator as shown in Fig. 3.24 with R1 equal to 238 kΩ andR2 equal to 6.5 kΩ. The equivalent scaling factor denoted K2 in the voltagecontrol loop is the ratio between R2 and R1 which is 1

35. Thus at an ideal

positive dc bus voltage of 175 V, the equivalent feedback voltage vfbv is 5 V.The reference voltage Vdc

∗ is therefore set to 5 V.A 2 kW load is connected to the dc bus rails. The transfer function Fp(s)

given in (3.73), describing the dc bus plant portion of the system, is modelled



VGND

R1R2

+Vdc

R1

−

+

LF353N

vfbv

R2

Figure 3.24: Bus voltage feedback circuit.

with and without the load present to conrm stability throughout. With theload Rdc connected the transfer function changes to

Fp(s) =−Rdc

sCRdc + 1, (3.76)

where the minimum value of the load is 60 Ω. The open-loop frequency re-sponse without the compensation amplier Fc(s) present is shown in Fig. 3.25for the loaded as well as unloaded dc bus condition. The initial dc bus currentis assumed zero, thus from (3.70) the operating point for the inductor currentKi0 is also zero.

−200

−150

−100

−50

0

50

Magnitude

(dB)

10−1 100 101 102 103 104 105−270

−225

−180

−135

−90

−45

0

Frequency (Hz)

Phase

(deg)

UnloadedLoaded

Figure 3.25: Bode plot of the voltage controller without compensation.

As seen from Fig. 3.25 when a 60 Ω load is connected the open-loop responsedoes not have innite gain at dc. A pole-zero compensator is once again chosen



as the compensation method since it will provide an additional pole to achievean innite dc gain and also provide the required additional bandwidth for thevoltage control loop.

The dierence between the set-point voltage Vdc∗ and the scaled bus voltage

Vfbv is Vε, which is the input to the voltage control loop's compensator, Fc(s).The derivation for the two corner frequencies and dc gain component for apole-zero compensator was shown in Section 3.2.3. The rst corner frequencyf1 is chosen to be at 5 Hz which is where the bode plot shown in Fig. 3.25rolls o at -20 dB/decade. The second corner frequency f2 is chosen to be ata frequency of around 10 kHz which will be well below the 0 dB line once thedc gain is added. The bandwidth of the voltage controller should ideally be ataround one tenth of the current control loop's, thus at 320 Hz.

The compensation amplier is identical to the circuit shown in Fig. 3.16where the two inputs are now Vsetv and Vfbv and the output is Vseti. The samedierential equations thus also apply. The component values were calculated ina similar manner to that of the current controller's compensation amplier byusing equations (3.54) through (3.59). The nal component values are given inTable 3.11 with the corner frequencies at 33.8 Hz and 15.95 kHz respectively.

Table 3.11: Component values for the voltage loop compensator.

Component ValueR1 1 kΩR2 100 kΩC1 100 pFC2 47 nF

The bode plots for both the open- and closed-loop frequency responses of thevoltage control loop are shown in Fig. 3.26 at a dc bus current of zero. A dcgain of 30.9 dB is indicated, corresponding to a static loop sensitivity of 35 Vof bus voltage per volt of excitation applied to the set-point input. Thus, ata set-point value of 5 V, the bus voltage will rise to 175 V. A phase-margin,gain-margin and unity gain crossover frequency of 77.6 degrees, 20.8 dB and294 Hz are further indicated, suggesting that the voltage control loop is stableunder the specied conditions. Since a load connected to the dc bus onlyaects the controller at very low frequencies (below 50 Hz) the gain and phasemargins remains the same under no-load conditions.

The stability of the voltage control loop was tested again at the meanminimum and maximum inductor current operating points of ±10 A. Theopen-loop frequency response results are summarised in Table 3.12.

The results show the voltage control loop will remain stable within theinductor current operating range with positive gain and phase margins for all



−200

−150

−100

−50

0

50

100

Magnitude

(dB)

10−1 100 101 102 103 104 105−360

−270

−180

−90

0

Frequency (Hz)

Phase

(deg)

Open-loopClosed-loop

Figure 3.26: Bode plot of voltage controller under load.

Table 3.12: Stability analysis of the voltage control loop at various meaninductor current operating points.

Ki0 10 A 0 A -10 AGain margin 24.2 dB 20.8 dB 17.1 dBPhase margin 81.4° 77.6° 73.7°Unity cross-over 319 Hz 294 Hz 270 Hz

conditions. A complete circuit schematics of the controllers used for both thetop and bottom converter are shown in Appendix A.1.2.

3.3 Summary

The detailed design of the bidirectional dc-dc converter circuit was presentedin this chapter. An overview of the basic circuit operation was given. Thedesign of the dc-dc converter's double control loop control circuit was presentedand the implementation thereof detailed. Both frequency and time domainequations were derived to describe the operation of the circuit. The frequencydomain analysis showed both the inner and outer control loops are stable. Thetime domain analysis is presented in the next chapter along with the measuredresults from the manufactured prototype circuit for comparison purposes.


Chapter 4

DC-DC Converter Simulation and

Test Results

In this chapter the operation of the designed dc-dc converter from the previouschapter is simulated in the time domain. This simulation is used to conrmthe stability of the converter during start-up, as well as to examine the stepresponse of the controller with both current and voltage control loops imple-mented. Various measurements are taken from the manufactured prototypecircuit in order to validate the time domain simulations and to demonstratethe practical operation of the circuit.

Since the simulation of the negative bus voltage is identical to the invertedsimulation of the positive bus voltage, only the top-half of the converter circuit(producing the positive bus voltage +Vdc) was used for simulation purposes.The simulations were implemented in MATLAB and corresponds to a simpleiterative Euler solution of the relevant dierential equations, (3.37), (3.38),(3.49), (3.50) and (3.65) from Chapter 3, that describe the behaviour of thecircuit.

4.1 Test Set-Up

The dc-dc converter test set-up is shown in Fig. 4.1. The printed circuit boards(PCBs) used for the practical implementation of the converter are presented inAppendix B.1. The two power boards responsible for generating the positiveand negative dc bus rails are mounted on two heat sinks as shown in Fig. 4.1.The control board is situated on top of the two heat sinks. A small 12 V fanis mounted on the side of the heat sinks to increase the airow, thus coolingthe heat sinks.

The batteries are located at the bottom of the trolley shown in Fig. 4.1. Thetwo motors on-top of the batteries are used with the inverter circuit and areirrelevant to the measurements taken for this chapter. The circuit is switchedon by the two circuit breakers at the front of the trolley where each circuit

56


CHAPTER 4. DC-DC CONVERTER SIMULATION AND TEST RESULTS 57

Figure 4.1: Converter prototype circuit test set-up.

breaker is connected to the positive and negative point of 10 series connectedbatteries.

The load used during testing is a 60 Ω resistive load comprising 6 seriesconnected 10 Ω resistors to form a resistor bank. Each resistor is rated tohandle 500 W and thus the six series connected resistors can handle a totalpower of 3 kW.

For safety purposes during measurements, the mid-point between the top-and bottom-half of the converter was used as the grounding point for all voltageprobe connections.

4.2 Start-Up Response

The simulated dc-dc converter start-up response showing both the instanta-neous dc bus voltage and inductor current are displayed in Fig. 4.2. Thissimulation includes the modelling of the soft-start circuit as well as the dead-time of the switches. A negative inductor current indicates current owingfrom the batteries into the dc bus to charge the dc bus or power a load, whilea positive inductor current indicates current owing from the dc bus into thebatteries thus charging the batteries.

As seen from Fig. 4.2 the rst stage of the soft-start circuit, the pre-chargecircuit, is active for the rst 350 ms after start-up, during which time thebus voltage rises from zero to the equivalent battery potential of 120 V. Thein-rush current iL charging the dc bus is seen to peak at 4.8 A.



0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

50

100

150

200

v dc(V

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

−4

−2

0

2

Time (s)

i L(A

)

Figure 4.2: Simulated dc bus voltage and inductor current during start-up.

At approximately 1.5 s the second stage of the soft-start circuit is activated,allowing the bus voltage to rise from 120 V to 175 V over the next 0.65 seconds.When the bus voltage reaches 175 V there is a small voltage overshoot of 2 V,which is within the allowed range of 170 V to 180 V. It is thus not necessaryto implement any additional anti-windup scheme [41] to prevent the dc busvoltage from overshooting after reaching its nominal value of 175 V.

The large initial ripple voltage on the dc bus is caused by the post-chargecircuit limiting the on-time of the switches by adjusting the dead-time. Theripple is seen to decrease until it reaches a minimum peak-to-peak value of27 mV once the dead-time has reached the minimum value. At time t = 4.5 sthe dead-time has decreased suciently to allow the controller to functionnormally thus regulating the dc bus voltage to 175 V continuously withoutany signicant voltage ripple. At the same time the inductor current is alsoshown to have reached the designed current ripple of approximately 2.25 Apeak-to-peak.

Fig. 4.3 shows the measured dc bus voltage and inductor current duringstart-up. The magnitude and rate of change of the bus voltage is similar to theresult of the time domain simulation shown in Fig. 4.2. Due to the samplingrate of the oscilloscope used to obtain the measurements (1000 samples overthe chosen time period), the inductor current displayed in Fig. 4.3 is undersampled and thus aliasing occurs. In the 5 s measurement taken for Fig. 4.3the inductor current is time averaged over a period of 5 ms, thus aliases of the



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5−200

−150

−100

−50

0

50

100

150

200

v dc(V

)

Positive RailNegative Rail

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

−4

−2

0

2

Time (s)

i L(A

)

Figure 4.3: Measured dc bus voltage and inductor current during start-up.

inductor current are displayed as opposed to the true instantaneous inductorcurrent. The inductor current ripple under normal operating conditions cantherefore not be seen as in the simulated model.

As predicted, the bus voltage is observed to rise to the equivalent batterypotential within 350 ms of connecting the battery to the converter at whichtime an audible click is heard as the relay short-circuits the soft-start resistors.The battery potential is approximately 125 V per rail section which is slightlyhigher than the simulated potential due to the initial state of charge of thepurchased batteries. Another measurement of the start-up current iL was takenover a 1 s time period to determine a more accurate peak start-up current of4.6 A as shown in Fig. 4.4. The small current spike of 0.6 A at 350 ms occurswhen the relay switch closes.

The bus voltage is subsequently observed to rise to and regulate at 177.2 Vand -177.8 V respectively in Fig. 4.3 over a period of approximately 0.6 s as thedead-time is progressively reduced. The rail-to-rail nominal bus voltage is thus355 V. The positive and negative dc bus voltages peak at 179 V and -180 Vrespectively, according to the oscilloscope measurements. This correspond to avoltage overshoot of approximately 2 V from the regulated voltage as predictedby the time domain simulation. The positive and negative bus voltage areobserved to regulate 2 to 3 V higher than the nominally required value of plus



0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−5−4−3−2−101

Time (s)

i L(A

)

Figure 4.4: Measured inductor current during start-up.

and minus 175 V due to a small inaccuracy in the set-point value Vdc∗. Since

it is still within the allowed operating range, no additional adjustments weremade. After another 2.5 s the ripple on the dc bus voltage is seen to havedecreased signicantly and the mean inductor current is shown to be zero.

4.2.1 Gating Signal Implementation

The voltage waveform generated by the push-pull oscillator used to power theoptocoupler (that communicates the gating signals between the controller andMOSFET gates) is shown in Fig. 4.5. The oscillation frequency is measuredas 311 kHz. The peak-to-peak voltage is approximately 24 V corresponding toa 1:1 transformer ratio when the circuit is powered from a single 12 V battery.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

·10−5

−10

0

10

Time (s)

Voltage

(V)

Figure 4.5: Measured oscillator signal used in gate-drive circuitry.

Both the current and voltage control loops employ integrators in their com-pensation ampliers. This causes the initial modulator reference voltage (gen-



erating the PWM signals) during the start-up sequence to be at a maximum,since the dc bus voltage has not yet reached the nominal value. The dutycycle of the switches are limited to 95 %. With the dead-time included themaximum duty cycle is 92 % and the resulting gating signal generated by thecomparator for Q2 is shown in Fig. 4.6 in blue. The green line shows the signalat the gate of the MOSFET.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−5

0

2

4

6

8

10

12

Time (s)

GatingSignals(V

)

ControllerMOSFET Gate

Figure 4.6: Measured gating signal from the controller and MOSFET gate forQ2 during start-up.

A similar switching signal is seen at the gate of Q3 while switches Q1 and Q4

are o completely due to the added dead-time.

4.3 Step Response

To determine the transient response of the dc-dc converter a step change in theload was implemented in both the simulated and prototype circuit. Fig. 4.7shows the predicted response of both the dc bus voltage and inductor currentto a step change in the load. The application of a 2.1 kW load was simulatedby adjusting the mean dc bus current Idc from 0 A to -6 A in the time domainsimulation. The system is tested for a load capability slightly higher thanthe required 2 kW due to the availability of the 60 Ω dummy load that wasused during testing. At time t = 0.1 s the load step response is implementedresulting in a negative average inductor current of 9.32 A and a negative voltagespike of 1.4 V. After 300 ms the simulated load is disconnected and the meancurrent is seen to return to zero while the dc bus voltage peaks at 176.4 Vbefore settling back to 175 V.

A similar response is seen when a dc current source is instantly appliedto the dc bus at time t = 0.7 s by changing the mean dc current Idc from0 A to 5.8 A (corresponding to 2.03 kW of power delivered to the converter).



0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2173

174

175

176

177

v dc(V

)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

−10

0

10

Time (s)

i L(A

)

Figure 4.7: Simulated step response of dc bus voltage and inductor current.

The voltage briey peaks at 176.3 V and the mean inductor current is shownto be 8.42 A. After 300 ms when the current source is removed, the dc busvoltage falls to 173.7 V before settling back to the nominal dc bus voltage.The inductor current is seen to return to a mean value of zero. Accordingto the time domain simulation the duration of the transient responses areapproximately 30 ms. As seen from Fig. 4.7 the simulated converter providesa good transient response by settling quickly and having a maximum voltageovershoot of less than 1 % of the nominal bus voltage. This simulation alsodemonstrates the bidirectional capability of the converter.

The transient response of the prototype circuit was tested by connectingand disconnecting a 2.1 kW (60 Ω) load to the 355 V nominal dc bus. Themeasurement was taken at the positive dc bus voltage rail by using the ac cou-pled setting on the oscilloscope. As shown in Fig. 4.8 the load was connectedat time t = 0.05 s which caused a brief voltage dip of 1.32 V. The bus voltagesettled back to 177.2 V after 0.5 s at which time the load was disconnectedcausing a voltage spike with an amplitude of 0.92 V. Another 400 ms later thedc bus voltage settled back to the nominal voltage.

The transient response of the simulated and measured step responses com-pare reasonable well. The main dierence being the simulated circuit shows a



0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−1.5

−1

−0.5

0

0.5

1

Time (s)

ACcoupledv d

c(V

)

Figure 4.8: Measured step response of the dc bus voltage under ac coupling.

faster settling time than the measured step response.The test showing the bidirectional capability of the dc-dc converter cir-

cuit will be presented in Chapter 7 as part of the system integration testingsince the asynchronous generator is required to source current to the con-verter. The design and implementation of the inverter circuit connecting tothe asynchronous generator will be discussed in the following chapters.

4.3.1 Inductor Ripple Current

The simulated inductor current ripple is shown in Fig. 4.9 and the measuredinductor current at no-load is shown in Fig. 4.10. The simulation predicts acurrent ripple magnitude of 2.25 A peak, which is 22.5 % of absolute maximummean current that the inductor is intended to conduct at full power (sink orsource). The magnitude of the current ripple is independent of the meancurrent, provided that the bus voltage, battery voltage and inductance of theinductor remain constant. The inductor current duty cycle from Fig. 4.9 isshown to be 68.8 % which is as expected.

The measured inductor current at no-load has a peak-to-peak value of2.06 A which is slightly less than the predicted value mainly due to the higherbattery potential. The leakage inductance in the cables connecting the batter-ies to the rest of the converter circuit, as well as the leakage inductance in thepath through the series connected batteries themselves will add to the totalinductance causing the current ripple to decrease slightly.

The measured inductor current when a 2.1 kW load is connected acrossthe bus rails, is shown in Fig. 4.11. The mean inductor current is -9.59 Acorresponding closely to the predicted value of -9.32 A, where the negativesign indicates the batteries are sourcing instead of sinking current.



0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

−1.5

−1

−0.5

0

0.5

1

1.5

Time (s)

i L(A

)

Figure 4.9: Simulated inductor current.

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

−1.5

−1

−0.5

0

0.5

1

1.5

Time (s)

i L(A

)

Figure 4.10: Measured inductor current without a load connected.

In the converter simulation the peak-to-peak value of the current ripple staysconstant at no-load and full-load conditions since the value of the inductorand battery voltage are assumed constant. From Fig. 4.11 it can be seenthat the measured peak-to-peak current ripple increased to 3.1 A at full-load,compared to the 2.06 A at zero load. This is mainly due to the drop in thetotal battery potential from 247.2 V to 236.6 V when the load is connected.Also there is a marginal decline in the inductance of the inductor, due to thedecreased instantaneous permeability of the inductor core material at greatermagnetisation.

In both cases, the measured current is of triangular form with a duty cycleof approximately 69 % at no-load and a duty cycle of 66 % at full-load, duringwhich time switches Q1 and Q4 are turned on and the inductor current isobserved to increase linearly.

Overall, the time domain simulations and measurements for the dc-dc con-verter correspond very well. The simulation can thus be considered a useful



0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

−12

−11

−10

−9

−8

Time (s)

i L(A

)

Figure 4.11: Measured inductor current with a 2.1 kW load connected to thedc bus rails.

tool for predicting the behaviour of the prototype circuit.

4.3.2 Gating Signals

The measured controller gating signals for switches Q1 and Q2 under no-loadare presented in Fig. 4.12. The switches are seen to never be on simultaneouslyindicating the dead-time of 1 µs was implemented correctly. The duty cycleof switch Q1 is 69.2 % and 22.7 % for Q2.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

·10−4

0

1

2

3

4

5

Time (s)

GatingSignals(V

)

Q1

Q2

Figure 4.12: Measured controller gating signals for Q1 and Q2 under steady-state no-load conditions.



4.4 Eciency

A 60 Ω resistor bank was employed to load the converter to approximately2.1 kW. The converter eciency is determined by comparing the power deliv-ered to the load to that drawn from the battery. The measured instantaneousinductor current and ac coupled battery voltage are shown in Fig. 4.13. Themean battery voltage was measured using a multimeter as 236.6 V. The instan-taneous input power is also shown in Fig. 4.13 and was obtained by multiplyingthe magnitude of the inductor current with the battery voltage (after addingthe dc oset of 236.6 V), using MATLAB.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

·10−4

−12

−11

−10

−9

−8

i L(A

)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

·10−4

−4

−2

0

2

4

v bat(V

)ac

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

·10−4

1.82

2.22.42.62.8

·103

Time (s)

p in(W

)

Figure 4.13: Measured inductor current and ac coupled battery voltage underload.

From Fig. 4.13 the measured ac coupled battery voltage is seen to be in phasewith the measured inductor current. Since there is no phase shift between thebattery voltage and inductor current, the average inductor and battery voltagecan be used to calculate the average input power. With the average inductor



current measured with a LEM current probe as 9.592 A, the average inputpower is thus

Pin = VbatIL = 2269 W. (4.1)

The mean value of the instantaneous input power pin shown in Fig. 4.13 wascalculated in MATLAB as 2268.6 W conrming the average power calculationof (4.1).

The regulated dc bus voltage was measured with another multimeter as355 V rail-to-rail and the dc bus current owing into the load was measuredwith the LEM current probe as 6.01 A. The output power at the load is thus

Pout = VdcIdc = 2133 W, (4.2)

resulting in a converter eciency of

η =Pout

Pin

= 94.02%. (4.3)

The total power loss is calculated as

Ploss = Pin − Pout = 136 W. (4.4)

The total switching and conduction losses were calculated as 14.33 W in (3.28)for one half-bridge converter, thus 28.66 W for the complete converter circuit.The current sense resistors of 68 mΩ is responsible for a power loss of 6.3 Wat a mean inductor current of 9.6 A. The remaining power loss of a 101 W ismainly due to the battery's internal resistance, the inductor's equivalent seriesresistance and the resistance within the (long) cables connecting the batteriesto the dc-dc converter circuit.

4.5 Summary

The time domain simulation of the dc-dc converter circuit was presented in thischapter along with the measured test results. The test set-up was describedin detail. The simulated start-up response of the dc-dc converter comparedextremely well to the measured start-up response. The transient response ofthe prototype circuit was tested by implementing a step change in the loadconnected to the converter's dc bus terminals. The simulated and measuredtransient responses compared reasonable well. The dc-dc converter circuitdemonstrated its ability to regulate the dc bus voltage under no-load andloaded conditions, whilst meeting the design specications. The prototypecircuit showed a high eciency and overall satisfactory performance.


Chapter 5

Asynchronous Machine Modelling

An asynchronous machine is used as the generator that connects to the invertercircuit functioning in rectier mode. A model of the asynchronous machine isrequired in order to design the controller for the inverter and generator. Thischapter derives all the necessary machine parameters for a computer simulatedmachine model. The machine model is demonstrated and compared with thetrue machine characteristics.

5.1 Machine Parameter Estimation

The asynchronous machine used is a 3 kW three-phase squirrel-cage rotorinduction motor. The motor will however be operated as a generator. Theequivalent circuit for an asynchronous machine (also known as an inductionmachine) was described in detail in the literature review Section 2.4.2. Theequivalent per-phase circuit diagram is repeated here as shown in Fig. 5.1 forconvenience.

−Vs

+

Rs

Is

jXls jXlr

Ir

Rr

Rr

s(1− s)jXmRc

Figure 5.1: Per-phase equivalent circuit of an induction machine.

The equivalent circuit parameters can be obtained by measurements, no-loadtesting and a locked-rotor test. The datasheet provides most of the no-load andlocked-rotor measurements required for the parameter estimation calculations.Table 5.1 provides a summary of the machine characteristics, as given in thedatasheet.

68


CHAPTER 5. ASYNCHRONOUS MACHINE MODELLING 69

Table 5.1: Three phase induction machine characteristic values.

Parameter Rated ValueShaft power 3 kWFrequency 50 HzPoles 2Slip 4.33 %Voltage 230/400 V (ac rms)Current 10.6/6.07 ALocked rotor current 70.7/40.7 ANo-load current 4.87/2.8 AFull load torque 9.99 NmLocked rotor torque 230 %Breakdown torque 280 %

Due to the available bus voltage of ±175 V provided by the dc-dc converter,the induction machine will be connected in delta (low-voltage conguration).The machine slip is denoted by a small letter s for the duration of this chapter.

5.1.1 Stator Resistance

The stator resistance Rs shown in Fig. 5.1 was measured with a multimeteras 2.1 Ω by measuring the resistance between one of the stator terminals andneutral, while the machine was connected in wye conguration.

5.1.2 Leakage Reactance

The leakage reactances Xls and Xlr shown in Fig. 5.1 are usually calculatedas one entity Xe and approximated by

Xls = 0.4 Xe, (5.1)

and

Xlr = 0.6 Xe, (5.2)

for a class B motor [26] such as the motor used for this project. An approximatemodel of the per-phase equivalent circuit [27] of an induction machine is usedto determine the leakage reactances as shown in Fig. 5.2. The approximation isvalid since the core resistance Rc and impedance of the magnetising inductanceXm are much larger than the stator leakage impedance Rs + jXls.

The leakage reactances are calculated from the expression for breakdowntorque which is derived below. First consider the expression for the real powerdeveloped at the shaft of the machine as given in (2.32) and repeated here:



−Vs

+ Is

Rs jXls jXlr

Ir

Rr

Rr

s(1− s)jXmRc

Figure 5.2: Approximate per-phase equivalent circuit of an induction machine.

Pd = 3Ir2Rr

(1− s

s

). (5.3)

The rotor current Ir is calculated as

Ir =Vs

Re + jXe +Rr(1−s)

s

, (5.4)

where

Re = Rs +Rr. (5.5)

Substituting (5.4) into (5.3) results in

Pd =3V 2

s Rr(1−s)

s

R2e +X2

e +[Rr

(1−s)s

]2+ 2ReRr

(1−s)s

. (5.6)

The torque is related to power by the synchronous angular velocity ωs as givenin (2.33) which results in a developed shaft torque of

Td =1

ωs

3V 2s

Rr

s

R2e +X2

e +[Rr

(1−s)s

]2+ 2ReRr

(1−s)s

. (5.7)

As seen from (5.7) the maximum torque, also known as the breakdown torque,occurs when 1−s

sis at a minimum. The breakdown slip sb is obtained by

dierentiating (5.7) with respect to s and setting it equal to zero which resultsin

sb =Rr√

R2s +X2

e

. (5.8)

The expression for the breakdown torque Tdm is calculated by substituting(5.8) into (5.7) resulting in

Tdm =3V 2

s

2ωs

[1

Rs +√R2

s +X2e

]. (5.9)



From (5.9), the measured stator resistance and the values given in Table 5.1,the combined leakage reactance Xe is calculated as 6.60 Ω. The individualleakage reactances are calculated from (5.1) and (5.2) as Xls = 2.64 Ω andXlr = 3.96 Ω respectively.

5.1.3 Rotor Resistance

The rotor resistance Rr (referred from the rotor to the stator) is calculatedfrom the developed power expression given in (5.6) as 1.96 Ω.

5.1.4 Magnetising Reactance

The magnetising reactance Xm is calculated from the no-load test. At no-loadthe slip is almost zero and hence the impedance of the rotor is almost innite.Fig. 5.2 thus reduces to Fig. 5.3.

−Vs

+ IsjXmRc

Figure 5.3: Reduced equivalent circuit of an induction machine under no-load.

The magnetising reactance is given by

Xm =V 2nl

Qnl

, (5.10)

where

Qnl = VnlInlsin(θpf ). (5.11)

The no-load current is given in the datasheet as 2.8 A and the no-load voltageis the same as the rated voltage, 230 V. The power factor at no-load is givenin the datasheet as 0.15. The power factor angle at no-load is thus

θpf = cos−1(0.15) = 81.37 (5.12)

Substituting (5.11) and (5.12) into (5.10) results in

Xm =Vnl

Inlsin(θpf )= 83.08 Ω. (5.13)



5.1.5 Core Resistance

The core resistance Rc is calculated in a similar manner as the magnetisinginductance. With reference to Fig. 5.3 the core resistance is

Rc =V 2nl

Pnl

, (5.14)

where

Pnl = VnlInlcos(θpf ). (5.15)

The resulting core resistance Rc is calculated as 547.6 Ω. The calculatedmachine parameters are summarised in Table 5.2

Table 5.2: Calculated machine parameters.

Parameter ValueRs 2.1 ΩXls 2.64 ΩXlr 3.96 ΩRr 1.96 ΩXm 83.08 ΩRc 547.6 Ω

5.2 Machine Characteristics

The characteristic curves related to slip are given in the machine datasheet andare used to determine the accuracy of the machine model. Since the machineis rated to operate at 50 Hz all the machine data given in the datasheet is at astator frequency of 50 Hz. The voltage applied to stator phases are consideredto have a constant rms value of 230 V.

5.2.1 Torque-Speed Relationship

The modelled and measured datasheet torque-speed curves are shown in Fig. 5.4.From the datasheet curve, the rotor speed is given as a percentage of the ratedspeed (50 Hz, 3000 rpm), thus the developed torque is given for slip valuesranging from 0 to 1. If the rotor speed is equal to the rated stator speed thenthe slip is 0, and if the rotor speed is zero the slip is 1. The modelled torquecurve was produced by simulating the developed torque as given in (5.7) forslip values also ranging from 0 to 1.



0 10 20 30 40 50 60 70 80 90 1000

0.5

1

1.5

2

2.5

3

Speed relative to rated speed (%)

Torquerelative

toratedtorque

ModelDatasheet

Figure 5.4: Torque vs rated speed characteristic curve.

To achieve the modelled curve of Fig. 5.4 the rotor resistance was changedfrom the calculated value of 1.96 Ω to 1.86 Ω, and the magnetising inductancewas slightly reduced to 80 Ω. As seen from Fig. 5.4 the modelled curve onlyresembles the curve given in the datasheet from 0 % slip to 25 % slip. Theequivalent model is thus not able to predict an accurate torque response forslip values greater than 25 %, at which point the breakdown torque is reached.Since the induction machine will never operate continuously at slip valuesgreater than a few percent, the model need only be accurate for slip valuesranging from 0 % to approximately 6 %. The rated machine slip is 4.33 % andthus the machine will not operate at more than one or two percent slip abovethe rated slip continuously.

The torque-speed curve shown is for motor operation where power is de-livered to the shaft. Since the induction machine will be used as a generator,the machine will be modelled using negative slip values.

5.2.2 Current-Speed Relationship

Similarly the stator current related to the rated speed is shown in Fig. 5.5for both the modelled and measured (from the datasheet) case. The modelledstator current was calculated from Fig. 5.1 as

Is =

∣∣∣∣ Vs

Zeq

∣∣∣∣ , (5.16)

where



Zeq = Rs + jXls +Rc||jXm||(jXlr +

Rr

s

)= Rs + jXls +

RcjXm

(jXlr +

Rr

s

)RcjXm + (Rc + jXm)

(jXlr +

Rr

s

) . (5.17)

0 10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

6

7

Speed relative to rated speed (%)

Current

relative

toratedcurrent

ModelDatasheet

Figure 5.5: Stator current vs rated speed characteristic curve.

The modelled current is seen to deviate signicantly more from the measuredcurrent for slip values greater than 6 %. For small slip values the model doeshowever correspond to the current given in the datasheet curve.

Since the measured current and torque curves deviate from the modelledcurves, it is clear that the values of the machine parameters also change atdierent slip values. The locked-rotor test for instance is only performed for afew seconds during which time the machine heats up signicantly. A change intemperature is known to change the eective resistance. The rotor resistancemay vary 50 % up to a 100 % from the nominal value at rated slip due toheating [42]. The magnetising inductance will vary due to ux saturationat high slip values. The leakage reactances change as the stator and rotorcurrents change due to the non-linear behaviour of magnetic materials at highereld-intensity values (which is directly related to current) [43].

The equivalent circuit parameters determined in this chapter are thus ad-equate to predict the behaviour of the chosen induction machine at very lowslip values (less than 6 % slip).



5.3 Dynamic Machine Model

The dynamic d-q model of an asynchronous (or induction) machine was al-ready discussed in Section 2.4.3. This model, consisting of equations (2.38) to(2.47), is used to model the dynamic behaviour of the 3 kW induction machinedescribed in this chapter at low slip values. The nal machine parameters usedfor modelling are summarised in Table 5.3. The core resistance Rc is not takeninto account for this model.

Table 5.3: Machine parameters used for modelling.

Parameter ValueRs 2.1 ΩXls 2.64 ΩXlr 3.96 ΩRr 1.86 ΩXm 80 Ω

Negative slip values are used to simulate generator operation. The machinemodel was programmed in a MATLAB script where the dierential equationswere solved using the iterative Euler method.

5.3.1 Modelling Results

The simulation was tested at a slip of zero to conrm the behaviour of thedynamic machine model. At a slip of zero the no-load current is given as 2.8 Ain the datasheet and thus a similar value is expected for the model. Threesinusoidal 50 Hz, 230 V rms voltages phase shifted by 120° from each otherwere applied to the dynamic model and the simulation results are shown inFig. 5.6.

The stator voltages were programmed to increase linearly over a time periodof 0.16 s before reaching a nominal value of 230 V rms. Although this didreduce current surges during start-up, to avoid any overcurrent conditionsaltogether, the stator voltages have to increase linearly over a time period ofapproximately 2 s. Once the current settled it reached a steady-state valueof 2.78 A rms which is close to the true no-load current of 2.8 A. Understeady-state no-load conditions the model showed a developed torque of zeroas expected.

Given that the generator will operate at a slip value of around -5 %, anothersimulation was conducted to conrm the generator operation of the dynamicmodel. The resulting stator and rotor currents for one of the three phasesare shown in Fig. 5.7. The rotor shaft was modelled to rotate at a constantangular velocity of 50 Hz.



0 2 4 6 8 10 12 14 16 18 20

·10−2

−400

−200

0

200

400

v s(V

)

0 2 4 6 8 10 12 14 16 18 20

·10−2

−10

−5

0

5

10

Time (s)

i s(A

)

Figure 5.6: Three-phase stator voltages and currents at zero slip.

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

−10

0

10

Time (s)

Current

(A)

isir

Figure 5.7: Stator and rotor currents at -5 % slip.

The stator current is shown to have a frequency of 47.62 Hz while the ro-tor current has a frequency of 2.38 Hz corresponding to a slip of 5 %. Thedeveloped torque of the machine is -15.27 Nm according to the simulation,indicating that 15.27 Nm of torque must be applied to the shaft in order toachieve -5 % slip operation.



5.4 Summary

This chapter derived the asynchronous generator machine parameters fromthe equivalent machine model and datasheet information. The machine modelwas simulated and the results compared to the given datasheet information toconrm the credibility of the model. The model was shown to be reasonablyaccurate for low slip values. The generator operation of the machine was alsoinvestigated. The next chapter contains the design of the inverter controlcircuit which is based on the machine parameters and performance detailed inthis chapter.


Chapter 6

Inverter Design and

Implementation

The design and implementation of a non-isolated bidirectional current-controlledswitched-mode inverter functioning as a synchronous rectier is described inthis chapter. The inverter connects to the dc bus provided by the dc-dc con-verter presented in Chapters 3 and 4. The asynchronous generator describedin Chapter 5 is used to supply power to the dc bus through the inverter circuit.

The generator is required to supply a maximum of 2 kW of electrical powerto a load connected between the dc bus rails, or if a load is not present, tothe dc-dc converter in order to charge the converter's batteries. The voltagesapplied to the generator stator terminals are controlled as a function of thedc bus current and the dc-dc converter's battery voltage. Two control loopsare used to facilitate the regulation of the battery voltage. The design ofthe control loops are presented along with their closed-loop stability analysis.The design and implementation of various additional safety features are alsodescribed.

6.1 Basic Circuit Operation

The inverter circuit is used to regulate the dc-dc converter battery voltage toensure the batteries are kept at their optimal oating use voltage of 13.6 V each.The positive and negative dc-dc converter bus rails, +Vdc and −Vdc, connectto the inverter terminals. The complete circuit diagram of the inverter circuitconnected to the already designed dc-dc converter circuit is shown in Fig. 6.1.

The inverter circuit is based on the commonly used three-phase half-bridgetopology, as shown in Fig. 6.1, with freewheeling diodes connected across theswitches. The current is assumed to ow into the dc bus thus indicatingthe three-phase machine is operating as a generator and the inverter as asynchronous rectier.

The dc bus terminals of the inverter and converter are connected together

78


CHAPTER 6. INVERTER DESIGN AND IMPLEMENTATION 79

Rin

Vbat

LiL vm

Q2

Q1

C

+Vdc

Rin

Vbat

LiLvm

Q3

Q4

C

−Vdc

Load

Io

idc

Ci

S1

is1

id1

S2

vu

is2

id2

S3

is3

id3

S4

vviv

ib vb

is4

id4

S5

is5

id5

S6

vwiw

iu

is6

id6

ic

vciava

3-PhaseMachine

Figure 6.1: Bidirectional converter and inverter interface circuit.

by means of multi-strand wires. The wires are about 1 m long. A load can alsobe connected to the dc bus if desired. A 100 µF 400 V electrolytic capacitor isconnected in parallel with a 100 nF 400 V ceramic capacitor and the combinedcapacitance is denoted Ci in Fig 6.1. The capacitors are connected betweenthe dc bus rails on the inverter side to lter any possible high-frequency noisedue to the inductance of the wire connection.

The dc-dc converter regulates the dc bus voltage to 355 V rail-to-rail. Thepositive denoted dc bus current idc is regulated and limited to a maximummean value of 5.7 A by the inverter's control circuit. This permits a powertransfer of up to 2023 W from the generator to the nominal 355 V dc bus,thus meeting the power requirement of 2 kW. Since the speed of the generatorshaft varies, as would be the case with an air-driven turbine generator, themaximum electrical power that can be drawn from the generator is dictatedby the mechanical power applied to the generator shaft at a given shaft speed.The current in the generator windings should never exceed the rated generatorcurrent, regardless of the generator shaft speed.

The magnitude and frequency of the fundamental voltages (vuf , vvf andvwf ) applied to the generator stator terminals are controlled to maintain aconstant Volt/Hertz ratio. Note all subscripts ending with an f indicate thefundamental component of said waveform. A constant Volt/Hertz ratio corre-sponds to a constant rms ux within the machine, since ux is proportional tovoltage integrated with respect to time. If constant ux is not maintained, themagnetic core of the machine will saturate causing large saturation currents



to ow which can damage the machine.The voltages applied to the generator stator terminals, vu, vv and vw, are

produced by the inverter circuit. An IGBT module containing six IGBTswith freewheeling diodes included, are used for switches S1 through S6. Thegeneration of the PWM signals controlling the six switches are shown in Fig. 6.2in block diagram form.

MPSignal

Processing

ωr

ControllerSignal

vcs

dsPIC DACvref

PWMSignal

vr

20 kHz

Figure 6.2: PWM signal generation block diagram.

The control circuit of the inverter produces three sinusoidal modulator refer-ence voltages, denoted vref in Fig. 6.2, each separated 120 degrees from eachother with equal magnitude. The control circuit includes a dsPIC digital signalcontroller and a digital-to-analog converter (DAC) to generate these referencevoltages as shown in Fig. 6.2.

The speed at which the generator shaft is rotating ωr is measured using amagnetic pick-up. The output signal from the magnetic pick-up, denoted MPin Fig. 6.2, is processed and given as an input to the dsPIC. The generatoris designed to function at a constant negative slip of -5.47 % and thus thefrequencies of the modulator reference voltages are approximately 5 % lowerthan the measured shaft speed.

The amplitudes of the modulator reference voltages are dependent uponthe analog control signal vcs, feeding into the dsPIC as shown in Fig. 6.2, aswell as the speed of the generator shaft ωr. The control signal vcs is generatedby the compensation amplier located inside the inverter's inner control loopand is described in more detail in the next section. The amplitudes of thereference voltages are scaled according to the magnitude of vcs and the speedinput ωr in order to maintain constant rms ux within the generator.

The modulator reference voltages are compared to a triangular carrierwaveform vr with a chosen frequency fs of 20 kHz to generate the PWMswitching signals as shown in Fig. 6.2. The top and bottom switches of each ofthe three half-bridge legs switch complementary to each other. With referenceto Fig. 6.1, when one of the top switches S1, S3 or S5 is switched on, the re-spective pole voltage is pulled high to +Vdc. Similarly, when one of the bottomswitches S2, S4 or S6 is switched on, the respective pole voltage is pulled lowto -Vdc.



0 12π π 3

2π 2π

−5

0

5

v ru(V

),v r

(V)

0 12π π 3

2π 2π

−200

−100

0

100

200

v u(V

),v u

f(V

)

0 12π π 3

2π 2π

−10

0

10

ωs1t (rad)

i uf(A

)

Figure 6.3: Inverter phase voltage and current for one half-bridge circuit.

Figure 6.3 illustrates the operation of the inverter circuit for the half-bridgewith the pole voltage vu. It should be noted that the triangular carrier wave-form vr shown in green in Fig. 6.3 has a frequency 2 kHz instead of the designed20 kHz frequency simply to allow a more detailed viewing of the circuit oper-ation in which the switching action can clearly be seen. The rst plot showsthe corresponding modulator reference voltage vru generated by the controlcircuitry and is dened as

vru = Vc cos(ωs1t), (6.1)

where Vc is the dsPIC scaled amplitude of the modulator reference voltageand ωs1 is the angular frequency of the modulator reference voltage. The timeperiod for one complete angular rotation of 2π is dened as T1. The angularfrequency ws1, and thus also the time period T1, will vary due to the variablespeed of the generator shaft. The reference voltage vru is thus used to modulatethe phase voltage vu and the amplitude modulation index ma is given by [11]



ma =Vc

Vr

, (6.2)

where Vr is the amplitude of the triangular carrier waveform vr. The carrierwaveform is generated in an identical manner to the carrier waveform used inthe converter control circuit detailed in Section 3.2.1. The only dierence isa 2 MHz crystal (instead of a 4 MHz crystal) is used to produce the 20 kHztriangular switching signal. The peak-to-peak output voltage of the triangularwaveform vr is 12 V, thus Vr equals 6 V. The amplitude Vc of each of the mod-ulator reference voltages is limited to 5 V resulting in a maximum modulationindex of

ma =Vc

Vr

=5

6= 0.833. (6.3)

The second plot in Fig. 6.3 shows the modulated phase voltage vu in blueand the fundamental component vuf of the voltage in red. No lter is addedbetween the inverter pole points and the stator terminals; hence the modulatedphase voltages are applied directly to the generator stator terminals. Theinduction machine does not require ltered voltages at its stator terminalssince the internal machine inductance is very high and thus the machine actsas a lter in itself. This property is described in more detail in the nextsubsection.

In Fig. 6.3 the fundamental phase voltage vuf is shown to be in phasewith the modulator reference signal vru. The amplitude Vp of the fundamentalwaveform vuf is thus related to the modulation index by

Vp = ma

Vdc(pp)

2, (6.4)

where Vdc(pp) is the peak-to-peak dc bus voltage of 355 V. The waveform vufis thus given by

vuf = Vp cos(ωs1t). (6.5)

The third plot in Fig. 6.3 shows the fundamental component iuf of the phasecurrent iu to demonstrate the phase shift between the fundamental phase volt-age vuf and current iuf . This phase shift is due primarily to the inductanceof the generator and is calculated from the impedance of the generator. Withthe generator parameters determined in the previous chapter, the impedanceZeq between two stator terminals is calculated using (5.17) as

Zeq = 31.46 6 143.62 Ω, (6.6)

at an angular frequency of 50 Hz. The fundamental phase voltage vuf isused as the reference waveform. With reference to (6.6) and with the phasecurrents dened as positive when owing out of generator and into the dc



bus, the current is calculated as leading the reference voltage by φ = 36.38°.The amplitude of the fundamental phase current is dened as Ip, hence thefundamental phase current iuf is given by

iuf = Ip cos(ωs1t+ φ). (6.7)

The corresponding currents through switches S1 and S2 are shown in Fig. 6.4with reference to Fig. 6.1 and Fig. 6.3, where current is dened as positive whenowing from the generator into the dc bus. During the positive half-cycle ofiuf shown in Fig. 6.3 and while switch S2 is o, current will ow from thegenerator through the forward biased diode of S1 towards the dc bus. Whenswitch S2 is on current will ow through the IGBT of S2 as shown in Fig 6.4.

0 12π π 3

2π 2π

0

5

10

15

i d1(A

)

0 12π π 3

2π 2π

0

5

10

15

i s2(A

)

0 12π π 3

2π 2π

0

5

10

15

i d2(A

)

0 12π π 3

2π 2π

0

5

10

15

ωs1t (rad)

i s1(A

)

Figure 6.4: Switch and diode currents for S1 and S2 over a single angularrotation.

During the negative half-cycle of iuf current will ow from the dc bus towardsthe generator through the IGBT of S1 as long as switch S1 is on. However,



when switch S1 is o and iuf is still within the negative half-cycle, current willow through the forward biased diode of S2.

The time-varying duty cycle of switch S1 is related to the modulation indexgiven in (6.2) and the modulator reference voltage vru dened in (6.1) suchthat [31]

d1 =1

2[1 +ma cos(ωs1t)] . (6.8)

The duty cycle d1 is thus out of phase with iuf as seen from Fig. 6.4. Theinstantaneous positive current owing into the dc bus, as shown in Fig. 6.1, isa function of the current through the diodes and IGBTs of either the top orbottom three switches where

idc = (id1 + id3 + id5)− (is1 + is3 + is5)

= −(id2 + id4 + id6) + (is2 + is4 + is6).(6.9)

0 13π 2

3π π

0

5

10

15

ωs1t (rad)

i dc(A

)

Figure 6.5: Instantaneous and average dc bus current.

Figure. 6.5 shows the instantaneous dc bus current in blue and the average dcbus current Idc in red. The dc bus voltage is regulated to a constant 355 V andthe dc bus capacitors labelled C in Fig. 6.1 remain charged, hence the currentowing into the capacitors (at equilibrium) has a mean value of 0 A (onlythe ripple component of the instantaneous dc bus current will ow into thecapacitors). At the maximum average dc bus current of 5.7 A, the rms valueof the ripple component was calculated in MATLAB as 5.07 A. The maximumcombined rms current the capacitance C is rated to is 9.7 A as stated in the dcbus capacitance design of Section 3.1.2. The maximum combined rms ripplecomponent of the dc bus current from both the converter and inverter circuit,at equilibrium, equals 9.61 A and is thus within the allowed operating rangeof the capacitors.



6.1.1 Generator Voltage and Current

The inverter phase voltages vu, vv and vw, shown in Fig. 6.1, are applied tothe respective generator stator terminals. The induction generator is howeverconnected in delta conguration, thus the line-to-line voltages applied acrosseach of the three generator phases, as shown in Fig. 6.1, are given by

va = vu − vv, (6.10)

vb = vv − vw, (6.11)

and

vc = vw − vu. (6.12)

0 12π π 3

2π 2π

−200

−100

0

100

200

v u(V

)

0 12π π 3

2π 2π

−200

−100

0

100

200

v v(V

)

0 12π π 3

2π 2π

−400

−200

0

200

400

ωs1t (rad)

v a(V

)

Figure 6.6: Instantaneous and fundamental line and phase voltages.

The two inverter phase voltages vu and vv are shown in Fig. 6.6 in blue, alongwith the resulting line voltage va. The fundamental component of each wave-form is also indicated in green. The applied line voltages cause induced linecurrents to ow and are calculated using



ILL =VLL

Zeq

, (6.13)

where ILL and VLL denote the respective phasor line currents and voltagesof the generator as shown in Fig. 6.1. The equivalent generator impedanceZeq is given in (6.6). The amplitudes of the line currents, and thus also theamplitudes of the inverter phase currents, will remain fairly constant with achange in angular frequency since both voltage and impedance change withrespect to frequency. However, at low angular frequencies the relationshipdoes not hold and current is seen to decrease with frequency and voltage.

The generator inductance as seen at the stator terminals is approximatedas the sum of the two leakage inductances, Lls and Llr. The approximation isvalid since the magnetising inductance Lm, connected in parallel with the rotorleakage inductance Llr, is 20 times larger than the rotor leakage inductanceand will thus have a negligible eect on the total generator inductance as seenfrom the stator terminals. The approximate generator inductance Lg is thuscalculated from the machine parameters, derived in Chapter 5, as

Lg =Xls +Xls

ωs0

=6.6

2π50= 21 mH, (6.14)

where ωs0 is the rated angular generator velocity. The inductance is seen tobe very large. Since current is equal to the time integral of the applied volt-age divided by the inductance, the generator will produce a sinusoidal phasecurrent with a small ripple component as shown in Fig 6.7. From simulation,the maximum current ripple is observed to occur when the duty cycle is 50 %,and has a peak-to-peak value of 0.155 A at a switching frequency of 20 kHz.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

·10−2

−10

−5

0

5

10

Time (s)

i a(A

)

Detail at t=7ms

Figure 6.7: Instantaneous line current.



From the line currents the equivalent inverter phase currents shown in Fig. 6.1are calculated as

iu = ic − ia, (6.15)

iv = ia − ib, (6.16)

and

iw = ib − ic. (6.17)

The amplitudes of the fundamental phase currents are√3 times larger than

that of the fundamental line currents and lags the line currents by 30 degrees.The inverter phase current ripple will thus also increase by

√3 to a peak-to-

peak value of 0.22 A. The currents through the switches and diodes do in facthave a small ripple component, but this is negligible for the purpose of losscalculations.

6.1.2 IGBT Power Loss and Heat Sink Design

The IGBT module used is the FS30R06W1E3 module from Inneon. Table 6.1shows the characteristic values of the chosen IGBT module.

Table 6.1: FS30R06W1E3 IGBT module parameter values.

Parameter Description ValueVCES Maximum collector-emitter voltage 600 VICnom Maximum continuous dc collector current 30 AICRM Maximum repetitive peak collector current 60 AVGES Maximum gate-emitter peak voltage ±20 VVCE(on) Collector-emitter saturation voltage 1.25 Vton Turn-on (rise) time 28 nstoff Turn-o (fall) time 165 nsRθjc Thermal resistance, junction to case 0.9°C/WRθcs Thermal resistance, case to sink 0.85°C/WVF Forward diode voltage 1.23 V

The inverter phase currents iu, iv and iw are of sinusoidal form with a ripplecomponent superimposed on them as described previously. For loss calcula-tions the approximation is made that these currents are pure sinusoids. Thephase currents are out of phase with the fundamental frequency of the phasevoltages vu, vv and vw as explained. The time period for one complete currentor voltage sine wave is denoted T1.



Similarly as with the MOSFET power losses, the IGBTs also have conduction,switching and diode losses. A sinusoidal current is positive and negative forthe same duration of time; hence the switching losses in all six switches areidentical. The losses are calculated for switch S1. The currents through theIGBT and diode of S1 are seen in Fig. 6.4. As described before, during thepositive half-cycle of the fundamental phase current iuf , most of the currentwill ow from the generator towards the dc bus through the forward biaseddiode D1. Alternatively, current will ow through the IGBT of S2 when itis on. During the negative half-cycle of iuf while S1 is on, current will owthrough the IGBT of S1, otherwise current will ow through the diode D2.

First consider the conduction losses. In order for an IGBT to conduct cur-rent it needs an on-voltage across the collector and emitter terminals referredto as Vce(on) or Von. The average power dissipated in the IGBT of switch S1

over a single period T1 is given by [11]

Pcond = VonIs1, (6.18)

where Is1 is the average current through the IGBT of S1. The average currentis calculated from the fundamental phase current through S1 as well as theduty cycle of switch S1. The fundamental phase current iuf is dened in (6.7)and repeated here for convenience:

iuf = Ipcos(ωs1t+ φ) = Ipcos(θ + φ), (6.19)

where Ip is the amplitude of the fundamental phase current and ωs1 is theangular frequency of each of the modulator reference voltages. The angle φdenotes the phase angle and was calculated in (6.6) as 36.38°. Both the ampli-tude of the fundamental phase current Ip and the phase angle φ will remainfairly constant with respect to the angular frequency, except at low angularfrequencies, where the phase angle will increase (resulting in a decreased powerfactor) to a maximum of 180°, at which point the generator acts as a motor.Similarly the current amplitude Ip will decrease to 0 A due to the fundamentalphase voltages decreasing with frequency. The loss calculations are performedfor the worst case scenario, hence current Ip is at a maximum (15 A) and thephase angle is at 36.38°.

Figure 6.8 shows a detailed graph of the current through the IGBT of switchS1 over three switching periods. During the on-time of each switching periodTs, the current is1 is assumed constant as shown in red in Fig. 6.8, but theamplitude at each switching period will vary [31]. By using a Riemann sumapproximation the area of the waveform shown in Fig. 6.8 can be calculated.When divided by the time period T1, this results in the average current Is1such that

Is1 ≈1

T1

N∑i=1

d1Ipcos(ωs1ti + φ)Ts, (6.20)



ti -1 ti ti +1 t

|d1Ts|

i s1

Ip cos (ωs1ti + φ)

Figure 6.8: Average switching current approximation taken from [31].

where the duty cycle d1 of switch S1 is given in (6.8). By expanding (6.20) intointegral form and also substituting ωs1t for the angle θ, the average currentover one angular rotation of 2π can be calculated. The lower and upper limitsof the integral are derived from Fig. 6.4 which shows current only ows throughthe IGBT of S1 when ωs1t is between π

2−φ and 3π

2−φ radians. With positive

current dened as owing into the dc bus, the average current Is1 is calculatedas

Is1 = − 1

2π

∫ 3π2−φ

π2−φ

1

2[1 +macos(θ)] Ipcos(θ + φ)dθ

= − Ip4π

∫ 3π2−φ

π2−φ

[cos(θ + φ) +macos(θ)cos(θ + φ)] dθ

= − Ip4π

∫ 3π2−φ

π2−φ

[cos(θ + φ) +

ma

2cos(2θ + φ) +

ma

2cos(−φ)

]dθ

=Ip2π

− Ipma

8cos(φ)

= 1.13 A.

(6.21)

The modulation index ma is dened in (6.3). The maximum rated machinecurrent of 15 A was used for Ip. From (6.18) and with Von given as 1.25 Vin Table 6.1, the average conduction losses for switch S1 was calculated as1.41 W.

The switching losses are due to the small amount of time during whichthere is current through as well as voltage across the IGBT when it changesstate, either from on to o or from o to on. These time periods are denedas ton and toff respectively. With reference to Fig. 6.4, the switching losses inthe IGBT of S1 during one angular rotation ws1 are approximated by [31]



Pswitch ≈ 1

T1

N∑i=1

1

2Vdc(pp)Ipcos(ωs1ti + φ)(ton + toff )

=Vdc(pp)Ip2T1Ts

(ton + toff )N∑i=1

cos(ωs1ti + φ)Ts

≈Vdc(pp)Ip4πTs

(ton + toff )

[−∫ 3π

2−φ

π2−φ

cos(θ + φ)dθ

]

=Vdc(pp)Ip2πTs

(ton + toff )

= 3.27 W,

(6.22)

where the peak-to-peak dc bus voltage Vdc(pp) is 355 V and the switching fre-quency fs is 20 kHz.

When switch S1 is o and the fundamental phase current iuf is negative,current will ow through the diode of S2. With reference to Fig. 6.4 and from(6.19) and (6.21), the average current Id2 is calculated during the negativehalf-cycle of iuf as

Id2 = −iuf − Is1

= − 1

2π

[∫ 3π2−φ

π2−φ

Iscos(θ + φ)dθ

]− Is1

=Isπ

− Is1

= 3.64 A.

(6.23)

The average conduction loss through diode D2 is given by

PD2 = VF Id2 = 4.48 W, (6.24)

where VF is the diode forward voltage given in Table 6.1 as 1.23 V. The totalpower loss through one diode and one IGBT during T1 is thus

Ptot = Pcond + Pswitch + PD2 = 9.16 W. (6.25)

The total power dissipated in each of the other diodes and IGBTs of theinverter is equal to the power dissipated in the IGBT of S1 and the diodeof S2, respectively. The total power loss inside the complete IGBT module isthus given by

Pmod = 6Ptot = 54.96 W. (6.26)

The heat generated by the IGBT module due to the power loss Pmod is dissi-pated with the help of a heat sink. The rise in junction temperature due tothe losses is given in (3.32) and repeated here for convenience:



∆Tj = PT (Rθjc +Rθcs +Rθsa) . (6.27)

The junction temperature is permitted to rise to a maximum of 150°C. Ab-solute worst case ambient temperature is assumed to be 40°C, therefore ∆Tj

= 110°C. From the IGBT module's datasheet the junction-to-case Rθjc andcase-to-sink Rθcs thermal resistances are given as 0.9°C/W and 0.85°C/W re-spectively. From (6.26) and (6.27) the sink-to-ambient thermal resistance Rθsa

is required to be 0.251°C/W in order to keep ∆Tj below 110°C. A 150 mmby 210 mm MeccAL aluminium heat sink was available for this project. Fromthe datasheet the sink-to-ambient thermal resistance is given as 0.15°C/W atan airow rate of approximately 5 m/s. Airow is provided by a small 12 Vbrushless dc fan mounted on the side of the heat sink. Thus

∆Tj = 54.96(0.9 + 0.85 + 0.15) = 104, (6.28)

and the maximum allowed ambient temperature is thus 46°C. In the case ofthe chosen IGBT module the junction-to-ambient temperature is rather high.This is due to the junction-to-case and case-to-sink thermal resistances that arethemselves high, due to the small size (and thus surface area) of the module.

6.1.3 Over-Temperature Protection

The IGBT module is equipped with a negative temperature coecient (NTC)thermistor which can be used to detect over-temperature conditions. The tem-perature sensor is located on the case of the IGBT module. The circuit shownin Fig. 6.9 is used to detect the temperature of the IGBT module. A voltagedivider circuit is used to obtain a voltage corresponding to the resistance ofthe thermistor, which is a function of the IGBT module's temperature.

Vcc

Rθ

dsPIC

A/DRd D1

Ve

FaultVe

R1

Figure 6.9: Temperature sensing circuit for the IGBT module.

At a case temperature of 100°C (equating to a junction temperature of 150°C),the thermistor Rθ has a value of 493 Ω with a deviation of ±5 % as indicated in



the IGBT module's datasheet. The recommended maximum power dissipationinside the NTC thermistor is Pmax = 9.6 mW. The maximum current is thus

Imax =

√Pmax

R100

= 3.74 mA. (6.29)

The supply voltage Vcc for the circuit is chosen as 5 V and henceR1 is calculatedas

R1 =Vcc

Imax

−R100 = 843 Ω. (6.30)

A 1 kΩ resistor was used for R1. The voltage at the output of the voltagedivider circuit is 3.35 V for an IGBT module temperature of 100°C. The outputof the voltage divider is fed into one of the dsPIC's 12-bit analog-to-digitalconverter (ADC) inputs. The dsPIC used as part of the inverter controller isthus also used to perform functions related to the protection of the invertercircuit and general housekeeping tasks.

The dsPIC is programmed to produce an ADC interrupt every 0.8 ms.Inside the interrupt subroutine the ADC's value is compared with the decimalvalue of 2744 which corresponds to 3.35 V. If the ADC's value is smaller than2744, the interrupt is cleared and the dsPIC continues to function normally.

If however the value is bigger than 2744, a 5 V error signal Ve is producedat one of the dsPIC's digital outputs and a red LED is turned on indicating anover-temperature condition occurred. Also, one of the dsPIC's digital outputlines referred to as the Fault line, is set low (0 V). The resistor Rd shown inFig. 6.9 has a value of 220 Ω and is used to limit the current through diodeD1 to less than 15 mA.

The six PWM signals (one for each IGBT) generated by the inverter controlcircuitry each pass through a high-speed CMOS logic 2-input CD74HC08 ANDgate before feeding into an optocoupler located inside a gate driver IC. Theother input to the respective AND gates is an error signal generated by thedsPIC Fault line. A block diagram of this circuit for one PWM channel isshown in Fig. 6.10.

ControlCircuit

PWMSignal

dsPIC

FaultSignal

CD74HC08

GateDriverCircuit

Switch

Figure 6.10: PWM signal and error signal integration.

Take for example switch S1. The controller generates a desired PWM switchingsignal for S1. This PWM signal, along with the error signal, is passed through



the two input AND gate. The output of the AND gate feeds the gate-drivecircuit used to turn switch S1 on and o. If the error signal is low, meaninga fault condition exists, then the output of the AND gate will remain low.Hence, the signal that is sent to the gate driver is also low, leaving switchS1 in an o state. Consequently if the error signal is high, meaning there isno fault condition, the PWM signal is passed through the AND gate to thegate-drive circuit, enabling the desired controller switching action of S1.

The same error signal is fed into all six AND gates, thus if a fault conditionexists, all the switches are simultaneously switched o, setting the pole pointsof the inverter into a high impedance state.

Since a high junction temperature is caused by the switching action, withthe switching action halted, the junction as well as case temperature will dropbelow the fault threshold temperature. The LED powered by the dsPIC willhowever not turn o if the case temperature drops below 100°C, nor will theinverter start switching again. The dsPIC Fault line will remain low. ThedsPIC and controller circuity have to be restarted in order to clear the errorcondition and resume normal switching action at the IGBT gates. This isdone purely for safety purposes and to ensure the cause of the fault conditionis dealt with.

To validate this safety feature a heatgun was used to heat the bottomof the IGBT module casing (which is usually connected to the heat sink) toabove 100°C. The red LED was observed to turn on and the inverter switchingaction terminated. Only once the circuit was restarted did the LED turn oand the inverter resume its switching action. The temperature at which thissafety feature responded was measured by an infrared thermometer as roughly100°C.

6.1.4 Isolated Gate-Drive Circuitry

The isolated gate-drive circuit used to communicate the switching signals tothe gate of each IGBT is similar to the gate-drive circuit used for the MOS-FET switches described in Section 3.1.5. To provide isolation between thecontrol circuit and switches an IGBT gate-drive optocoupler IC is used. Thegate driver is powered by a small push-pull oscillator circuit with a toroidaltransformer and two fast rectier diodes, identical to the circuit used in Sec-tion 3.1.5. The supply voltage to the oscillator circuit is however changed to15 V and the transformer ratio to 10:11. The gate driver IC supply voltage isthus 16.5 V.

The gate driver IC chosen is the ACPL-333J gate driver from Avago Tech-nologies. It is specically designed as an IGBT gate-drive optocoupler equippedwith integrated (Vce) desaturation detection and feedback, undervoltage lock-out and active Miller clamping [35]. The characteristic values of the gate driverare given in Table 6.2.



Table 6.2: ACPL-333J gate driver characteristic values.

Parameter Description ValueVCC2 Positive supply voltage range 15-30 VIO Maximum peak output current 2.5 AVIORM Maximum working insulation voltage 1414 VVUV LO Undervoltage lockout threshold 11.6 VVDESAT Desaturation detection threshold 7 VIM Maximum active Miller clamp current 1.7 Atp Maximum propagation delay time 250 nsCM Common mode transient immunity 50 kV/µs

The maximum voltage across one of the IGBT switches is the rail-to-rail busvoltage of 355 V. The turn-on time of the switches is given as 28 ns and theturn-o time as 165 ns in Table 6.1. The turn-on time is signicantly fasterthan the turn-o time; hence the maximum rate of change of IGBT voltageoccurs when the switch is turned on where

dV

dt=

Vmax

ton= 12.7 kV/µs. (6.31)

The dV/dt rating of the gate driver is thus sucient to support the switchingaction of the IGBTs, since the gate driver is rated to withstand 50 kV/µs.

ACPL-333J

VCC2

VEE

DESAT

Vclamp

Vout

VEE

Rg

RPD

Rb D1 Z1

Cb

ANODE

CATHODE

VCC1

Fault

Vs

Rp

PWMSignal

RF

CF

dsPICInput

+5VOscillatorPowerCircuit

Figure 6.11: Block diagram of the IGBT gate-drive circuit.

A block diagram of the isolated gate-drive circuit is shown in Fig. 6.11. Dur-ing normal operation the PWM signal from the control circuit is fed through



resistor Rp into the anode of the light emitting diode located inside the gatedriver's optocoupler which then controls the output voltage Vout (as either highor low). The resistor Rp is chosen as 470 Ω. At the same time the desatura-tion detection circuitry is continuously monitored and the Fault line outputvoltage is high.

Once the desaturation detection picks up a Vce value of more than 7 V ittriggers a fault condition, during which time the output voltage Vout is reducedto zero. This allows the switch to be turned o softly and prevent large di/dtinduced voltage spikes. The internal fault feedback is activated which changesthe Fault line voltage from high to low in order to notify the control circuit.The PWM signal from the control circuit is ignored during the fault period.After a xed period of approximately 26 µs the fault pin is reset and normaloperation will continue unless Vce is still larger than 7 V.

The fault feedback is given as a digital input to the dsPIC digital sig-nal processor. Similarly as with an over-temperature fault, a yellow LED isswitched on indicating an overcurrent fault occurred at one or more of theIGBT switches. The dsPIC output Fault line is set low and the same se-quence of events will follow as described in the previous subsection. Essentiallyall switching action is stopped and the inverter is shut down. Again the circuitis required to restart before the dsPIC Fault line will change to a high state,allowing the switching action to resume and for the yellow LED to turn o.

The output of the gate driver is controlled by the PWM control signal,the protection circuitry, the desaturation detection circuitry as well as by theundervoltage lockout protection. If the voltage supplied by the oscillator circuitto the gate driver is less than 11.6 V, Vout is not allowed to go high due tothe undervoltage lockout feature of the gate driver. Once the supply voltageis again greater than the threshold voltage, the output is allowed to go high.This feature protects the gate driver and the switch if the oscillator circuitwere to fail.

The active Miller clamp capability allows the use of a positive supply volt-age only for the gate driver, while still controlling the Miller current duringhigh dV/dt transients. When the IGBT is switched o the gate voltage ismonitored. The clamp circuitry is only activated when the gate voltage dropsbelow 2 V, providing a low impedance path to sink the Miller current quickly.The clamp is released as soon as the next optocoupler LED trigger from thecontrol circuit is received.

To ensure the maximum output current the gate driver can supply is notexceeded, the gate resistor Rg shown in Fig.6.11 is required to have a minimumvalue of

Rg(min) =Vcc2

IO=

16.5

2.5= 6.6 Ω. (6.32)

The nal value for Rg was chosen as 10 Ω, thus limiting the output current to1.65 A. To clamp the output voltage Vout at Vcc2 (16.5 V) a pull-down resistor



is required and is recommended in the datasheet to sink 650 µA of currentwhile the output is high. The pull-down resistor is calculated as RPD = 16.5

0.65

= 25.4 kΩ. The nal value for the pull-down resistor was chosen as 27 kΩ.The Fault output is connected internally within the gate driver to the

collector of a BJT. A passive pull-up resistor RF is thus required and therecommended value is given as 2.1 kΩ. A 2.2 kΩ resistor was used for RF .Along with the pull-up resistor, a 1 nF ltering capacitor CF is recommendedbetween Fault and Vs thus CF was chosen as 1 nF.

As seen in Fig. 6.11 the desaturation detection circuit requires componentsRb, Cb, D1 and Z1 to be connected externally from the gate driver to functioncorrectly. The desaturation detection is internally set to trigger when Vce

equals 7 V, but for the chosen IGBT module this value is too high. At a Vce

value of approximately 1.7 V the collector current will already reach a value ofaround 25 A. Since the peak current through the inverter switches will neverexceed 15 A, the desaturation protection is chosen to trigger at Vce = 1.7 V.To achieve this a 3.9 V zener diode denoted by Z1 in Fig. 6.11 was placed inseries with D1, a BYV26EGP ultrafast diode with a forward voltage of 1.4 V.

The values for Rb and Cb are specied in the datasheet as 100 Ω and100 pF respectively. Resistor Rb is simply used as a protection resistor to limitthe current from the gate driver such that it will not damage the IC. Thedesaturation fault detection circuitry is designed to stop any fault feedbackonce the IGBT switches on for a short period of time, to allow the Vce value tofall below the threshold value. This time period can be adjusted by changingCb. With Cb = 100 pF the blanking time is 2.7 µs.

6.1.5 Overvoltage Protection

The dc bus voltage is regulated by the dc-dc converter circuit. There areonly two probable situations which will cause the dc bus voltage to exceed thenominal voltage of 355 V rail-to-rail. For both cases it is assumed there is noload connected to drain the bus voltage.

The bus voltage will rise if the current owing from the generator intothe dc bus is greater than the maximum current that each dc-dc converter ispermitted to conduct. This occurs at a mean dc bus current of 6.857 A. Theadditional current will ow into the capacitors thus charging them to a valuehigher than the nominal voltage. A value of 6.857 A corresponds to an averageinductor current of 10 A which is the current limit for charging the batteriesas given in the battery datasheet. Since the mean bus current is regulated bythe inverter circuit, it should never exceed an average current of 5.7 A unlessthe control circuit fails.

Secondly, the dc bus voltage will rise if the converter circuit is switched owhile the generator is still supplying power to the dc bus. If the converter orbatteries are disconnected there is nothing to sink the dc bus current exceptfor the bus capacitors. They will continue to charge until they reach voltages



higher than what they are rated to operate at. In order to protect the capac-itors as well as the other high voltage components such as the MOSFETs andIGBTs, overvoltage protection was added to the inverter control circuit.

The dc bus voltage is monitored and a scaled version of the bus voltage isfed into a comparator. If the bus voltage exceeds 365 V, which is 5 V higherthan the allowed operating range, the comparator output changes from a high(5 V) to a low (0 V) state. The output of the comparator connects to one ofthe digital input lines on the dsPIC as well as directly to the AND gates usedfor sending the switching signals to the optocoupler inside the gate driver IC.The switching action is thus stopped immediately after the overvoltage faultoccurred. The dsPIC ensures the fault is detected and keeps the digital outputfault line low until the control circuit is reset.

6.2 PWM Controller Design

A block diagram of the proposed PWM control circuit is shown in Fig. 6.12.A double control loop approach is followed with an inner and outer controlloop. The inner loop functions to control the amount of current owing fromthe inverter into the dc bus, while the outer control loop regulates the batteryvoltage of the converter. The inner current control loop measures and comparesthe mean dc bus current with the set-point voltage vseti generated by the outervoltage control loop, where one volt at vseti corresponds to 1.14 A of currentsupplied by the generator to the dc bus. The set-point vseti is dependant uponthe state of charge of the converter's batteries as determined by the voltagecontrol loop.

Vbat∗ Σ

+

−vfbv

VoltageController

vrefi

Limiter

vseti

Σ+

−vfbi

CurrentController

Scaling

MachineModel

InvPlant

idc ConvPlant

vbat

CurrentSensor

VoltageSensor

ModulatorCircuitInner Loop

vε vcs

Figure 6.12: Block diagram of the inverter control circuit.

The battery voltage set-point Vbat∗ is a constant corresponding to 272 V. The

resulting individual battery potential is 13.6 V for each of the twenty lead-acidbatteries connected to the converter circuit.

As seen from Fig. 6.12, the current set-point vseti, generated by the voltagecontrol loop, is limited to between 0 V and 5 V such that the average dc bus



current is limited to a minimum of 0 A (to ensure the induction machine neveroperates continuously as a motor) and a maximum of 5.7 A.

The magnitude of the control signal vcs generated by the current controller,as seen in Fig. 6.12, is also limited to 5 V since it feeds into an analog inputpin on the dsPIC DSP. The generator shaft speed is measured and also givenas an input to the dsPIC. Inside the dsPIC the magnitude of the control signalis scaled according to the angular speed of the generator shaft to ensure aconstant Volt/Hz ratio is maintained.

The dsPIC is responsible for producing the sinusoidal reference waveformsthat are compared with the triangular carrier waveform to generate the re-quired PWM switching signals for the six IGBTs. In Fig. 6.12 the PWMgeneration circuit is denoted as the modulator circuit and will be described inmore detail in the subsections to follow.

Both the voltage and current controllers are designed using frequency do-main analysis. The necessary time domain equations are derived to obtain thefrequency domain equations by using the Laplace transform. The time domainsimulations are only presented in the next chapter alongside the measured testresults for comparison purposes.

6.2.1 Inverter Plant

The plant portion of the inverter circuit is shown in Fig. 6.13. It is used toidentify the relationship between the generator line voltages and the currentowing into the dc bus. The inverter phase voltages, and hence also the gener-ator line voltages, are controlled by the switching action of the IGBTs dictatedby the current control loop.

The approximation is made that the instantaneous power owing into thedc bus equals the instantaneous power owing out of the generator, hence theswitching and conduction losses are not taken into account. The dc bus currentis related to either the inverter phase voltages and currents or the generatorline voltages and currents, since the total instantaneous power from the in-verter phase voltages and currents must equal the total instantaneous powerfrom the generator line voltages and currents. With reference to Fig. 6.13 theinstantaneous power owing into the dc bus is given by [11]

Vdc(pp)idc = vaia + vbib + vcic, (6.33)

where Vdc(pp) is the converter regulated dc bus voltage of 355 V and idc is thetime-varying dc bus current. The line currents are sinusoidal with a small rip-ple component superimposed on them and can thus be viewed as pure sinusoidswith only the fundamental components present.

The triangular carrier waveform's switching frequency is much larger thanthe fundamental frequency of the line voltages, resulting in a large frequencymodulation ratio. The amplitudes of the subharmonics will thus be very small



idc

Ci

+Vdc

−Vdc

S1

is1

id1

S2

vu

is2

id2

S3

is3

id3

S4

vviv

ib vb

is4

id4

S5

is5

id5

S6

vwiw

iu

is6

id6

icvcia

va

3-PhaseMachine

Figure 6.13: Bidirectional inverter circuit.

and it can be approximated that only the fundamental frequency component ofthe line voltages will contribute towards the instantaneous power generated bythe induction machine [11]. With the line voltages and currents approximatedas fundamental line voltages and currents, (6.33) reduces to

idc =2Vs(rms)Is(rms)

Vdc(pp)

[cos(ωs1t)cos(ωs1t+ φ)

+ cos(ωs1t− 120)cos(ωs1t− 120 + φ)

+ cos(ωs1t+ 120)cos(ωs1t+ 120 + φ)]

=3Vs(rms)Is(rms)

Vdc(pp)

cosφ,

(6.34)

where Vs(rms) and Is(rms) are the rms values of the fundamental line voltagesand currents, respectively. The angle φ denotes the power factor angle asdescribed earlier. The rms values of the generator line voltages and currentsare related by the equivalent generator impedance Zeq such that

Is(rms) =Vs(rms)

|Zeq|, (6.35)

where |Zeq| is the magnitude of the equivalent generator impedance given in(5.17). Recall the amplitudes, and therefore also the rms values of the fun-damental line voltages, are varied in proportion to the angular frequency of



the fundamental waveforms in order to maintain constant rms ux within thegenerator core. The impedance Zeq is also frequency dependant and thus from(6.35) the rms value of the line currents will remain fairly constant. At lowfrequencies (below 20 Hz) the real component of the impedance dominates theimaginary component that varies with frequency and hence Is(rms) will changewith Vs(rms).

The control circuit is designed for the worst case scenario and thus Is(rms)

is assumed constant and equal to the maximum delta connected rms currentgiven in the machine datasheet as 6.07 A for the frequency domain analysis.

The phase angle φ with respect to the generator frequency is shown inFig. 6.14 and was calculated using the equivalent generator model derived inChapter 5. The phase angle is seen to remain fairly constant at frequenciesabove 25 Hz. The generator will only be allowed to operate at frequenciesabove 7 Hz since it draws instead of delivers current at lower frequencies. Theangle φ is assumed constant and equal to 36.38° as calculated from (6.6) forthe frequency domain analysis.

10 20 30 40 50 60 70 800

45

90

135

180

Frequency (Hz)

φ(deg)

Figure 6.14: Phase angle over generator operating frequency range.

The Laplace transform of the (6.34) yields

Idc(s) =3Is(rms)

Vdc(pp)

cosφVs(s), (6.36)

where Vs(s) is the rms line voltage of the generator that varies with frequency.The transfer function of the inverter plant Gp(s), describing the average dcbus current as a function of the rms line voltage, is thus given by

Gp(s) =Idc(s)

Vs(s)=

3Is(rms)

Vdc(pp)

cosφ. (6.37)

The plant portion of the inverter is thus combined with the machine modelshown in Fig. 6.12.



6.2.2 Digital Signal Processor Interfacing

The main function of the dsPIC is to assist with the control of the inverterswitches. It is also used alongside protection circuitry as mentioned throughoutthis chapter. The 30F4013 dsPIC from Microchip was chosen for its DSPcapabilities and functionality. The parameters of the dsPIC is summarised inTable. 6.3.

Table 6.3: Parameter values of the dsPIC30F4013 DSP.

Parameter ValueArchitecture 16-bitCPU speed 30 MIPSProgram memory 48 KBRAM 2048 BEEPROM 1024 BOperating voltage 2.5 V to 5.5 VOperating temperature -40°C to 125°CPin count 40Input/output pins 30Communication peripherals 2 UART, 1 SPI, 1 I2CAnalog peripherals 1-ADC, 13 x 12-bit at 200 kspsTimers 5 x 16-bit, 2 x 32-bit

The dsPIC is operated at 5 V and 10 MHz. An external 10 MHz crystaloscillator was used to generate the internal 10 MHz clock. The dsPIC wasprogrammed using a dsPICDEM 2 development board and an MPLAB ICD2in-circuit debugger.

The generator is driven by an identical induction motor controlled by acommercial o-the-shelf variable-speed drive system to simulate airow througha turbine that would otherwise apply torque to the generator shaft. Due to thelarge moment of inertia, the speed at which the generator shaft is turning willnot change rapidly; hence vector control is not required. The stator voltagesare controlled as a function of the dc bus current, but Volt/Hertz control isalso included inside the inner control loop using the dsPIC to ensure the ma-chine's magnetic rms ux stays constant. The detailed operation of the dsPICis described in this section.

The current controller produces a control signal vcs which feeds into one ofthe 12-bit ADC channels on the dsPIC. The dsPIC is operated at 5 V, hencethe maximum allowed voltage at any of the input pins is also 5 V. The controlsignal vcs is limited to between 0 V and 5 V by means of an active clampcircuit identical to the circuit used for limiting current and voltage inside theconverter as described in Section 3.2.4.



To determine the shaft speed of the generator a magnetic pick-up sensor wasused. The functioning of the magnetic pick-up circuit is demonstrated inFig. 6.15. The magnetic pick-up consists of a small permanent magnet and acoil wound around the magnet. The permanent magnet establishes a magneticeld that couples to the coil. When a ferromagnetic material passes in closeproximity to the magnet, the magnetic eld is displaced about the coil. Thus,by Faraday's law, a voltage is induced in the winding. The output voltage isproportional to the strength and rate of change of the magnetic eld coupledto the winding.

Magnetic Pickup

N S

V1

V2

Shaft Coupling

ωr

Figure 6.15: Shaft coupling with magnetic pick-up for speed feedback.

The shaft coupling, connecting the generator and motor shafts, was used as theferromagnetic object, as shown in Fig 6.15. Six holes with a diameter of 14 mmeach, separated exactly 60° from each other, were drilled 10 mm deep into thecircular shaft coupling. The magnetic pick-up was mounted approximately2 mm away from the shaft. One complete rotation thus produces 6 voltagepulses between the two output terminals V1 and V2.

The output signal of the magnetic pick-up is processed using the circuitshown in Fig. 6.16. The coil wound around the permanent magnet can berepresented as an inductor L in series with a resistor R. The output voltagepulses are rst passed through an operational amplier with a gain of approxi-mately 3 to amplify the speed feedback signal. Once the output of the op-ampexceeds 0.45 V, the LM311 comparator changes from a high (5 V) to a low(0 V) state. Even if the shaft is turning at very low speeds, the output voltagewill exceed 0.45 V and thus generate a state-change at the comparator output.Positive feedback is added to provide hysteresis which ensures that no falsestate changes occur.

The output of the comparator is fed into one of the dedicated externalinterrupt pins on the dsPIC. The interrupt will trigger an interrupt subroutine



L

R V1

V2

−

+

Ri

Rf

Ri

Rf

Rpu

+5V

R1

+5V

R2 Rfb

vmp

Figure 6.16: Magnetic pick-up interfacing with the dsPIC.

on every falling edge of the comparator output voltage vmp. The values of thecomponents used in Fig. 6.16 are given in Table 6.4

Table 6.4: Component values for the magnetic pick-up and dsPIC interfacingcircuit.

Component ValueL 350 mHR 580 ΩRi 3.3 kΩRf 10 kΩR1 10 kΩR2 1 kΩRfb 22 kΩRpu 1.8 kΩ

One of the dsPIC's two 32-bit timers is used to count the time interval betweeninterrupts generated by the magnetic pick-up circuit. As soon as the rstmagnetic pick-up is received the timer is reset and starts counting from zero.One count is added every 100 ns since the timer is set to run at the internal10 MHz clock speed of the processor. Once the second interrupt is received,the timer value is stored in memory and thereafter the timer is reset to onceagain start counting from zero. The value that is stored in memory is used tocalculate the frequency of the generator shaft since

f =Fc

6CT

, (6.38)

where f is the shaft frequency measured in Hertz, CT is the timer value storedin memory and Fc is the clock frequency of 10 MHz. The factor 1

6is present

due to the magnetic pick-up producing six interrupts during one completeshaft rotation. The measured shaft frequency f is further divided by a basefrequency fb of 65 Hz to generate a scaling factor Kc. A base frequency of



65 Hz was chosen to avoid saturation currents when the generator is operatedat a slip of -5.47 %. The scaling factor scales the control signal vcs to ensure thegenerator is always operated at constant ux, thus the maximum amplitude Vc

of the dsPIC and DAC output modulator reference waveforms are calculatedas

Vc =f

fbvcs = Kcvcs. (6.39)

If the measured frequency of the generator is less than 7 Hz, the control signalvcs is gradually reduced to zero inside the dsPIC since the machine simulationpredicted the generator is only able to supply power when operating at afrequency above 7 Hz. Below 7 Hz the generator will actually draw powerfrom the dc bus to keep it running when operated at a slip of -5.47 %.

Similarly, the control signal vcs is reduced to zero inside the dsPIC whenthe measured shaft frequency exceeds 75 Hz (4500 rpm), which is the speciedmaximum operating frequency of generator system. When the generator isrunning at either under 7 Hz or above 75 Hz an orange LED is switched on,visually indicating the generator shaft speed is out of range. When the controlsignal vcs reaches zero the switches are all switching at a constant duty cycleof 50 % and the amplitudes of the fundamental phase voltages applied to thegenerator stator terminals are also zero. No power will thus be transferredbetween the generator and the dc bus.

The orange LED switch o once the shaft speed is again within the speciedrange. At the same time the control voltage is gradually increased to thedesired value.

In order to generate the required PWM signals, three 120° separated si-nusoids have to be compared with the 20 kHz triangular carrier waveform asexplained in the previous section. The dsPIC is used to generate these three si-nusoidal modulator reference waveforms using a look-up table (LUT) approachsimilar to the approach followed in [44] and [45] where a part of the sinusoidis pre-computed and stored in the memory of the processor used, thus forminga binary LUT.

The maximum resolution of the sine wave generated within the dsPIC ischosen as 12 bits, where the 12th bit is used to indicate the polarity of thesinusoid as either positive or negative. The sampling speed of the sine wave waschosen as 128 samples per 60°. The sine wave was modelled using MATLABwhere the amplitude of the sine wave peaked at 2047 corresponding to theavailable 11-bit magnitude inside the dsPIC.

Since the induction generator is designed to function at a slip of -5.47 %,the number of samples during 60 degrees of rotation is 128

0.948= 135 samples. To

simplify the look-up process inside the dsPIC, the entire positive half of thesine wave generated in MATLAB was stored in the EEPROM. The EEPROMthus contain 135× 3 = 405 samples where each sample is represented using 2bytes.



The three sinusoidal modulator reference waveforms vru, vrv and vrw generatedby the dsPIC, are shown in Fig. 6.17. Each have their own LUT pointer. Theamplitudes of the modulator reference waveforms are equal and denoted Vc,as dened in (6.1) for vru. At a sample speed of 128 samples per every 60°,the counter value CT is divided by 128 to produce a timer limit LT for a16-bit timer. Each time the 16-bit timer reaches the limit LT an interruptis generated and the three pointers are all incremented to point to the nextcorresponding value inside the LUT.

vcs

vmp

dsPIC30F4013

vrv

vru

vrw

Figure 6.17: Three-phase reference waveform generation with the dsPIC.

The LUT value is then manipulated such that the 12th bit is set high if thesinusoid is negative. Also the scaling factor Kc is used to scale the magnitudeof the LUT value (and thus also scale the magnitude of the sinusoid) accordingto the value read in by the ADC for vcs and the speed of the generator shaft.

The dsPIC was programmed in assembly language using the MPLAB ed-itor. Assembly was chosen instead of the C programming language to haveprecise control over the number of instruction cycles that occur after the mag-netic pick-up produces an interrupt. This ensures the correct timer value isstored in memory and allows for a more accurate shaft speed calculation.

The three manipulated LUT values are communicated to a 12-bit AD7398digital-to-analog converter (DAC) using the serial peripheral interface (SPI)protocol. The DAC outputs three modulator reference sinusoids, each with amaximum amplitude of 2.5 V and a dc oset of 2.5 V. The dc oset is removedand a gain of two is added using a dierential LF353 operational amplier. Thethree resulting modulator reference waveforms, with a maximum amplitudeVc of 5 V, are used for comparison with the triangular carrier waveform togenerate the PWM switching signals using high-speed AD790JN comparatorsfrom Analog Devices.

The complete circuit diagram containing the dsPIC, DAC and magneticpick-up interface circuit is given in Appendix A.2.2. A small PCB containingthese circuit components is mounted on top of the analog control PCB. BothPCBs are given in Appendix B.2.2.



6.2.3 Current Control Loop

The current control loop, shown in Fig. 6.18, functions to control the meandc bus current by controlling the switching action of the IGBTs using bothanalog and digital circuitry. Essentially the controlling of the switches allowsthe amount of power generated by the induction machine to be controlled,and since the dc bus voltage is assumed constant, the dc bus current is thuscontrolled. The digital part of the controller was already described in theprevious subsection along with the PWM signal generation.

Idc∗

(Vseti)Σ

+

−Vfbi

Gc(s) KcVc

P (s) KmVs

Gp(s)

H(s)

IdcVcs

Figure 6.18: DC bus current control loop block diagram.

In Fig. 6.18 Gp(s) denotes the transfer function of the inverter plant portionderived in (6.37) and the transfer function H(s) denotes the current sensingfeedback circuit. The current control loop's compensation amplier is de-scribed by the transfer function Gc(s).

The transfer function P (s) shown in Fig. 6.18 is a third order Padé approx-imation [46] used to approximate the various time delays within the currentcontrol loop as a time-continuous function for frequency domain analysis. Thetime delays, mainly due to the dsPIC, can potentially cause system instabil-ity and it is therefore important to include the time delays in the frequencydomain analysis. Note, a time delay introduces phase shift only and does notaect the magnitude of the control loop's response. The total control looptime delay was overestimated as 1 ms. The Padé function within MATLABwas used to model this time delay.

The scaling factor Kc used for the Volt/Hertz scaling within the dsPIC(as detailed in the previous subsection) is also included in the current controlloop as shown in Fig. 6.18. The scaling factor has a maximum value of 1and a minimum value of 0.11 (at a generator shaft frequency of 7 Hz). Thegain denoted Km in Fig. 6.18 is used to represent the modulator circuit and isdescribed in detail next.

A linear model of the PWM circuit is assumed, thus a linear relationshipexists between the sinusoidal modulator reference signals (vru,vrv and vrw) andthe fundamental inverter phase voltages (vuf ,vvf and vwf ). The rms voltageVs(rms) of the fundamental generator line voltages (vaf ,vbf and vcf ) is relatedto the amplitude of the inverter phase voltages Vp by



Vs(rms) =

√3√2Vp. (6.40)

Substituting (6.4) and (6.2) into the above equation yields

Vs(rms) =

√3

2√2maVdc(pp)

=

√3

2√2

(Vc

Vr

)Vdc(pp)

≈0.612Vdc(pp)

Vr

Vc,

(6.41)

where Vr is the amplitude of the triangular carrier waveform and Vc is dsPICscaled amplitude of the modulator reference voltages. The Laplace transformof the above equation yields:

Vs(s) ≈0.612Vdc(pp)

Vr

Vc(s). (6.42)

With reference to Fig. 6.18, the frequency dependant rms line voltage Vs(s)and modulator reference waveform amplitude Vc(s) are thus related by Km

where

Km =Vs(s)

Vc(s)=

0.612Vdc(pp)

Vr

. (6.43)

The dc bus current is measured using an ACS756 fully integrated Hall ef-fect sensor from Allegro. The characteristics of the sensor is summarised inTable 6.5.

Table 6.5: Allegro ACS756 Hall eect sensor characteristics.

Characteristic Description ValueVcc Supply voltage 5 VIcc Supply current 10 mAtPROP Propagation time 1 µsIp Primary Sampled Current ±50 ASensTA Sensitivity 40 mV/AETOT Maximum total output error ±5 %VISO Voltage Isolation 3 kVTOP Ambient Operating Temperature -40°C to 125°C

At a sensitivity of 40 mV/A and a maximum dc bus current of 5.7 A, themaximum output voltage is 0.228 V. The desired output voltage is 5 V for themaximum dc bus current, hence a gain of 21.93 was required. The circuit used



to convert the measured current into the equivalent desired voltage is shownin Fig. 6.19. The component values for the current feedback circuit are givenin Table 6.6.

ACS756

GND

VCC

viout

Ip+

Ip−

5Vidc

−

+

LF353N

Ri

Rv

V5p

Rf

R1

R2 C1

−

+

R1

R2

C1

vfbi

Figure 6.19: DC bus current sensor feedback circuit.

Table 6.6: Component values for the current feedback circuit.

Component ValueV5p 5 VRv 10 kΩRi 4.7 kΩRf 10 kΩR1 3.3 kΩR2 36.3 kΩC1 100 nF

An LF353 operational amplier is used to provide the additional gain required.The rst op-amp circuit is used to remove the 2.5 V dc oset from the Halleect sensor's output viout. The resistor Rv is a variable resistor to trim thedc oset in case of a small voltage oset error at the sensor's output for a 0 Ameasurement. The output voltage for the rst op-amp circuit is given by

vout =Rf

Ri +Rv

(viout − V5p) + viout. (6.44)

The ratio between the feedback resistor Rf and the two input resistors Rv+Ri

should ideally equal one thus (6.45) becomes



vout = 2viout − V5p. (6.45)

The input V5p is a precision 5 V reference source generated by a REF02 ICfrom Analog Devices. With a dc oset of 2.5 V at viout, the output voltagevout has a gain of 2 with respect to the two input voltages viout and V5p.

The second op-amp circuit is a low pass lter with a transfer function of

L(s) =Zf

Zi

=R2

R1

(1

1 + sC1R2

), (6.46)

and a corner frequency of

f1 =1

2πC1R2

, (6.47)

which equals 43.84 Hz with the component values given in Table 6.6. Thelow pass lter is used to remove the ripple component from the measured dcbus current as well as provide a dc gain of 11. The transfer function for thecomplete current feedback circuit shown in Fig. 6.19 is denoted H(s) and isgiven by

H(s) =Vfbi(s)

Idc(s)=

2RcsR2

R1 (1 + sC1R2), (6.48)

where Rcs equals 40 mΩ and is used to include the 40 mV/A sensitivity of theHall eect sensor. With reference to Fig. 6.18 the open-loop transfer functionof the current control loop Gol(s) is

Gol(s) = Gc(s)KcP (s)KmGp(s)H(s), (6.49)

and closed-loop transfer function Gcl(s) is

Gcl(s) =Gc(s)KcP (s)KmGp(s)

1 +Gc(s)KcP (s)KmGp(s)H(s), (6.50)

where Gc(s) is the transfer function of the compensation amplier and Gp(s) isthe transfer function of the inverter plant derived in (6.37). The frequency do-main analysis of Gol(s) with the dsPIC scaling factor Kc at its maximum valueof 1 is shown in Fig. 6.20, without the transfer function of the compensationamplier present.

The magnitude plot shown in Fig. 6.20 has a corner frequency equal to f1and rolls o at -20 db/decade thereafter. The bandwidth of the current controlloop without the compensation amplier present is determined from Fig. 6.20to be 37.3 Hz. The phase plot indicates a large phase shift mainly due to thethird order Padé approximation of the time delay within the current controlloop.



−40

−20

0

Magnitude

(dB)

100 101 102 103 104−720

−540

−360

−180

0

Frequency (Hz)

Phase

(deg)

Figure 6.20: Bode plot of the open-loop response of the current control loopwithout the compensator present.

The speed of the current control loop should ideally be lower than the lowestoperating speed of the generator (7 Hz) since the generator will inherentlyreact slowly to a change in the applied stator voltages.

−

+vcs

Rvfbi

C

Rvseti

C

Figure 6.21: Active integrator compensation circuit.

In order to provide a theoretical innite gain at dc, an integrator is requiredin the compensation amplier. The integrator will also lower the bandwidthof the current control loop and is thus in itself an adequate compensationamplier for the current control loop. The active integrator circuit is shownin Fig. 6.21. The transfer function for the compensation amplier is given by

Gc(s) =Vcs

Vseti − Vfbi

=1

sCR. (6.51)



The resistor R was chosen as 120 kΩ and the capacitor C as 1 µF. The op-ampused is the LF353 JFET operational amplier from STMicroelectronics.

The frequency domain analysis of both the open- and closed-loop transferfunctions Gol(s) and Gcl(s) are shown in Fig. 6.22. The open-loop transferfunction is seen to have a unity gain crossover frequency of 1.74 Hz whichis within the desired range. The corresponding phase margin is measured as87.1° and the open-loop response shows a -20 db/decade roll-o when it crossesthe zero dB line. The gain margin is determined from Fig. 6.22 as 39.6 dB.With both a positive gain and phase margin the current control loop is shownto be stable.

−150

−100

−50

0

50

Magnitude

(dB)

10−1 100 101 102 103 104−720

−540

−360

−180

0

Frequency (Hz)

Phase

(deg)

Gol(s)Gcl(s)

Figure 6.22: Bode plot of the open-loop response of the complete currentcontrol loop.

The closed-loop response shown in Fig. 6.22 has a dc gain of 1.135 dB corre-sponding to a loop sensitivity of 1.14 A of dc bus current per volt of excitationapplied to the current set-point Vseti. At a maximum set-point voltage of 5 Vthe corresponding dc bus current will rise to and settle at 5.7 A as designedfor.

Due to the large 1 µF capacitor used in the compensation amplier, integralwindup occurs. Recall the output of the compensator Vcs is limited to 5 V.The integral windup will cause a large initial current overshoot in the dc busand will also lead to a slow settling time [47]. Since the current owing into thebatteries is current limited, a large current overshoot is undesirable, especiallyif it will take a prolonged period of time to settle. To combat the integralwindup, a tracking back anti-windup scheme [41] is used. Figure 6.23 shows



a block diagram of the tracking back scheme when using an integrator for thecompensation circuit.

Vseti Σ+

−Vfbi

Σ+

−Vaw

1

sKi

Limiter

Vcs

Σ

+−

Ka

H(s) Idc

Figure 6.23: Tracking back anti-windup scheme with an integral controller.

The gain block labelled Ki in Fig. 6.23 is the integrating factor 1RC

from (6.51),while Ka is the anti-windup factor. The dierence between the limited (satu-rated) output and the unsaturated output of the integrator is fed back to theinput of the integrator after adding gain Ka to the signal, thus producing Vaw.Although it is desirable to make Ka very large to reduce the integrator windupquickly, it will also increase the settling time. Ideally the constant Ka shouldbe close to unity when using an integral compensation method [41]. By testingthe prototype circuit the optimal value for Ka was determined to be 1.27.

The anti-windup circuitry only aects the controller when the integratoroutput is higher or lower than the clamped output Vcs. When the integratoroutput is within the desired operating range, the saturated and unsaturatedoutputs are equal to each other and thus the dierence between them is zero.The voltage at Vaw is thus also zero and will have no eect on the compensationcircuit.

6.2.4 Voltage Control Loop

The combined current and voltage control loops are shown in Fig. 6.24, wherethe inner current control loop is enclosed by the outer voltage control loop.The functioning of the current control loop was presented in the previoussubsection. The outer voltage control loop as shown in Fig. 6.24 functions toregulate the mean battery potential of the 20 lead-acid batteries used in thedc-dc converter circuit.

The transfer function Fp(s) shown in Fig. 6.24 denotes the plant portionof the dc-dc converter in order to obtain a relationship between the dc buscurrent and the state of charge of the batteries. The battery voltage feedbackcircuit has a transfer function J(s) and the transfer function Fc(s) denotes thecompensation circuit used for the outer voltage control loop.



Vbat∗ Σ

+

−Vfbv

Fc(s)

Vseti

Σ+

−Vfbi

Gc(s) Kc P (s) Km Gp(s)Idc

Fp(s) Vbat(s)

H(s)

J(s)

Vε Vcs

Figure 6.24: Voltage and current control loop block diagram.

Either the converter's batteries, the load connected between the dc bus rails,or both, are responsible for sinking the current owing into the dc bus fromthe inverter. Since the load is not permanently connected, current will owinto the batteries, thus charging them. The batteries have a maximum oatinguse potential of 13.6 V to 13.8 V per battery which should not be exceeded.For the safety of the batteries the voltage control loop will strive to keep thebatteries charged to a maximum mean potential of 13.6 V per battery, thus272 V in total.

With reference to Fig. 6.12 and Fig. 6.24 the plant portion of the convertercircuit is derived next. The 40 Ah batteries will take hours to fully chargeand thus simulating their true response with respect to the current they sinkrequires an extremely long simulation. For time domain analysis the batterywas approximated as a constant voltage source in series with a resistor andhence the total battery voltage vbat is given by

vbat = VB + iLRin, (6.52)

where VB is the nominal battery voltage, iL is the mean battery and inductorcurrent, as dened in Fig. 6.1, and Rin is the internal battery resistance. Thenominal voltage VB will be adjusted in the time domain simulation over aperiod of a few seconds to ensure the voltage control loop responds correctlyto a change in battery voltage.

For frequency domain analysis the battery was modelled as a large capacitorin series with a resistor. From rst principles it is known that electrical chargeis equal to voltage multiplied by capacitance (Q = CV ) and one ampere-hourequals 3600 coulombs of charge. The value of the capacitor Cb representingthe battery is thus approximated by

CB =Q

VB

≈ 3600× 40

12× 20= 600 F. (6.53)

The internal resistance of the twenty batteries Rin is approximated as 5 timesthe resistance of the batteries when fully charged, thus 0.95 Ω.

The mean dc bus current Idc is related to the mean battery and inductorcurrent IL by



D1 =IdcIL

= 0.6857, (6.54)

as given in (3.3) and repeated here for convenience. The transfer function forthe battery voltage with respect to the dc bus current is given by

Fp(s) =Vbat

Idc=

1

D1

(1

sCB

+Rin

)=

1 + sCBRin

sD1CB

. (6.55)

The battery voltage is measured by means of a fully dierential amplier asshown in Fig. 6.25 to provide the feedback voltage vfbv. Two capacitors wereadded to the dierential amplier to form a low-pass lter that is used toreduce the noise on the measured signal.

R1R2 C1

−

+

R1−vbat

R2

C1

vfbv+vbat

Figure 6.25: Battery voltage feedback circuit.

At a battery reference voltage Vbat∗ of 5 V the measured battery voltage should

rise gradually to 272 V. The amplier thus acts as an attenuator with a gainfactor of 5

272. The values chosen for R1 and R2 are 446 kΩ and 8.2 kΩ re-

spectively. The capacitor C1 is chosen as a 100 nF ceramic capacitor. The lowpass lter's corner frequency is calculated using (6.47) as 194 Hz.

The transfer function for a low pass lter was already derived in (6.46).With reference to Fig. 6.24, the transfer function of the voltage feedback circuitis denoted J(s) and thus J(s) is given by

J(s) =R2

R1

(1

1 + sC1R2

). (6.56)

The voltage control loop compensation amplier is denoted Fc(s). The blockdiagram shown in Fig. 6.24 can be reduced to the block diagram shown inFig. 6.26 where the inner current control loop is replaced by the closed-looptransfer function Gcl(s) derived in (6.50).

With reference to Fig. 6.26, the open-loop transfer function of the voltagecontrol loop Fol(s) is



Vbat∗ Σ

+

−Vfbv

Fc(s) Idccl(s) Fp(s) Vbat

J(s)

Vε

Figure 6.26: Reduced voltage and current control loop block diagram.

Fol(s) =Vε(s)

Vfbv(s)= Fc(s)Gcl(s)Fp(s)J(s), (6.57)

and the closed-loop transfer function Fcl(s) is

Fcl(s) =Fc(s)Gcl(s)Fp(s)

1 + Fc(s)Gcl(s)Fp(s)J(s). (6.58)

The bode plot of the open-loop response Fcl(s) without the transfer functionof the compensation amplier present is shown in Fig. 6.27. The frequencyresponse shows a unity crossover frequency of approximately 10−5 Hz whichis very low. The desired speed response of the voltage control loop is in factvery slow since the battery voltage will change over a period of minutes tohours. A slight gain can however be added to speed up the voltage controlloop frequency response to approximately 0.01 Hz.

−40

−20

0

20

Magnitude

(dB)

10−6 10−5 10−4 10−3 10−2 10−1 100 101−135

−90

−45

0

Frequency (Hz)

Phase

(deg)

Figure 6.27: Bode plot of the open-loop frequency response of the voltagecontrol loop without compensation.



The ability of the batteries to store charge allows it to act as a large capacitorwhich already provides an integrator as shown in Fig. 6.27, thus the voltagecontrol loop has theoretical innite gain at dc. A low-pass lter with gainand a very low corner frequency is selected as the compensator to ensure thecurrent set-point Vseti is never changed abruptly. The circuit looks identical toFig. 6.25 with R1, R2 and C1 equal to 22 kΩ , 470 kΩ and 100 µF, respectively.The open- and closed-loop response of the voltage control loop are shown inFig. 6.28.

−100

−50

0

50

100

Magnitude

(dB)

10−6 10−5 10−4 10−3 10−2 10−1 100 101−225

−180

−135

−90

−45

0

Frequency (Hz)

Phase

(deg)

Fol(s)Fcl(s)

Figure 6.28: Bode plot of the open- and closed-loop frequency response of thevoltage control loop.

From Fig. 6.28 the gain and phase margins are given by 75.7 dB and 140° re-spectively. The unity crossover frequency increased to 0.0025 Hz. The closed-loop response has a dc gain of 34.71 dB corresponding to a loop sensitivityof 54.33 V of battery voltage per volt of excitation applied to the voltage set-point Vsetv. At a maximum set-point voltage of 5 V the corresponding batteryvoltage will rise to 272 V, as designed for. It should be noted, however, thatregardless of the battery voltage measured by the circuit of Fig. 6.25, the bat-tery charging current will never exceed a mean value of 10 A due to the actionof the dc-dc converter.

The frequency domain analysis thus indicates that both the current andvoltage control loops are stable. The complete circuit schematic for the invertercontrol board is given in Appendix A.2.2.



6.3 Summary

The detailed operation of the bidirectional inverter circuit and asynchronousgenerator were presented in this chapter. The switching and conduction lossesfor the chosen IGBT module were calculated numerically. The design and im-plementation of the inverter circuit's safety features were presented, amongstwhich are over-temperature, overcurrent and overvoltage protection. A de-tailed design of the inverter control circuit was also presented where two con-trol loops, an inner and outer control loop, were used to regulate the dc buscurrent and battery voltage, respectively. Frequency domain analysis showedboth control loops to be stable. The time domain equations describing theinverter operation were derived and the simulations are presented in the nextchapter, along with the measured results from the manufactured prototypecircuit.


Chapter 7

Inverter Simulation and System

Integration Test Results

This chapter contains the simulated and measured test results of the integrateddc-dc converter and inverter circuit. The inverter circuit, designed in the pre-vious chapter, is modelled and simulated in the time domain along with thegenerator detailed in Chapter 5. The simulated circuit is compared to the man-ufactured prototype circuit and the results are discussed. The implementedinverter safety features were tested and observations are presented.

The test set-up for the integration of the inverter and converter circuitsis also described in this chapter. The measured battery voltage is comparedto the measured dc bus current to validate the system integration and todemonstrate the practical operation of the completed circuit.

All time domain simulations were implemented in MATLAB where therelevant dierential equations were once again solved using the iterative Eulermethod.

7.1 System Integration

The operation of the dc-dc converter prototype circuit (with and without aload connected to the dc bus) was already presented and discussed in Chapter4. The inverter circuit was designed to operate from the regulated positiveand negative dc bus rails provided by the dc-dc converter. The inverter con-trol circuitry modulates the voltages applied to the asynchronous generatorstator terminals and in return the generator supplies current to the dc busthrough the inverter circuit at a constant negative slip of -5.47 %. The dc-dcconverter's batteries are responsible for sinking the dc bus current owing intothe converter's dc bus terminals.

118


CHAPTER 7. INVERTER SIMULATION AND SYSTEM INTEGRATION

TEST RESULTS 119

7.1.1 Test Set-Up

The test set-up for the complete system is shown in Fig. 7.1. The prototypeinverter circuit is located on the left-hand side of the table shown in Fig. 7.1,while the prototype dc-dc converter circuit is placed on the right-hand side ofthe table. The 60 Ω , 2.1 kW load is placed between the two prototype circuits.

Figure 7.1: Test set-up for generator and battery interface circuit.

The inverter circuit is constructed in a similar manner to the dc-dc convertercircuit. The control board is mounted on top of the power board connected tothe heat sink. A small 12 V fan is also mounted to the side of the heat sinkand control board. The detailed inverter PCBs are given in Appendix B.2.Both the inverter control and power boards are powered from a 12 V benchpower supply through a DKE10A-15 converter.

The two induction machines (one to drive the other) are mounted on topof the trolley as shown in Fig. 7.1. The VSD controlling the induction motoroperation is located to the right of the two machines.

The measurements for the system operation were obtained using an Agi-lent Technologies oscilloscope, LEM current probe, multimeter and Avometer,depending on the type of measurement required.

7.1.2 Start-Up Procedure

The inverter control circuit is switched on rst (before the dc-dc convertercircuit). The dsPIC ensures the inverter circuit will remain idle (not switching)



TEST RESULTS 120

until it receives at least two magnetic pick-up interrupts to prevent the inverterfrom loading the dc-bus before it is fully charged.

Next, the dc-dc converter is switched on and the dc bus is charged to355 V as presented in Chapter 4. The VSD system driving the inductionmachine used to simulated airow through a turbine is switched on last. Thegenerator shaft starts to turn, generating magnetic pick-up interrupts at oneof the input channels of the dsPIC. The inverter control circuitry responds bygenerating PWM signals to turn on the IGBTs of the inverter, thus poweringthe generator.

7.2 PWM Generation and Gate Signals

The generation of the six PWM signals to drive each of the IGBTs were de-scribed and simulated in the previous chapter. The measured PWM generationresults are presented in this section as well as the measured IGBT gate signals.

7.2.1 Reference Waveforms

The modulator reference waveforms are generated by the dsPIC DSP and thesinusoidal output waveforms are provided by a DAC, connected to the dsPICas detailed in Section 6.2.2. As soon as the inverter control circuit is switchedon, the battery voltage is measured and the dc bus current set-point is adjustedas a function of the battery voltage.

The nominal battery voltage is 12 V and when fully charged it can reach anominal value of 12.6 V, hence the initial measured battery voltage will alwaysremain below 260 V (13 V per battery). The control circuit will produce amaximum current set-point (5 V), thus demanding 5.7 A of dc bus current, ifthe measured voltage is below 260 V due to the gain provided by the voltagecontrol loop's compensation amplier.

Once the magnetic pick-up senses the generator shaft frequency has ex-ceeded 7 Hz, the orange warning LED switches o and the amplitudes of thesinusoidal modulator reference waveforms slowly increase as shown in Fig. 7.2.The maximum amplitude of a waveform is dependent on the speed of thegenerator shaft and the magnitude of the control signal vcs, generated by thecurrent control loop's compensation amplier.

At a shaft frequency of 25 Hz and a maximum vcs control signal magnitudeof 5 V, the maximum allowed amplitude Vc of the sinusoids are calculatedusing (6.39) as 1.92 V (3.84 V peak-to-peak), due to the scaling factor Kc

dened in Section 6.2.2. Recall, by scaling the amplitudes of the modulatorreference waveforms with respect to the generator shaft speed, the amplitudesof the fundamental stator voltages are also scaled and thus the generator isoperated below or at rated ux. Saturation currents within the generator arethus avoided. The measured modulator sinusoids are shown in Fig. 7.3.



TEST RESULTS 121

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5−1

−0.5

0

0.5

1

Time (s)

v ref

(V)

vruvrvvrv

Figure 7.2: Measured modulator reference waveforms at an increasing genera-tor shaft speed.

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1−2

−1

0

1

2

Time (s)

v ref

(V)

vruvrvvrw

Figure 7.3: Measured modulator reference waveforms at a shaft frequency of25 Hz.

The measured peak-to-peak voltages of the three waveforms shown in Fig. 7.3are 3.83 V, 3.78 V and 3.80 V, respectively, closely matching the designedvoltage of 3.84 V. The amplitudes of the three sinusoids are close to, but notidentical to each other. This indicates a small margin of error introduced bythe op-amp and resistor circuit that is used to remove the dc oset and add again of 2 to each of the DAC outputs. The gain of each sinusoid is thus slightlygreater or lower than two, resulting in the small voltage error. The resultingphase currents will thus also vary ever so slightly in error. The small error incurrent and voltage will not stop the generator from operating as required.

The measured frequency of each of the waveforms shown in Fig. 7.3 is23.7 Hz corresponding to a slip of -5.47 %, thus matching the designed slip of-5.47 %.

Similarly at a shaft frequency of 50 Hz, the maximum allowed sinusoidalvoltage is 7.69 V peak-to-peak. The measured sinusoidal modulator reference



TEST RESULTS 122

waveforms at a shaft frequency of 50 Hz are shown in Fig. 7.4. The peak-to-peak voltages are measured as 7.65 V, 7.58 V and 7.6 V, respectively. Thevoltages are close to the designed maximum voltage of 7.69 V. The referencewaveform frequencies are measured as 47.4 Hz corresponding to the designedslip of -5.47 %.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

·10−2

−4

−2

0

2

4

Time (s)

v ref

(V)

vruvrvvrw

Figure 7.4: Measured modulator reference waveforms at a shaft frequency of50 Hz.

The dsPIC and DAC are seen to function as designed and deliver the correctmodulator reference voltage waveforms at various measured generator shaftspeeds. From Fig. 7.3 and Fig. 7.4 it can be seen that the digitally generatedsinusoids look very much like analog signals, indicating the resolution chosenfor the digital sinusoids is adequate.

Lastly, when the generator shaft frequency exceeds the maximum frequencyof 75 Hz, the orange warning LED switches on and the reference waveformsgradually reduce until reaching peak-to-peak values of zero.

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

−0.4

−0.2

0

0.2

0.4

Time (s)

v ref

(V)

vruvrvvrw

Figure 7.5: Measured modulator reference waveforms after the operating shaftspeed range was exceeded.



TEST RESULTS 123

Similarly when the shaft frequency was slightly reduced to a value below 75 Hz,the reference waveforms were seen to gradually return to an amplitude of 5 Vas shown in Fig. 7.5. The warning LED switched o and normal switchingoperation continued.

7.2.2 Triangular Carrier Waveform

The triangular carrier waveform used for comparison with the sinusoidal refer-ence waveforms, was designed to have a frequency of 20 kHz and a peak-to-peakvoltage of 12 V. The measured carrier waveform is shown in Fig. 7.6.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

·10−4

−6

−3

0

3

6

Time (s)

v r(V

)

Figure 7.6: Measured triangular carrier waveform.

The measured frequency is 20 kHz and the peak-to-peak voltage is 11.9 V. Theamplitude of the triangular wave is thus 5.95 V. The measured result comparesextremely well to the designed carrier waveform detailed in Section 6.1.

7.2.3 Switching Signals

The measured PWM switching signals generated by the inverter control cir-cuitry for the IGBTs in one half-bridge are shown in Fig. 7.7.

The switching signal of S1 is complementary to S2, as designed. At theinstance of the measurement the duty cycle for S1 was 68.4 % and 26.6 % forS2. The implementation of the dead-time can clearly be seen in Fig. 7.7 dueto the small time period during which both switches are o. The dead-timewas set to 1.2 µs and was chosen as such to avoid any IGBT shoot-throughcurrents.

Similar PWM signals were generated for the other two half-bridges contain-ing switches S3 through S6. The duty cycles vary sinusoidally and in phasewith the modulator reference voltage waveforms, as expected.



TEST RESULTS 124

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

0

2.5

5

Time (s)

SwitchingSingals(V

)S1S2

Figure 7.7: Measured PWM switching signals for one inverter half-bridge.

At a maximum reference waveform amplitude of 5 V and a 5.95 V ramp waveamplitude, the maximum modulation index is 0.84. From (6.8) the maximumduty cycle is thus limited to 92 %.

7.2.4 IGBT Gate Signal

The push-pull oscillator circuit used to power the gate driver IC that communi-cates the switching signal to the gate of the IGBT, was determined to oscillateat a frequency of 309 kHz. The optocoupler supply voltage was measured as16.4 V, close to the designed voltage of 16.5 V.

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

0

2

4

PWM

Signal(V

)

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

0

5

10

15

Time (s)

GateSignal(V

)

Figure 7.8: Measured controller and gate PWM switching signals.



TEST RESULTS 125

At a generator shaft frequency below 7 Hz or above 75 Hz, the duty cycleof all the switches change to a constant value of approximately 50 %, sincethe reference waveforms have reduced to a constant zero volt signal. Themeasured PWM switching signal for S1, as well as the signal at the gate ofthe corresponding IGBT, are shown in Fig. 7.8 at a generator shaft frequencybelow 7 Hz.

The measured duty cycles for both the PWM control signal and the gatesignal were 47.6 %. Due to the dead-time the duty cycles are slightly lowerthan the ideal 50 %. The signal at the gate of the IGBT has a maximumvoltage of 16.3 V corresponding to the gate driver IC supply voltage of 16.4 V.

7.3 Current Simulation and Test Results

The PWM gate drive signals produce PWM voltages at the three pole points ofthe inverter. These voltages are also applied to the generator stator terminalswith their fundamental component at a lower frequency than the measuredshaft frequency. Due to the constant -5.47 % slip operation, current is inducedin the rotor of the generator and current will ow out of the generator into thedc bus.

The outer voltage control loop will demand a current of no greater than5.7 A when a 2 kW load is connected between the dc bus rails, thus no powerows into the batteries to allow them to charge. As soon as the load is removedor its resistance increases, current ows into the batteries and the batteryvoltage rises to above 260 V. In return less current is demanded by the voltagecontrol loop and the battery voltage progressively settle. The batteries arefurther charged slowly and the mean dc bus current gradually decreases, underthe control of the two control loops.

The phase currents and dc bus current were simulated in MATLAB at themaximum allowed mean dc bus current as well as at a lower dc bus current,such as while the batteries are charging. The results are presented in thissection and the time domain analysis showing the stability of the system is alsodiscussed. The corresponding measurements of these currents are presentedand compared with the simulated results.

Without a 2 kW load connected between the dc bus rails, the dc bus currentis shown to ow into the converter to charge the batteries.

7.3.1 Inverter Phase Currents

Initially no load is connected between the dc bus rails. The battery voltagebegins to rise as soon as the bus current rises, since the batteries are beingcharged. The inverter phase current measurements were taken once the batteryvoltage started to settle at a voltage of 266.1 V and a mean dc bus current



TEST RESULTS 126

of 3.3 A. For comparison purposes the simulation was repeated under theseconditions.

The simulated phase currents are shown in Fig. 7.9 at a set-point voltagecorresponding to a mean dc bus current of 3.3 A and a generator shaft fre-quency of 50 Hz. The corresponding measured phase currents are shown inFig. 7.10.

0 1 2 3 4 5 6 7 8

·10−2

−10

0

10

Time (s)

i p(A

) iuiviw

Figure 7.9: Simulated inverter phase currents at a 3.3 A dc bus current set-point.

0 1 2 3 4 5 6 7 8

·10−2

−10

0

10

Time (s)

i p(A

) iuiviw

Figure 7.10: Measured inverter phase currents at a measured dc bus currentof 3.3 A.

The simulated phase currents each have an rms value of 7.5 A and a frequencyof 47.4 Hz. The rms values of the three measured phase currents are 8.99 A,8.89 A and 8.95 A, respectively. As indicated by the measured modulatorreference waveforms, the phase currents will also vary slightly in magnitude.The frequency of the measured phase currents are 47.5 Hz each. From Fig. 7.10it can be seen that the measured phase currents are not pure sinusoids. This



TEST RESULTS 127

is due to the fact that the inductance of the generator is, in reality, a functionof the currents passed through the generator windings due to the non-linearmagnetic permeability of the rotor and stator core material. As a generalrule the permeability of the ferromagnetic core material is seen to decline asthe generator line currents increase. We thus observe the distorted sinusoidalphase currents in response to the application of sinusoidal fundamental phasevoltages to the generator stator terminals.

Both the simulated and measured phase currents indicate a constant gener-ator slip of approximately -5.47 %, as designed for. The rms value of the simu-lated and measured phase currents does however dier by approximately 1.5 A,indicating the equivalent generator impedance is lower than the impedance ap-proximated by the equivalent induction machine model derived in Chapter 5.A margin of error was expected since the parameters of induction machineschange with a change in temperature and operating frequency (slip) [42], [43].

The simulated and measured phase current ripple are shown in Fig. 7.11and Fig. 7.12, respectively. The simulated current ripple has a peak-to-peakvalue of 0.22 A. The measured current ripple has a peak-to-peak value of0.356 A. The measured current ripple is larger than the simulated currentripple conrming the statement that the true machine inductance is lowerthan the values calculated in Chapter 5 from the approximate machine model.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

·10−4

8.2

8.4

8.6

8.8

9

Time (s)

i u(A

)

Figure 7.11: Simulated inverter phase current ripple.

The frequency of both the simulated and measured current ripple is 20 kHzcorresponding to the 20 kHz switching frequency of the IGBTs. The measuredripple current is shown to have a signicant amount of high-frequency noisesuperimposed on the signal. This noise is not real and is simply due to thenoise picked up by the LEM current probe while taking the measurement.The two induction machines, VSD, dc-dc converter and inverter all operatingat dierent frequencies and thus a signicant amount of noise is produced,which is easily picked up by measuring equipment. One of the most signicantsources of radiated noise was determined to be the commercial VSD used tocontrol the motor coupled to the shaft of the generator.



TEST RESULTS 128

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

7.8

8

8.2

8.4

Time (s)

i u(A

)

Figure 7.12: Measured inverter phase current ripple.

The simulated modulator reference waveform for switches S1 and S2 is shownin Fig. 7.13, along with the corresponding phase current iu at a mean dcbus current of 3.3 A. The modulator reference voltages are in phase with thefundamental component of the inverter phase voltages, if the modulator circuitis considered ideal. The modulator reference waveforms can thus be used todetermine the phase angle between the phase currents and voltages. As seenfrom Fig. 7.13 the current is leading the modulator reference voltage and thephase angle was determined from the simulation as 35.82°.

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−2

−4

−2

0

2

4

Time (s)

v ru(V

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−2

−12

−6

0

6

12

i u(A

)

Figure 7.13: Simulated modulator reference voltage and phase current for oneinverter half-bridge.

The measured phase current iu and the modulator reference waveform forswitches S1 and S2 are shown in Fig. 7.14. Since the inverter phase volt-age waveforms are modulated, their fundamental waveforms are not easilymeasured. Although the modulator circuit itself is not ideal, the phase shiftbetween the fundamental phase voltages and currents are approximately equalto the phase shift between the measured modulator reference waveforms and



TEST RESULTS 129

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−2

−3

−2

−1

0

1

2

3

Time (s)

v ru(V

)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

·10−2

−15

−10

−5

0

5

10

15

i u(A

)

Figure 7.14: Measured modulator reference voltage and phase current for oneinverter half-bridge.

the phase current waveforms. From Fig. 7.14 the current is shown to lead themodulator voltage by 35.88°.

The amplitude of the modulator reference waveform is seen to dier for thesimulated and measured case shown in Fig. 7.13 and Fig. 7.14, respectively.This is because the dc bus current is regulated to 3.3 A and, as already shown,the measured phase currents are larger than the simulated phase currents.Thus, a lower modulator reference voltage is required to produce 3.3 A ofcurrent owing in the dc bus for the measured case.

Once the 2.1 kW load is connected, the battery voltage reduces to below260 V since the batteries as well as the generator is used to supply power tothe load. The set-point generated by the voltage control loop increases to 5 V(5.7 A). At a shaft frequency of 34 Hz the corresponding measured modulatorvoltage and phase current are shown in Fig. 7.15.

From Fig. 7.15 the modulator reference voltage is shown to peak at 2.5 Vand the measured frequency is 32.1 Hz. The maximum allowed reference volt-age is 2.6 V at a shaft frequency of 34 Hz. The corresponding phase current hasan rms value of 11.99 A. The power angle is measured as 36.9°. The phase shiftis thus seen to remain constant with a change in frequency when compared tothe power angle of 35.88° at a shaft frequency of 50 Hz.

The amplitudes of the phase currents will remain reasonable constant overa wide generator shaft speed range since both the fundamental stator volt-ages and generator impedance change with speed. From measurements it wasseen that at low shaft speeds (below approximately 20 Hz) this voltage andimpedance relationship does not remain constant and the amplitude of thephase currents will change signicantly as a function of the shaft speed.



TEST RESULTS 130

0 1 2 3 4 5 6 7 8 9 10

·10−2

−3

−2

−1

0

1

2

3

Time (s)

v ru(V

)

−18

−12

−6

0

6

12

18

i u(A

)

Figure 7.15: Measured modulator reference voltage and phase current at ashaft frequency of 34 Hz.

7.3.2 Bus Current

The time domain analysis of the dc bus current during start-up is shown inFig. 7.16 for a maximum current loop set-point of 5 V. The simulation wasconducted at a shaft frequency of 50 Hz. The amplitudes of the modulatorreference waveforms were gradually increased as discussed in Section 7.2.1. Thedc bus current is shown to increase with an increase in the applied inverterphase voltages, as expected. After 2.42 s, the dc bus current is shown to reachthe desired mean dc bus current value of 5.7 A. A small current overshoot of0.4 A follows with the dc bus current thus peaking at 6.1 A. After a total of2.6 s the dc bus current is shown to have settled to the desired value of 5.7 A.

0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 30

2

4

6

8

Time (s)

I dc(A

)

MeasuredSet-point

Figure 7.16: Simulated dc bus current during generator start-up.

The time domain analysis shows the dc bus current will settle at the desiredcurrent set-point without a large current overshoot (less than 7.1 %). Thesystem is seen to be stable and able to supply the current required by theouter control loop.



TEST RESULTS 131

The VSD controlling the motor (used to turn the generator shaft) was set toaccelerate the frequency of the stator voltages applied to the motor over aperiod of 10 s to avoid saturation currents in the motor. The slow accelerationof the generator shaft combined with the gradual increase of the amplitudes ofthe modulator reference waveforms cause the measured dc bus current to rampup slowly and with a maximum current overshoot of approximately 0.1 A topeak at 5.8 A. The motor is decelerated in a similar manner using the VSD.

In practice the dc bus current set-point will never experience a step responseafter start-up, since the outer voltage control loop is set to react very slowly(due to the batteries charging slowly) and hence the set-point generated byvoltage control loop will change gradually, allowing the dc bus current to follow.This response is detailed in the next section.

The measured dc bus current under steady state conditions is shown inFig. 7.17 at a maximum set-point of 5 V, corresponding to 5.7 A, and a gen-erator shaft frequency of 50 Hz. The mean value is measured as 5.66 A whichclosely match the desired value of 5.7 A. The error is due to a small inaccu-racy in the current sensing circuit. With a regulated 355 V dc bus, the powerrequirement of 2 kW is still met. The inverter and generator circuit is thusable to supply 2 kW of power to the dc bus.

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

4

5

6

7

8

Time (s)

i dc(A

)

Figure 7.17: Measured dc bus current at the maximum set-point current.

The dc bus current is shown to have a fundamental frequency of 20 kHz with a40 kHz component also present. The inverter is switching at 20 kHz while thedc-dc converter is switching at 40 kHz accounting for the additional frequencycomponent. The ripple in the dc bus current is seen to have a peak-to-peakvalue of 2.75 A. An increase or decrease in the amplitudes of the three in-verter phase currents will result in a corresponding increase or decrease in thepeak-to-peak dc bus current ripple.

Due to the diculty in measuring the fundamental component of the in-verter phase voltages, the inverter eciency was not determined. A poweranalyser of some sort is required to accurately measure the eciency of such



TEST RESULTS 132

a circuit. The lab facilities available for this project did unfortunately notcontain any power analysers.

The dc bus current was also measured whilst charging the batteries. Themeasurement was taken along with the already presented phase current mea-surements at a mean dc bus current of 3.3 A as shown in Fig 7.18. The ripplecurrent has a peak-to-peak magnitude of 1.94 A, which is lower than that ofthe previous dc bus current measurement, as expected.

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2

·10−4

2

3

4

5

Time (s)

i dc(A

)

Figure 7.18: Measured dc bus current whilst charging the batteries.

The dc bus current control loop is shown to be stable and able to regulate thecurrent owing into the dc bus eectively. The power transfer requirement of2 kW is also shown to be met by the prototype circuit.

7.3.3 Battery Current

The measured current owing into the batteries at a mean dc bus current ofapproximately 3.3 A is shown in Fig. 7.19. The battery current is shown tohave a mean value of 4.8 A and a peak-to-peak current ripple of 2.04 A at afrequency of 40 kHz.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

·10−4

3

4

5

6

Time (s)

i L(A

)

Figure 7.19: Measured battery current whilst charging the batteries.



TEST RESULTS 133

The inductor current ripple is seen to be lower than the designed value of2.25 A even if the inductor is experiencing greater magnetisation which wouldincrease the current ripple. This is simply due to the battery voltage thatincreased to 266.1 V from the nominal value of 240 V (12 V per battery). Thevoltage across the inductor is thus less than before when switches Q1 and Q4

are closed, resulting in a smaller current ripple. The duty cycle of switchesQ1 and Q4 are also seen to have changed slightly to 70 % as opposed to theprevious value of 68.57 %.

The dc-dc converter is thus shown to be bidirectional since it can accom-modate current ow to as well as from the dc bus. The results showing powerow from the batteries to the dc bus were already presented in Chapter 4.

7.4 Bus Current and Battery Voltage

Relationship

The results of the outer voltage control loop used to regulate the batteryvoltage are presented in this section. As the battery voltage increases, the dcbus current should decrease until such point where the current supplied bythe generator is just enough to keep the batteries at their oating use voltageof 272 V to 276 V. Both the simulated and measured response of the dc buscurrent with respect to the state of charge of the batteries are presented anddescribed.

7.4.1 Simulated Response

The time domain simulation only deals with the electrical properties of thebatteries, thus the batteries were modelled as a constant voltage source with aninternal resistance, as detailed in Chapter 6. In order to observe the change indc bus current as a function of the battery voltage in the simulation, the batteryvoltage (modelled as the constant voltage source) was increased linearly overa time period of 7 s.

To provide a better approximation of the battery's response to sinkingcurrent, the battery voltage was simulated to increase from 240 V (nominally12 V per battery) to 265 V over a period of 3 s and then increase slowly to272 V over the next 4 s. The results are shown in Fig. 7.20.

Initially the set-point current corresponds to 5.7 A as indicated in Fig. 7.20.The dc bus current is ramped up as explained in Section 7.3.2. At the sametime the battery voltage is seen to rise gradually. After 3 s the battery voltageexceeds 260 V and the current set-point is shown to decline. The simulated dcbus current is seen to respond to the change in the current set-point. Whenthe battery voltage reaches 265 V the batteries start charging at a lower rate.The current set-point is seen to also decline at this lower rate, with the dc buscurrent following its response. Once the battery voltage reaches the desired



TEST RESULTS 134

0 1 2 3 4 5 6 7−202468

I dc(A

)

MeasuredSet-point

0 1 2 3 4 5 6 7240

250

260

270

280

Time (s)

Vba

t(V

)

Figure 7.20: Simulated mean dc bus current and battery voltage.

value of 272 V, the current set-point reaches zero, thus demanding zero current.The dc bus current is also seen to reduce to the desired value of zero.

The time domain simulation predicts that both the voltage and currentcontrol loops of the inverter are stable.

7.4.2 Measured Response

Due to the time duration required for the batteries to charge, the measurementcould not be obtained as a single measurement using an oscilloscope. The meanbattery voltage was measured at regular intervals with a multimeter and themean dc bus current was measured with an Avometer as well as as with a LEMcurrent probe, to conrm the measurement. As soon as the generator startedto deliver power to the dc bus (a load was not connected between the dc busrails), the battery voltage was seen to increase rapidly to above 260 V. Theresults were taken from a battery voltage of 260 V and are shown in Fig. 7.21.The measurements were taken with the batteries drained beforehand to a valueof approximately 11.92 V per battery.

The results given in Fig. 7.21 show the mean dc bus current does in factdecrease as the mean voltage of the batteries increases, as desired. Initiallythe dc bus current is seen to peak at 5.8 A while the dc bus voltage increasesrapidly. The gain used in the voltage compensation amplier is sucient todemand 5.7 A of current up to a measured battery voltage of 260 V. Thereafterthe demanded current is decreased as shown in Fig. 7.21.

The current is seen to drop at approximately the designed rate until thebattery voltage reaches 265 V. Thereafter the battery voltage starts to settle



TEST RESULTS 135

260 261 262 263 264 265 266 267 268 269 270 271 2721

2

3

4

5

6

Vbat (V)

I dc(A

)

Figure 7.21: Measured mean dc bus current vs battery voltage.

and requires more current than predicted to continue charging the batteries.From Fig. 7.21 the voltage is seen to never reach exactly 272 V, it remainssomewhere between 271 V and 272 V. Similarly the dc bus current is seen toreach a minimum value of approximately 2.1 A. The battery voltage and dcbus current thus reach equilibrium at these values. The equilibrium values canchange with a change in temperature, since the storage capacity of batteriesare temperature dependent.

The simulation predicted that the dc bus current will drop to zero at abattery voltage of 272 V. In practice the battery voltage will never actuallyreach 272 V but will remain very close to 272 V as long as the necessary currentis supplied to keep it there, thus trickle charging the batteries. The internalresistance of the batteries as well as the eciency of the converter causes thedc bus current to remain above zero in order to keep the batteries at theiroptimal oating use voltage of 272 V.

The last few measurements were taken approximately 30 minutes from eachother. In total the batteries where charged for approximately 8 hours to reacha voltage of 271.5 V. If the batteries are charged even longer, the internalbattery resistance will decrease even further and the required dc bus currentwill decrease slightly.

Overall the inverter control circuit is shown to be stable and provides thedesired controller responses. The dc-dc converter prototype circuit was suc-cessfully integrated with the inverter prototype circuit. The mean dc buscurrent provided by the generator is successfully controlled as a function ofthe measured battery voltage, with the batteries connected to the dc-dc con-verter. The overall system is also shown to be stable under various operatingconditions (with or without a load connected).



TEST RESULTS 136

7.5 Safety Features Testing

The safety features detailed in Chapter 6 were implemented in the inverterprototype circuit. The soft turn-on and turn-o feature of the amplitudes ofthe modulator reference waveforms when the generator shaft speed exceeds theoperating speed range (above 75 Hz or below 7 Hz), were already presentedand discussed in Section 7.2.1. The correct LED also turned on to visuallyindicate why the generator cannot supply current to the dc bus.

A green LED was also mounted on the PCB containing the dsPIC. TheLED was programmed to turn on and o at 0.5 s intervals. If the LED stopsashing it indicates the dsPIC is either not receiving power or has fallen intoa continuous loop where the low priority interrupt to turn the LED on and ocan never be reached. This provides a visual method to indicate if the controlcircuit is switched on and to see if the dsPIC itself is experiencing any majorproblems. The other safety features were also tested and is discussed in thissection.

7.5.1 Over-Temperature Protection

The over-temperature detection was tested using an external input to simulatethe temperature output from the thermistor circuit. At a voltage of 3.35 V(the designed threshold voltage) the over-temperature sensor tripped and thered LED was switched on by the dsPIC. At the same time all switching actionwas terminated as desired. The mean dc bus current was seen to drop andafter a few seconds it reached zero. The switching action only resumed afterthe dsPIC was reset. Similarly the red LED only turned o once the dsPICcircuit was restarted.

7.5.2 Overcurrent Protection

The overcurrent protection is supplied by the gate driver IC (ACPL-332J)which detects the Vce voltage of the IGBTs. The larger the currents throughthe collector of the IGBT, the higher the measured Vce voltage. The IGBTmodule was tested before using it in the fully functional inverter circuit to seethat the fault output from the gate driver IC tripped when large currents wereowing through the IGBT collector. The fault output was observed to changestate thus indicating it functioned correctly.

Initially the dead-time for the IGBT switches was set to 800 ns. Theinverter circuit was able to function as desired but after a while, when theIGBT module started to heat up, shoot-through currents were detected dueto the increased turn-on and turn-o times of the switches. The overcurrentprotection provided by the gate driver IC sent a fault signal to the dsPIC whileactivating the soft switch turn-o feature built into the chip. The orangeLED was turned on by the dsPIC. Similarly as with the over-temperature



TEST RESULTS 137

fault condition, the switching action was terminated. The control circuit wasrestarted to allow the switching action of the IGBTs to resume and to allowthe LED to turn o. The dead-time was subsequently increased to 1.2 µs.

7.5.3 Overvoltage Protection

The overvoltage protection was tested using an external input to simulatethe dc bus voltage feedback. As soon as the simulated scaled dc bus voltageexceeded 5 V, the output of the comparator was shown to change state, thusthe overvoltage protection circuitry was triggered. The IGBT switching actionwas once again terminated as with the other protection features. The reversebiased diodes connected across the collector and emitter of each IGBT stillprovide a path for the generator current to ow, but as soon as the switchingaction of the IGBTs are terminated the voltage applied to the generator statorterminals are also terminated. With no voltage applied to the generator statorterminals the induced current immediately reduces and after a few seconds(less than 5 s) the mean dc bus current reaches zero.

The dc bus voltage will thus not rise to a high enough voltage to damageany of the components used in the inverter and converter prototype circuits.All of the high voltage components are rated to operate continuously at avoltage of at least 400 V. The IGBT switching action is resumed after thedsPIC is restarted.

7.6 Summary

The performance of both the inverter and dc-dc converter prototype circuitswere presented in this chapter with the main focus on the integration betweenthe two circuits. The test set-up and start-up procedure to test the completesystem was described in detail. The generation of the gate-drive signals used tocontrol the switching action of the IGBTs was presented using measurements.The inverter phase currents and dc bus current were presented in order todemonstrate the correct operation of the designed inverter current loop whencompared to the simulated response. The measured battery current used tocharge the batteries was given indicating that the dc-dc converter is in factbidirectional. The test results showing the relationship between the mean dcbus current and measured battery voltage were presented and the integrationof the dc-dc converter and inverter circuits were proven to be successful. Theinverter protection circuitry was shown to function properly and provide thenecessary protection for which it was designed.


Chapter 8

Conclusions

A summary of the work presented in this thesis along with the results are givenin this chapter. Recommendations with regard to the research conducted arediscussed and possible future work is considered.

8.1 Thesis Conculsions

A circuit that demonstrates the interface between an asynchronous generator,a battery of electrochemical cells, and an electrical load was proposed. Thisthesis presented the successful design and implementation of such a circuit.

The circuit was designed such that the battery connects to a dc bus througha bidirectional dc-dc converter, and the asynchronous generator connects tothe same dc bus through a bidirectional inverter. A positive and a negative dcbus rail were used and the load was connected between the two bus rails.

The bidirectional dc-dc converter circuit was successfully designed to reg-ulate the dc bus to 355 V rail-to-rail (within the design specication) by em-ploying two control loops, an inner current control loop and an outer voltagecontrol loop. The inner current control loop was used to control the amountof current owing into or out of the converter's batteries as a function of theset-point generated by the outer control loop that regulates the dc bus voltage.Both frequency and time domain analysis conrmed the closed-loop stabilityof the system.

The converter was practically implemented by manufacturing PCBs to con-struct the prototype circuit. The converter circuit used a half-bridge topologyconsisting of MOSFETs as switches, which were controlled using pulse-widthmodulation. A two-stage soft-start circuit was successfully implemented toavoid in-rush currents during start-up through the reversed biased diodes ofthe MOSFETs.

The transfer of up to 2.1 kW of electrical power between the batteries anddc bus was demonstrated by powering a 2.1 kW load connected between the dcbus rails. The step response of the converter circuit was tested and excellent

138


CHAPTER 8. CONCLUSIONS 139

transient response was demonstrated. Overall the simulated and test resultscompared extremely well. The converter also showed a high eciency of 94 %.

The asynchronous generator, controlled by the inverter circuit, was success-fully modelled in a computer simulation when compared to the given datasheetinformation.

The detailed design of the bidirectional inverter circuit used to interfacethe asynchronous generator and the dc bus was presented and implemented.The switching action of the IGBTs used in the inverter circuit were controlledusing two control loops. The inner control loop was used to successfully controlthe magnitude of the current owing into the dc bus while the outer controlloop was used to regulate the converter's battery voltage. Both frequency andtime domain analysis showed the closed-loop inverter system to be stable.

A dsPIC digital signal processor was used along with a digital-to-analogconverter to produce the required sinusoidal modulator reference waveformsfor the inverter switches. A magnetic pick-up was used to determine the speedof the generator shaft and the result was processed inside the dsPIC. Thegenerator was shown to function as desired when operated at a constant slipof -5.47 % using current as well as Volt/Hertz control. The generator was ableto supply 2 kW of electrical power to the dc bus when a load was connectedbetween the bus rails.

The integration of the dc-dc converter circuit and inverter circuit was suc-cessfully implemented. The generator was shown to supply power to the dc-dcconverter circuit in order to charge the batteries to their optimal oating usevoltage of 272 V. The bidirectional capability of the dc-dc converter circuitwas thus proven.

The test results showed that as the battery voltage increased, the demandeddc bus current decreased, indicating the inverter control loops functioned asdesired. The dc bus current reached a minimum demanded value of 2.1 A,which was the necessary current required to keep the battery voltage at ap-proximately 272 V, thus trickle charging the batteries.

The prototype circuits showed that the induction generator can be con-trolled as a function of the dc-dc converter's battery voltage by making useof the presented dc-dc converter and inverter circuits. The overall systemperformance was shown to meet all the design specications.

8.2 Recommendations and Future Work

The prototype circuit was tested using another asynchronous machine to drivethe shaft of the generator. It is recommended that a turbine driven by airowis used to drive the generator shaft in future as this is the intended application.

If the system is desired to be used as a stand-alone system, it will requirea separate battery to power all the control and gate-drive circuitry.


CHAPTER 8. CONCLUSIONS 140

Although the prototype circuit was able to charge the batteries, a batterymanagement system should be considered to allow the state of charge of thevarious converter batteries to remain the same. Dierent charging algorithmsshould be investigated in order to nd the optimal battery charging solution.As an alternative to using lead-acid batteries, the use of lithium-ion batteriesas well as supercapacitors could be investigated.

A dierent IGBT module should be considered for the inverter circuit.The chosen module has a very high junction-to-case and case-to-sink thermalresistance. The resulting IGBT operating junction-to-ambient temperature isvery high and the inverter circuit will not be able to function in areas with anambient temperature above 40°C to 45°C.

The prototype circuit was designed as a concept demonstrator for a circuitused on board an aircraft to supply power to an electrical load. The circuitcan however also be used to supply power to small loads in remote areas byreplacing the RAM air turbine with a wind turbine. This could serve as arenewable energy solution in areas without access to the local power grid.


List of References

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[2] P. Bolognesi, F. Papini, and L. Taponecco, Hybrid-excitation dc machinesas highly reliable generators for ram air turbines, in Industrial Electron-ics, 2009. IECON '09. 35th Annual Conference of IEEE, Nov 2009, pp.25692574.

[3] X. Roboam, O. Langlois, H. Piquet, B. Morin, and C. Turpin, Hybridpower generation system for aircraft electrical emergency network, IETElectrical Systems in Transportation, vol. 1, no. 4, pp. 148155, December2011.

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LIST OF REFERENCES 142

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Appendices

146


Appendix A

Complete Circuit Schematics

A.1 DC-DC Converter Circuit Schematics

All of the circuit diagrams used for the implementation of the bidirectionalcurrent-controller voltage-regulated dc-dc converter prototype circuit are givenin this section.

A.1.1 Power Stage Schematics

The schematics for the power stage of the dc-dc converter are given in thissection. It includes the half-bridge converter topologies, gate-drive circuitryand pre-charge soft-start mechanisms. The schematic for the top-half of theconverter is shown in Fig. A.1 and the schematic for the bottom half is shownin Fig. A.2.

147


APPENDIX A. COMPLETE CIRCUIT SCHEMATICS 148

11

22

33

44

55

66

77

88

DD

CC

BB

AA

D1

BA

T85

D2

BA

T85

Q2

BC

556

Q1

BC

556

T1 1:1

C1

100p

F

C2

100p

F

R1

0.22

K

R2

0.22

K

R3

1M

Ano

de2

Cat

hode

3

SGND 5

Vo(

B)

6V

o(A

)7

SVCC8

IC1

TLP2

50

R4

0.22

K

C3

100u

F

M1

IRFP

264

R5

27oh

m

+12V

D3

BA

T85

D4

BA

T85

Q4

BC

556

Q3

BC

556

T2 1:1

C4

100p

F

C5

100p

F

R6

0.22

K

R7

0.22

K

R8

1M

Ano

de2

Cat

hode

3

SGND 5

Vo(

B)

6V

o(A

)7

SVCC8

IC2

TLP2

50

R9

0.22

K

C6

100u

F

M2

IRFP

264

R10

27oh

m

+12V

1 2

CO

N1

PWM

1 1 2

CO

N2

PWM

2

PWM

1

PWM

2

L1 406u

H

1 2 3

CO

N3

BA

TTER

Y

R11

R12

0E68

R13

R14

R15

R16

R17

R18

R19

R20

R21

PWM

1

PWM

2

K1

Rel

ay

C11

1mF

Vs+

1 2

CO

N4

LOA

D

1

3

BA

L/ST

B6

BA

L5

V-

42

7

V+

8IC

3

LM31

1P

12

CO

N5

CS

Sign

al

+12V

Vs+ R

2222

0K

R24

10K

+12V

R26

1K

D5

5V6

D6

1N40

07

C8

100n

F

C9

100n

F

C10

100n

F

C7

100n

F

C12

1mF

R27

R28

R29100ohm

R30

4K7

R31

4K7

C13

100n

F

C14

100n

F

C15

10uF

SGN

D1

SGN

D1

SGN

D2

SGN

D2

D7

1N41

48

1 2

CO

N6

VS

Sign

al

+12V

1 2

CO

N7

12V

Sup

ply

0V

0V

0V

0V0V

GN

D

R23

2K

R32

10K

Q5

2N22

19A

D8

BY

V96

E

D9

BY

W96

E

D10

BY

W96

E

0V+12V

PIC101

PIC1

02

COC1

PIC201

PIC202

COC2

PIC301 PIC302COC

3

PIC401

PIC4

02

COC4

PIC501

PIC502

COC5

PIC601 PIC602COC

6

PIC701PIC702COC

7

PIC801PIC802COC

8

PIC901PIC902COC

9

PIC1001PIC1002COC10

PIC1101 PIC1102

COC11

PIC1201 PIC1202

COC12

PIC1301PIC1302COC13

PIC1401PIC1402COC14

PIC1501 PIC1502

COC15

PICON101

PICON102

COCON1

PICON201

PICON202

COCON2

PICO

N301

PICO

N302

PICO

N303

COCON3

PICON401

PICON402CO

CON4

PICON501PICON502

COCON5

PICO

N601

PICO

N602

COCON6

PICON701

PICON702

COCON7

PID101

PID102

COD1

PID201

PID202

COD2

PID301

PID302

COD3

PID401

PID402

COD4

PID501PID502CO

D5

PID601PID602CO

D6

PID701PID702CO

D7

PID801PID802CO

D8

PID901PID902COD

9

PID1001PID1002COD10

PIIC102

PIIC103

PIIC105

PIIC106

PIIC107

PIIC108COIC1

PIIC202

PIIC203

PIIC205

PIIC206

PIIC207

PIIC208COIC2

PIIC301

PIIC302

PIIC303

PIIC

304

PIIC305

PIIC306

PIIC307

PIIC308

COIC3

PIK101 PIK102

PIK103 PIK104

COK1

PIL101

PIL1

02

COL1

PIM101

PIM102 PIM103CO

M1

PIM201

PIM202 PIM203CO

M2

PIQ101PIQ102

PIQ103CO

Q1

PIQ201PIQ202

PIQ203 COQ2

PIQ301PIQ302

PIQ303CO

Q3

PIQ401PIQ402

PIQ403 COQ4

PIQ501

PIQ502 PIQ503COQ5

PIR101

PIR102

COR1

PIR201

PIR202

COR2

PIR301PIR302 COR3

PIR401PIR402 COR4

PIR501

PIR502

COR5

PIR601

PIR602

COR6

PIR701

PIR702

COR7

PIR801PIR802 COR8

PIR901PIR902 COR9

PIR1001

PIR1002

COR10

PIR1101PIR1102 COR11

PIR1

201

PIR1202

COR12

PIR1

301

PIR1302

COR13

PIR1

401

PIR1402

COR14

PIR1

501

PIR1502

COR15

PIR1

601

PIR160

2COR16

PIR1

701

PIR1702

COR17

PIR1

801

PIR1802

COR18

PIR1

901

PIR1902

COR19

PIR2

001

PIR2002

COR20

PIR2

101

PIR2102

COR21


PIR2301PIR

2302PIR2303 CO

R23



PIR2701PIR2702 COR27PIR2801PIR2802

COR28





PIT101PIT102

PIT103PIT104

PIT105PIT106

PIT107PIT108 COT

1

PIT201PIT202

PIT203PIT204

PIT205PIT206

PIT207PIT208 COT

2

PIC702

PIC802 PIC902

PIC1002

PICO

N302

PICON701

PID602PID702

PID802

PIIC305

PIIC306

PIIC308

PIK103

PIQ103PIQ203

PIQ303PIQ403

PIR2602

PIC701

PIC801 PIC901

PIC1001

PIC1502PI

CON3

03

PICON501

PICON702

PID501

PID801

PID901

PIIC

304

PIQ503

PIR301

PIR801

PIR1

201

PIR1

301

PIR1

401

PIR1

501

PIR1

601

PIR1

701

PIR1

801

PIR1

901

PIR2

001

PIR2

101

PIR2401PIR3201

PIT106PIT107

PIT206PIT207

PIC602

PIC1102PIC1202

PIC1401

PICON402

PICON502

PICO

N602

PIIC205

PIM203PIR1202

PIR1302

PIR1402

PIR1502

PIR160

2

PIR1702

PIR1802

PIR1902

PIR2002

PIR2102

PIR3101

PIT202PIT203

PIC101

PIQ101

PIT105

PIC1

02

PIR201

PIR302PIC201

PIR102

PIC202

PIQ201

PIT108

PIC301

PIC1302

PID102

PID202

PIIC108

PIC401

PIQ301

PIT205

PIC4

02

PIR701 PI

C501

PIR602

PIR802PIC502

PIQ401

PIT208

PIC601

PIC1402

PID302

PID402

PIIC208

PIC1501PID701PIIC303

PIR2201

PIR230

2PIR2303

PICON101

PIR402

PICON102

PIIC103

PICON201

PIR902PICON202

PIIC203

PICO

N301

PIK102PIR1101

PIR2701PIR2801

PIR2901

PID101

PIT104

PID201

PIT101

PID301

PIT204

PID401

PIT201

PID502PIIC302

PIR2601PID601

PIIC307

PIK104PIQ502

PID902PID1001

PIK101PIL101

PIR1102PIR2702

PIR2802PIR2902

PIIC102

PIR401

PIIC106

PIIC107

PIR501

PIIC202

PIR901

PIIC206

PIIC207

PIR1001

PIIC301

PIQ501

PIR3202

PIQ102PI

R101

PIQ202

PIR202

PIQ302PI

R601

PIQ402

PIR702

PIR2301 PIR2402

PIM101

PIR502

PIR3002

NLPWM1

PIM201

PIR1002

PIR3102

NLPWM2

PIC302

PIC1301

PIIC105

PIL1

02

PIM103 PIM202

PIR3001

PIT102PIT103

PIC1101PIC1201

PICON401

PICO

N601

PID1002PIM102

PIR2202

Figure A.1: Schematic for the top-half of the dc-dc converter circuit.



11

22

33

44

55

66

77

88

DD

CC

BB

AA

D1

BAT8

5

D2

BAT8

5

Q2

BC55

6Q

1BC

556

T1 1:1

C1 100p

F

C2 100p

F

R1 0.22

K

R2 0.22

K

R3 1M

Ano

de2

Cath

ode

3

SGND 5

Vo(

B)6

Vo(

A)

7

SVCC8

IC1

TLP2

50

R4 0.22

K

C3 100u

F

R5 27oh

m

0V

D3

BAT8

5

D4

BAT8

5

Q4

BC55

6Q

3BC

556

T2 1:1

C4 100p

F

C5 100p

F

R6 0.22

K

R7 0.22

K

R8 1M

Ano

de2

Cath

ode

3

SGND 5

Vo(

B)6

Vo(

A)

7

SVCC8

IC2

TLP2

50

R9 0.22

K

C6 100u

F

M2

IRFP

264

R10

27oh

m

0V

1 2

CON

1

PWM

1 1 2

CON

2

PWM

2

PWM

1

PWM

2

L1 406u

H

1 2 3

CON

3

BATT

ERY

R11

R12

0E68

R13

R14

R15

R16

R17

R18

R19

R20

R21

PWM

2

K1

Rela

y

C11

1mF

1 2

CON

4

LOA

D

1

3

BAL/

STB

6

BAL

5

V-

42

7

V+

8IC

3

LM31

1P

12

CON

5

CS S

igna

l

-12V

-VsR2

222

0K

R24

10K

0V

R26

1K

D5

5V6

D6

1N40

07

C8 100n

F

C9 100n

F

C10

100n

F

C7 100n

F

C12

1mF

R27

R28

R29100ohm

R30

4K7

R31

4K7

C13

100n

F

C14

100n

F

C15

10uF

SGN

D2

SGN

D2

D7

1N41

48

1 2

CON

6

VS

Sign

al

0V1 2

CON

7

12V

Sup

ply

M1

IRFP

264

PWM

1

SGN

D1

SGN

D1

0V

-12V

-12V

-12V

-12V

-Vs

R23

2K

R32

10K

GN

DD

8BY

V96

E

D9

BYW

96E

D10

BYW

96E

Q5

2N22

19A

PIC101

PIC1

02

COC1

PIC201

PIC202

COC2

PIC301 PIC302COC

3

PIC401

PIC4

02

COC4

PIC501

PIC502

COC5

PIC601 PIC602COC

6

PIC701PIC702COC

7

PIC801PIC802COC

8

PIC901PIC902COC

9

PIC1001PIC1002COC10

PIC1101 PIC1102

COC11

PIC1201 PIC1202

COC12

PIC1301PIC1302COC13

PIC1401PIC1402COC14

PIC1501 PIC1502

COC15

PICO

N101

PICO

N102

COCON1

PICO

N201

PICO

N202

COCON2

PICO

N301

PICO

N302

PICO

N303

COCON3

PICO

N401

PICO

N402

COCON4

PICON501PICON502

COCON5

PICON601

PICON602CO

CON6

PICON701

PICON702

COCON7

PID101

PID102

COD1

PID201

PID202

COD2

PID301

PID302

COD3

PID401

PID402

COD4

PID501PID502CO

D5

PID601PID602CO

D6

PID701PID702CO

D7

PID801PID802CO

D8

PID901PID902COD

9

PID1001PID1002CO

D10

PIIC102

PIIC103

PIIC105

PIIC106

PIIC107

PIIC108COIC1

PIIC202

PIIC203

PIIC205

PIIC206

PIIC207

PIIC208COIC2

PIIC

301

PIIC302

PIIC303

PIIC304

PIIC305

PIIC306

PIIC307

PIIC

308

COIC3

PIK101 PIK102

PIK103 PIK104

COK1

PIL101

PIL1

02

COL1

PIM101

PIM102 PIM103CO

M1

PIM201

PIM202 PIM203CO

M2

PIQ101PIQ102

PIQ103CO

Q1

PIQ201PIQ202

PIQ203 COQ2

PIQ301PIQ302

PIQ303CO

Q3

PIQ401PIQ402

PIQ403 COQ4

PIQ501

PIQ502 PIQ503COQ5

PIR101

PIR102

COR1

PIR201

PIR202

COR2

PIR301PIR302 COR3

PIR401PIR402 COR4

PIR5

01PI

R502

COR5

PIR601

PIR602

COR6

PIR701

PIR702

COR7

PIR801PIR802 COR8

PIR901PIR902 COR9

PIR1

001

PIR1

002

COR10


PIR1

201

PIR1

202

COR12

PIR1

301

PIR1

302

COR13

PIR1

401

PIR1

402

COR14

PIR1

501

PIR1

502

COR15

PIR1

601

PIR1

602

COR16

PIR1

701

PIR1

702

COR17

PIR1

801

PIR1

802

COR18

PIR1

901

PIR1

902

COR19

PIR2

001

PIR2

002

COR20

PIR2

101

PIR2

102

COR21


PIR2301PIR2302PIR2303COR23



PIR2701PIR2702COR27

PIR2801PIR2802 COR28PIR2901PIR2902

COR29




PIT101PIT102

PIT103PIT104

PIT105PIT106

PIT107PIT108 CO

T1

PIT201PIT202

PIT203PIT204

PIT205PIT206

PIT207PIT208 COT

2

PIC701

PIC801 PIC901

PIC1001

PICO

N302

PICON702

PID701

PID801

PIIC304

PIQ503

PIR301

PIR801

PIR2601PIR3201

PIT106PIT107

PIT206PIT207

PIC302

PIC1102PIC1202

PIC1301

PICO

N402

PICON602

PID1001

PIIC105

PIM103PIR2201

PIR3001

PIT102PIT103

PIC702

PIC802 PIC902

PIC1002PIC1501

PICO

N301

PICON502PICON701

PID502PID602

PID802PID902

PIIC305

PIIC306

PIIC

308

PIK103

PIQ103PIQ203

PIQ303PIQ403

PIR1

201

PIR1

301

PIR1

401

PIR1

501

PIR1

601

PIR1

701

PIR1

801

PIR1

901

PIR2

001

PIR2

101

PIR2302PIR2303

PIC1101PIC1201

PICO

N401

PICON501

PICON601

PIM202

PIR1

202

PIR1

302

PIR1

402

PIR1

502

PIR1

602

PIR1

702

PIR1

802

PIR1

902

PIR2

002

PIR2

102

PIC101

PIQ101

PIT105

PIC1

02

PIR201

PIR302PIC201

PIR102

PIC202

PIQ201

PIT108

PIC301

PIC1302

PID102

PID202

PIIC108

PIC401

PIQ301

PIT205

PIC4

02

PIR701 PI

C501

PIR602

PIR802PIC502

PIQ401

PIT208

PIC601

PIC1402

PID302

PID402

PIIC208

PIC1502 PID702PIIC302

PIR2202PIR2401

PICO

N101

PIR402

PICO

N102

PIIC103

PICO

N201

PIR902PI

CON2

02

PIIC203

PICO

N303 PIK101

PIR1102PIR2702

PIR2802PIR2902

PID101

PIT104

PID201

PIT101

PID301

PIT204

PID401

PIT201

PID501PIIC303

PIR2602

PID601PIIC307

PIK104PIQ502

PID901 PID1002

PIK102PIL101

PIR1101PIR2701

PIR2801PIR2901

PIIC102

PIR401

PIIC106

PIIC107

PIR5

01

PIIC202

PIR901

PIIC206

PIIC207

PIR1

001

PIIC

301

PIQ501

PIR3202

PIQ102PI

R101

PIQ202

PIR202

PIQ302PI

R601

PIQ402

PIR702

PIR2301 PIR2402

PIM101

PIR5

02

PIR3002

NLPWM1

PIM201

PIR1

002

PIR3102

NLPWM2

PIC602

PIC1401

PIIC205

PIL1

02

PIM102PIM203

PIR3101

PIT202PIT203

Figure A.2: Schematic for the bottom-half of the dc-dc converter circuit.



A.1.2 Control Stage Schematics

The complete control schematic for the top- and bottom-half of the dc-dcconverter circuit is given in this section in Fig.A.3.



11

22

33

44

55

66

77

88

DD

CC

BB

AA

2 31

A8 4

[H(s

)]

IC2A

LF35

3N

Vin

-1

Vin

+2

Vou

t+3

COM

4

Vou

t-5

IC1

DK

E10A

-15

1 2

CON

1

Batte

ry 1

2V

+12V 0V

+15V

-15V

GN

D

+15V

-15V

GN

D

R1 4K7

R2 4K7

R3 33K

R4 33K

567

B

8 4

[F(s

)]

IC2B

LF35

3N

+15V

-15V

R5 3K3

R6 3K3

R7 4K7

R8 4K7

C2 470n

FC1 10nF

C3 10nF

C4 470n

F

GN

D

IN2

VTE

MP

3

GN

D4

TRIM

5O

UT

6N

C8

NC

7N

C1

IC3

REF0

3GP

+15V

GN

D

C5 100n

F

8 5

2 3

4

6

7

1

IC4

OP0

7CP

8 5

2 3

4

6

7

1

IC5

OP0

7CP

+15V

+15V

-15V

-15V

R9 4K7

R10

4K7

R11

4K7

R12

4K7

GN

D

GN

D

+5V

REF

-5V

REF

2 31

A

8 4

IC6A

LF35

3N

567

B8 4

IC6B

LF35

3N

+15V

+15V

-15V

-15V

R13

0K47

-5V

REF

D1

BAT8

5D

2BA

T85

Ve

Cla

mpe

d1

C6 10uF

+2.5

V R

EF

2 31

A8 4

IC7A

LF35

3N

567

B8 4

IC7B

LF35

3N

+15V

+15V

-15V

-15V

R16

6K8

R17

3K3

R18

3K3

R19

10K

R15 2K G

ND+2.5V REF

+3V

REF

R20

2K

GN

D

+2.5

V R

EF

-6V

REF

+15V

+15V

-15V

-15V

-6V

REF

2 31

A8 4

IC8A

LF35

3N

567

B8 4

IC8B

LF35

3N

D3

BAT8

5D

4BA

T85

R21

0K47 +3

V R

EF

567

B8 4

[J(s

)]

IC10

BLF

353N

2 31

A8 4

IC10

ALF

353N

+15V

+15V

-15V

-15V

R30

1K

R31

100K

R32

6K8

R33

18K

R34

18K

R35

6K8

R36

220K

R37

220K

12

IC12

A

M74

HCT

14B

34

IC12

B

M74

HCT

14B

98

IC12

D

M74

HCT

14B

RST

1

CLK

9

D0

3Q

02

D1

4Q

15

D2

6Q

27

D3

11Q

310

D4

13Q

412

D5

14Q

515

VCC

16

GN

D8

IC13

M74

HC1

74B

1R

RST

1

CLK

9

D0

3Q

02

D1

4Q

15

D2

6Q

27

D3

11Q

310

D4

13Q

412

D5

14Q

515

VCC

16

GN

D8

IC14

M74

HC1

74B

1R

2 31

A8 4

IC15

ALF

353N

567

B8 4

IC15

BLF

353N

12

OSC

1

4MH

zR4

5

10M

R46

1KR4

71K

R48

22K

R49

22K

R50

1MR51

1M

R52

1K5

R53

4K7

C9 22pF

C10

22pF

C11

100n

F

C12

100n

F

C13

100u

FC1

410

0uF

GN

D

GN

D

+5V

56

IC12

C

M74

HCT

14B

1110

IC12

E

M74

HCT

14B

1312

IC12

F

M74

HCT

14B

+5V

GN

D

+5V

+5V

+15V

+15V

-15V

-15V

C15

100n

F

C16

1nF

C17

1nF

GN

D

GN

D

GN

D

Vtri

567

B8 4

IC18

BLF

353N

2 31

A8 4

IC18

ALF

353N

+15V

+15V

-15V

-15V

R64

4K7

R65

4K7

R66

4K7

R67

4K7

R68

4K7

R69

4K7

R70

4K7R7

1

4K7

GN

DV

eS2

VeS

1

Ve

Cla

mpe

d1

Ve

Cla

mpe

d1

1

23

4

5

6

7

8 IC19

AD

790J

N

1

23

4

5

6

7

8 IC20

AD

790J

N

GN

D

GN

D

+15V

+15V

-15V

-15V+5

V

+5V

C20

100n

F

C21

100n

F

C22

100n

F

C23

100n

F

C24

100n

F

C25

100n

F

GN

D

GN

D

GN

D

GN

D

GN

DV

r1

Vr1

1 2

CON

5

PWM

2

1 2

CON

4

PWM

1

GN

D

GN

D

IN1

2

OU

T3

GN

D

VS1

MC7

805C

T

GN

D

+15V

+5V

8

1

4

32

1IC

17A

LM35

8N

8 4

756

2IC

17B

LM35

8N

+15v

+15V

GN

D

GN

D

D6

1N41

48

GN

D

R55

100K

R56

1K8

R57

5K6

R58

1K8

R59

5K6

R54

100K

D5

1N41

48

C18

100n

F

C19

100n

F

C37

470u

F

C26

100n

F

+5V

GN

D

C27

100n

F

C28

100n

F

GN

D

GN

D

C29

100n

FG

ND

C30

100n

F

+5V

REF

C31

100n

F

C32

100n

FC3

310

0nF

GN

D

C34

100n

F

GN

D

GN

D

R25

1K5

R26

1K5

12

CON

2

CS S

igna

l 1C7 47

nF

C8 100p

F

C35

100p

FC3

647

nF

R29

100K

R28

1K

+5V

REF

GN

D

+5V

REF

GN

D

Vof

fset

Vof

fset

C38

100u

FC3

9

100u

F

(+5V

)(-

5V)

123

CON

3

VS

Sign

al 1

GN

D

SetI1

Vre

f1

C40

100n

F

GN

D

C41

100n

FC4

2

100n

F

C43

100n

F

(-5V

)(+

5V)

GN

D

GN

D

567

B8 4

IC23

BLF

353N

2 31

A8 4

IC23

ALF

353N

+15V

+15V

-15V

-15V

R80

4K7

R81

4K7

R79

4K7

R82

4K7

R86

4K7

R84

4K7

R85

4K7R8

3

4K7

GN

DV

eS3

VeS

4

Ve

Cla

mpe

d2

Ve

Cla

mpe

d2

1

23

4

5

6

7

8 IC24

AD

790J

N

1

23

4

5

6

7

8 IC25

AD

790J

N

GN

D

GN

D

+15V

+15V

-15V

-15V+5

V

+5V

C58

100n

F

C57

100n

F

C56

100n

F

C61

100n

F

C60

100n

F

C59

100n

F

GN

D

GN

D

GN

D

GN

D

GN

DV

r2

Vr2

1 2

CON

9

PWM

3

1 2

CON

8

PWM

4

GN

D

GN

D

Vof

fset

2 31

A8 4

[H(s

)]

IC21

ALF

353N

+15V

-15V

GN

D

R72

4K7

R73

4K7

R76

33K

R74

33K

567

B

8 4

[F(s

)]

IC21

BLF

353N

+15V

-15V

R22

3K3

R23

3K3

R27

4K7

R24

4K7

C52

470n

FC53

10nF

C50

10nF

C51

470n

F

GN

D

2 31

A

8 4

IC22

ALF

353N

567

B8 4

IC22

BLF

353N

+15V

+15V

-15V

-15V

R14

0K47

-5V

REF

D9

BAT8

5D

10BA

T85

Ve

Cla

mpe

d2

+15V

+15V

-15V

-15V

-6V

REF

2 31

A8 4

IC11

ALF

353N

567

B8 4

IC11

BLF

353N

D7

BAT8

5D

8BA

T85

R44

0K47 +3

V R

EF

567

B8 4

[J(s

)]

IC16

BLF

353N

2 31

A8 4

IC16

ALF

353N

+15V

+15V

-15V

-15V

R60

1K

R63

100K

R40

6K8

R39

18K

R42

18K

R43

6K8

R38

220K

R41

220K

+5V

REF

GN

D

R75

1K5

R78

1K5

12

CON

7

CS S

igna

l 2C4

7

47nF

C46

100p

F

C44

100p

FC4

547

nF

R62

100K

R61

1K

+5V

REF

GN

D

123

CON

6

VS

Sign

al 2

GN

D

SetI2

Vre

f2

C48

100n

F

GN

D

C49

100n

FC5

4

100n

F

C55

100n

F

(-5V

)(+

5V)

GN

D

GN

D

2 31

A8 4

IC26

ALF

353N

567

B8 4

IC26

BLF

353N

+15V

+15V

-15V

-15V

R87

1K

R88

1K

R89

1K R90

1K

GN

D

Vtri

Vr1

R91

1K

R92

1KG

ND

GN

D

Vtri

Vr2

PIC1

01PIC102

COC1

PIC201

PIC2

02

COC2

PIC301PIC302CO

C3

PIC401PIC402COC

4

PIC501PIC502COC

5PIC601 PIC602

COC6

PIC701

PIC7

02

COC7PI

C801

PIC802

COC8

PIC901PIC902COC

9PIC1001PIC1002

COC10

PIC1101PIC1102COC11

PIC1201PIC1202COC12

PIC1301 PIC1302COC13

PIC1401 PIC1402

COC14

PIC1

501

PIC1502

COC15

PIC1601

PIC1602

COC16

PIC1701PIC1702CO

C17

PIC1801

PIC1

802

COC18

PIC1901PIC1902CO

C19

PIC2

001

PIC2002COC20

PIC2101

PIC2

102

COC21

PIC2201

PIC2

202

COC22

PIC2

301

PIC2302COC23

PIC2401

PIC2

402

COC24

PIC250

1PI

C250

2

COC25

PIC2601PIC2602COC26

PIC2701

PIC2702CO

C27

PIC2801

PIC2

802COC28

PIC2901

PIC2902CO

C29

PIC3001

PIC3

002

COC30

PIC310

1PI

C310

2

COC31

PIC320

1PI

C320

2

COC32

PIC3301PIC3302COC33

PIC3401PIC3402COC34

PIC3501PIC3502COC35

PIC3601PIC3602COC36


PIC3

801

PIC3802

COC38 PIC3

901

PIC3902COC39

PIC4001

PIC4

002COC40

PIC410

1PI

C410

2

COC41

PIC4

201

PIC4202

COC42

PIC4301

PIC4

302

COC43

PIC4401PIC4402COC44

PIC4501PIC4502COC45

PIC4

601

PIC4602

COC46

PIC4701

PIC4

702

COC47

PIC4801

PIC4

802COC48

PIC4901

PIC4

902

COC49

PIC5001PIC5002COC50

PIC5101PIC5102COC51

PIC520

1PI

C520

2

COC52

PIC5

301

PIC5302

COC53

PIC5

401

PIC540

2

COC54

PIC550

1PI

C550

2

COC55

PIC5601

PIC5

602

COC56

PIC5701

PIC5

702

COC57

PIC5

801

PIC5802COC58

PIC590

1PI

C590

2

COC59

PIC6001

PIC6

002

COC60

PIC6

101

PIC6102COC61

PICON101

PICON102

COCON1

PICON201

PICON202

COCON2

PICON301

PICON302

PICON303

COCON3

PICO

N401

PICO

N402

COCON4

PICO

N501

PICO

N502

COCON5

PICON601

PICON602

PICON603

COCON6

PICON701

PICON702

COCON7

PICO

N801

PICO

N802

COCON8

PICO

N901

PICO

N902

COCON9

PID101 PID102CO

D1

PID201PID202CO

D2

PID301 PID302COD

3

PID401PID402CO

D4

PID501PID502COD

5

PID601PID602CO

D6

PID701 PID702CO

D7

PID801PID802CO

D8

PID901 PID902CO

D9

PID1001PID1002COD10

PIIC101

PIIC102

PIIC103

PIIC104

PIIC105

COIC1

PIIC201

PIIC202

PIIC203

PIIC204PIIC208

COIC2A

PIIC204PIIC205

PIIC206

PIIC

207

PIIC208COIC2B

PIIC301

PIIC302

PIIC303

PIIC304

PIIC305

PIIC306

PIIC307

PIIC308

COIC3

PIIC401

PIIC402

PIIC403

PIIC404PIIC405

PIIC406

PIIC407PIIC408

COIC4

PIIC501

PIIC502

PIIC503

PIIC504PIIC505

PIIC506

PIIC507PI

IC50

8

COIC5

PIIC601

PIIC602

PIIC603

PIIC604PIIC608

COIC6A

PIIC604PIIC605

PIIC

606

PIIC607

PIIC608

COIC6B

PIIC701

PIIC702

PIIC703

PIIC704PIIC708 COIC

7A

PIIC704PIIC705

PIIC706

PIIC

707

PIIC708

COIC

7B

PIIC801

PIIC802

PIIC

803

PIIC804PIIC808

COIC8A

PIIC804PI

IC80

5

PIIC806

PIIC807

PIIC808

COIC8B

PIIC

1001

PIIC1002

PIIC1003

PIIC1004PIIC1008

COIC

10A

PIIC1004PIIC1005

PIIC1006

PIIC

1007

PIIC1008

COIC

10B

PIIC1101

PIIC1102

PIIC1103

PIIC1104PIIC1108

COIC

11A

PIIC1104PIIC1105

PIIC1106

PIIC

1107

PIIC1108

COIC

11B

PIIC1201

PIIC1202

COIC

12A

PIIC1203

PIIC1204

COIC

12B

PIIC1205

PIIC

1206

COIC

12C

PIIC1208

PIIC1209

COIC

12D

PIIC

1201

0PI

IC12

011

COIC

12E

PIIC

1201

2PI

IC12

013

COIC

12F

PIIC

1301

PIIC1302

PIIC

1303

PIIC

1304

PIIC1305

PIIC

1306

PIIC1307

PIIC

1308

PIIC

1309

PIIC

1301

0PI

IC13

011

PIIC

1301

2PI

IC13

013

PIIC

1301

4PI

IC13

015

PIIC

1301

6

COIC

13

PIIC

1401

PIIC1402

PIIC

1403

PIIC

1404

PIIC1405

PIIC

1406

PIIC1407

PIIC

1408

PIIC

1409

PIIC

1401

0PI

IC14

011

PIIC

1401

2PI

IC14

013

PIIC

1401

4PI

IC14

015

PIIC

1401

6

COIC

14

PIIC

1501

PIIC1502

PIIC1503

PIIC1504PIIC1508 COIC

15A

PIIC1504PIIC1505

PIIC1506

PIIC1507

PIIC1508CO

IC15

B

PIIC

1601

PIIC1602

PIIC1603

PIIC1604PIIC1608

COIC

16A

PIIC1604PIIC1605

PIIC1606

PIIC

1607

PIIC1608

COIC

16B

PIIC1701

PIIC1702

PIIC1703


17A

PIIC1704PIIC1705

PIIC1706

PIIC1707

PIIC1708CO

IC17

B

PIIC1801

PIIC

1802

PIIC

1803


18A

PIIC1804PI

IC18

05

PIIC

1806

PIIC1807

PIIC1808COIC

18B

PIIC1901

PIIC1902

PIIC1903

PIIC1904

PIIC1905

PIIC1906PIIC1907

PIIC1908 COIC19

PIIC2001

PIIC2002

PIIC2003

PIIC2004

PIIC2005

PIIC2006PIIC2007

PIIC2008 COIC

20

PIIC2101

PIIC

2102

PIIC

2103

PIIC2104PIIC2108

COIC

21A

PIIC2104PI

IC21

05

PIIC

2106

PIIC2107

PIIC2108CO

IC21

B

PIIC2201

PIIC

2202

PIIC

2203

PIIC2204PIIC2208

COIC

22A

PIIC2204PIIC2205

PIIC2206

PIIC

2207

PIIC2208

COIC

22B

PIIC2301

PIIC

2302

PIIC

2303


23A

PIIC2304PI

IC23

05

PIIC

2306

PIIC2307

PIIC2308COIC

23B

PIIC2401

PIIC2402

PIIC2403

PIIC2404

PIIC2405

PIIC2406PIIC2407

PIIC2408 COIC

24

PIIC2501

PIIC2502

PIIC2503

PIIC2504

PIIC2505

PIIC2506PIIC2507

PIIC2508 COIC25

PIIC2601

PIIC2602

PIIC2603


26A

PIIC2604PIIC2605

PIIC2606

PIIC2607

PIIC2608COIC

26B

PIOSC101

PIOSC102

COOSC1

PIR101

PIR102

COR1

PIR201

PIR202

COR2

PIR301

PIR302

COR3

PIR401PIR402 COR4

PIR501

PIR5

02CO

R5 PIR6

01PI

R602COR

6

PIR7

01PIR702

COR7

PIR801PIR802 COR8

PIR9

01PI

R902CO

R9PIR1001

PIR1

002

COR10

PIR1101

PIR1102

COR11

PIR1201

PIR1202

COR12

PIR130

1PIR

1302

COR13

PIR1401

PIR1402

COR14

PIR1501 PIR1502

PIR1503COR15

PIR1601

PIR1

602

COR16


PIR1801

PIR1802

COR18

PIR1

901

PIR1902

COR19

PIR2001 PIR2002

PIR2003

COR20

PIR2101

PIR2102

COR21

PIR2201

PIR2

202

COR22

PIR2

301

PIR2

302COR23


PIR2

501

PIR2

502COR25

PIR2601

PIR2602

COR26

PIR2

701

PIR270

2COR27

PIR2

801

PIR280

2COR28


PIR3

001

PIR3

002

COR30

PIR3101

PIR3102

COR31

PIR3

201

PIR3202

COR32

PIR3

301

PIR3302

COR33

PIR3

401

PIR340

2COR34


PIR3601

PIR3602CO

R36 PIR

3701

PIR370

2COR37 PI

R3801

PIR3802CO

R38

PIR3

901

PIR3902

COR39

PIR4

001

PIR400

2COR40

PIR4101

PIR4102CO

R41

PIR4

201

PIR4202

COR42


PIR4401

PIR4402

COR44

PIR4501

PIR4502

COR45



PIR4801

PIR4802

COR48

PIR490

1PIR

4902

COR49


PIR5101

PIR5102

COR51

PIR5201

PIR5202

COR52

PIR5

301

PIR5

302

COR53

PIR5401 PIR5402

PIR5403

COR54




PIR5801 PIR5802COR58

PIR5

901

PIR5902COR

59

PIR6

001

PIR6

002

COR60 PIR6

101

PIR6102COR61


PIR6301

PIR6302

COR63

PIR6401

PIR6402

COR64 PIR

6501

PIR650

2COR65

PIR6

601

PIR6

602

COR66

PIR6701

PIR6

702

COR67

PIR6801

PIR6

802

COR68

PIR6901

PIR6902

COR69

PIR7001

PIR7002

COR70

PIR7101

PIR7102

COR71

PIR7201

PIR7202

COR72

PIR7301

PIR7302

COR73


PIR7

501

PIR7

502COR75

PIR7601

PIR7602

COR76

PIR7801

PIR7802

COR78

PIR7

901

PIR7

902

COR79

PIR8001

PIR8002

COR80 PI

R8101

PIR8102CO

R81

PIR820

1PI

R820

2COR82

PIR8301

PIR8302

COR83

PIR8401

PIR8402

COR84

PIR8501

PIR8502

COR85

PIR8601

PIR8

602

COR86

PIR8

701

PIR8702

COR87

PIR8

801

PIR8

802

COR88

PIR8

901

PIR8902

COR89

PIR9001

PIR9

002

COR90


PIR9

201

PIR9

202

COR92

PIVS101

PIVS102

PIVS103

COVS1

PIIC306

PIIC403

PIR1501

PIR2001NL0205V REF

PIC3302PIIC701

PIIC

803

PIIC1103

PIR1

602

NL03V REF

PIC1102

PIC1202

PIC2101

PIC2401

PIC2602

PIC3

202

PIC5701

PIC6001

PIIC

1201

4

PIIC

1301

6PI

IC14

016

PIIC1905

PIIC1908

PIIC2005

PIIC2008

PIIC2405

PIIC2408

PIIC2505

PIIC2508

PIR4602PIR4702

PIVS103

PIC3701

PIIC406

PIIC603

PIIC

2203

PIR1

002

PIR1101

PIR3

001

PIR5401

PIR6

001

NL05V REF

PICON101

PIIC102

PIC502PIC601

PIC2

202

PIC2

502

PIC2

802

PIC2902

PIC310

1

PIC3

801

PIC410

1

PIC4301

PIC4901

PIC550

1

PIC5

602

PIC5

902

PIIC103

PIIC208

PIIC302

PIIC407PIIC507

PIIC608

PIIC708

PIIC808

PIIC1008

PIIC1108

PIIC1508

PIIC1608 PIIC1708

PIIC1808PIIC1901 PIIC2001

PIIC2108

PIIC2208PIIC2308

PIIC2401 PIIC2501

PIIC2608

PIVS101

PIIC506

PIIC605

PIIC2205

PIR1202

NL05V REF

PIC3402PI

IC70

7

PIIC

805

PIIC1105

PIR1902

NL06V REF

PIC2

001

PIC2

301

PIC2701

PIC3001

PIC3902

PIC4001

PIC4202

PIC4801

PIC540

2

PIC5

801

PIC6

101

PIIC105

PIIC204

PIIC404PIIC504

PIIC604

PIIC704

PIIC804

PIIC1004

PIIC1104

PIIC1504

PIIC1604


PIIC2104

PIIC2204PIIC2304

PIIC2404 PIIC2504

PIIC2604

PICON102

PIIC101

PIC301

PIC401

PIC501PIC602

PIC901PIC1001

PIC1101

PIC1201

PIC1302PIC1402

PIC1701PIC1901

PIC2002

PIC2

102

PIC2201

PIC2302

PIC2

402

PIC250

1

PIC2601

PIC2702

PIC2801

PIC2901

PIC3

002

PIC3

102

PIC320

1

PIC3301PIC3401

PIC3501

PIC3601

PIC3802

PIC3

901

PIC4

002

PIC4

102

PIC4

201

PIC4

302

PIC4401

PIC4501PI

C480

2

PIC4

902

PIC5001

PIC5101

PIC5

401

PIC5

502

PIC5601

PIC5

702

PIC5802

PIC590

1

PIC6

002

PIC6102

PICON303

PICO

N402

PICO

N502

PICON603

PICO

N802

PICO

N902

PID501

PIIC104

PIIC304

PIIC503

PIIC705

PIIC1207

PIIC

1201

2

PIIC

1308

PIIC

1301

5

PIIC

1408

PIIC

1401

5

PIIC1505

PIIC1704PIIC1705

PIIC1906 PIIC2006 PIIC2406 PIIC2506

PIIC2603

PIR9

02

PIR1503

PIR1701

PIR2003

PIR2

502

PIR3501 PIR4301

PIR5001PIR5701

PIR5802

PIR650

2

PIR7101

PIR7

502

PIR8102

PIR8301

PIR8

901

PIR9101

PIVS102

PIC1

01

PIC201

PIIC206

PIR5

02

PIC102

PIIC

207

PIR702

PIR130

1

PIC2

02PI

R701

PIC302

PIIC205

PIR6

01

PIR802 PIC402PIR801

PIC701

PIC8

01

PIIC1006

PIR3

002

PIC7

02PIR3101

PIC902PIIC1201

PIOSC101

PIR4501

PIC1002

PIIC1202PIIC1203

PIOSC102

PIR4502

PIC1301

PIIC

1301

PIR4601

PIC1401

PIIC

1401

PIR4701

PIC1

501

PIC1602

PIIC

1501

PIR5102

PIC1502PIR5201

PIC1601

PIIC1502

PIR4802PIR5101

PIC1702PIIC1503

PIR490

2PIR5002

PIC1801

PIIC1702

PIR5801

PIR5902

PIC1902PIIC1703

PIR5601 PIR5702

PIC3502

PIIC1005

PIR2

801

PIR2902 PIC3602PIR2901

PIC3702 PID502

PIR5501 PIR5602

PIC4402

PIIC1605

PIR6

101


PIC4

601

PIC4701

PIIC1606

PIR6

002

PIC4

702

PIR6301

PIC5002

PIIC

2105

PIR2

301


PIC520

1PIC5

301

PIIC

2106

PIR2

202

PIC5

202P

IR27

01

PIC5302

PIIC2107PIR1401

PIR270

2

PICON201 PIR201

PICON202PIR101

PICON301

PIR370

2

PICON302

PIR3602

PICO

N401

PIIC1907

PICO

N501

PIIC2007

PICON601

PIR4102

PICON602

PIR3802

PICON701 PIR7301

PICON702PIR7201

PICO

N801

PIIC2407

PICO

N901

PIIC2507

PID102PIIC601

PID201PIIC607

PID302PIIC801

PID401PIIC807

PID601PIIC1707

PID702PIIC1101

PID801PI

IC11

07

PID902PIIC2201

PID1001PI

IC22

07

PIIC201

PIR501

PIR2602

PIIC202

PIR102

PIR301

PIIC203

PIR202

PIR402

PIIC301

PIIC303

PIIC305

PIIC307

PIIC308

PIIC401

PIIC402

PIR9

01PIR1001

PIIC405

PIIC408

PIIC501

PIIC502

PIR1102

PIR1201

PIIC505

PIIC

508

PIIC702

PIR1601

PIR1702PIIC703

PIR1502

PIIC706

PIR1802PIR1

901

PIIC

1001

PIR280

2

PIR3202

PIIC1002

PIR3

201

PIR3302 PIIC1003

PIR340

2 PIR3502

PIIC1204

PIIC

1309

PIIC1205

PIIC

1301

2

PIIC

1206

PIIC

1303

PIIC1208P

IR4901

PIIC1209

PIIC

1401

0

PIIC

1401

3

PIR4801

PIIC

1201

0

PIIC

1403

PIIC

1201

1

PIIC

1401

2

PIIC

1201

3

PIIC1302

PIIC

1304

PIIC1305

PIIC

1306

PIIC1307

PIIC

1301

1PI

IC13

010

PIIC

1301

3

PIIC

1409

PIIC

1301

4

PIIC1402

PIIC

1404

PIIC1405

PIIC

1406

PIIC1407

PIIC

1401

1

PIIC

1401

4

PIIC1506

PIR5202PI

R530

1

PIIC

1601

PIR400

2

PIR6102

PIIC1602

PIR3902PIR4

001

PIIC1603

PIR4202 PIR4302

PIIC

1802

PIR6

602PI

R6701

PIIC

1803

PIR6402

PIR650

1 PIIC

1805

PIR6902

PIR7002

PIIC

1806

PIR6801

PIR7102

PIIC2101

PIR2201

PIR7802

PIIC

2102

PIR7202PI

R7601

PIIC

2103

PIR7302 PIR7402

PIIC

2302

PIR7

902PIR

8201

PIIC

2303

PIR8002

PIR8101 PIIC

2305

PIR8402

PIR8502

PIIC

2306

PIR8302PIR8601

PIIC2602

PIR8702

PIR8

801

PIIC2605

PIR9

002 PIR9102PI

IC2606

PIR8902

PIR9

201

PIR302

PIR2601

PIR401PI

R250

1

PIR1801

PIR2002

PIR3

301

PIR3601 PI

R340

1PIR

3701

PIR3801PIR

3901

PIR4101PIR

4201

PIR5402

PIR5403 PIR5502

PIR7401PI

R750

1

PIR7602

PIR7801

PID301PID402

PIIC802

PIIC806

PIR6

02

PIR2102

NLSetI

1

PID701PID802

PIIC1102

PIIC1106

PIR2

302

PIR4402

NLSetI

2

PID101PID202

PIIC602

PIIC

606

PIR130

2PIR6401

PIR7001

NLVe Clamped1

PID901PID1002

PIIC

2202

PIIC2206

PIR1402

PIR8001

PIR8501

NLVe Clamped2

PIIC1801

PIIC1902

PIR6

702

NLVe

S1

PIIC1807

PIIC2003

PIR6

802

NLVe

S2

PIIC2307

PIIC2503

PIR8

602

NLVe

S3

PIIC2301

PIIC2402

PIR8

202

NLVe

S4

PIC1

802

PID602PIIC1701

PIIC1706

PIR5

901

PIR6

601

PIR6901

PIR7

901

PIR8401

NLVo

ffse

t

PIIC1903

PIIC2002

PIIC2601

PIR8

802

NLVr1

PIIC2403

PIIC2502

PIIC2607

PIR9

202

NLVr2

PIC802

PIIC

1007

PIR2101

PIR3102

NLVref

1

PIC4602

PIIC

1607

PIR4401

PIR6302

NLVr

ef2

PIIC1507

PIR5

302

PIR8

701

PIR9001

NLVt

ri

Figure A.3: Control schematic for the dc-dc converter circuit.



A.2 Inverter Circuit Schematics

All of the circuit diagrams used for the implementation of the bidirectionalcurrent-controller three-phase inverter prototype circuit are given in this sec-tion.

A.2.1 Power Stage Schematics

The schematics for the power stage of the inverter circuit are given in thissection. It includes the three-phase inverter topology, gate-drive circuitry anddc bus current sensor. The schematic is shown in Fig.A.4.



11

22

33

44

55

66

77

88

DD

CC

BB

AA

D1

BAT8

5

D2

BAT8

5

Q2

BC55

6Q

1BC

556

T110

:11

C1 100p

F

C2 100p

F

R1 0.22

K

R2 0.22

K

R3 1M

R4 0.47

K

C4 100u

FR5 10

ohm

+15V

C3 100n

F

R6 27K

C5 100n

F

SGN

D1

GN

D

D3

BAT8

5

D4

BAT8

5

Q4

BC55

6Q

3BC

556

T210

:11

C6 100p

F

C7 100p

F

R7 0.22

K

R8 0.22

K

R9 1M

C9 100u

F

+15V

C8 100n

F

C10

100n

F

GN

D

D5

BAT8

5

D6

BAT8

5

Q6

BC55

6Q

5BC

556

T310

:11

C11

100p

F

C12

100p

F

R13

0.22

K

R14

0.22

K

R15

1M

C14

100u

F

+15V

C13

100n

F

C15

100n

F

GN

D

D7

BAT8

5

D8

BAT8

5

Q8

BC55

6Q

7BC

556

T410

:11

C16

100p

F

C17

100p

F

R19

0.22

K

R20

0.22

K

R21

1M

C19

100u

F

+15V

C18

100n

F

C20

100n

F

GN

D

D9

BAT8

5

D10

BAT8

5

Q10

BC55

6Q

9BC

556

T510

:11

C21

100p

F

C22

100p

F

R25

0.22

K

R26

0.22

K

R27

1M

C24

100u

F

+15V

C23

100n

F

C25

100n

F

GN

D

D11

BAT8

5

D12

BAT8

5

Q12

BC55

6Q

11BC

556

T610

:11

C26

100p

F

C27

100p

F

R31

0.22

K

R32

0.22

K

R33

1M

C29

100u

F

+15V

C28

100n

F

C30

100n

F

GN

D

G1

G2

G3

G4

G5

G6

UV

W

EU

EV

EW

E1U

E1V

E1W

T1 T2PM

1FS

30R

06W

1E3_

B11

C31

100u

F

1 2 3

P5 3Pha

se

1 2

P4 DC

Bus

PWM

1

PWM

2

PWM

3

PWM

4

PWM

5

PWM

6

1 2

P6

Vbu

s Mon

itor

1 2

P7 12V

Sup

ply+1

2V 0V

R39

1K

GN

D

+5V

VCC

1

GN

D2

VIO

UT

3

IP+

4

IP-

5

H4

ACS

756x

CB

VCC

213

Vou

t11

DES

AT

14

VEE

12

VCL

AM

P10

VE

16

VLE

D15

AN

OD

E6

CATH

OD

E5

VCC

12

Vs

1

nFA

ULT

3

IC1

TLP5

214

C33

100n

F

+5V

R37

2K2

R38

0K1

C34

100p

F

PWM

1

D13

BYV

26E

C35

1nFnF

1 GN

D

+Vs

-Vs

+Vs

1 2 3

CON

1

PWM

1

C39

100n

F

1 2 3

CON

2

PWM

2 1 2 3

CON

3

PWM

3 1 2 3

CON

4

PWM

4

1 2 3

CON

5

PWM

51 2 3

CON

6

PWM

6

+5V

nF2 G

ND

SGN

D1

R10

0.47

K

R11

10oh

mR1

227

K

-Vs

VCC

213

Vou

t11

DES

AT

14

VEE

12

VCL

AM

P10

VE

16

VLE

D15

AN

OD

E6

CATH

OD

E5

VCC

12

Vs

1

nFA

ULT

3

IC2

TLP5

214

C40

100n

F

R40

2K2

R41

0K1

C41

100p

F

PWM

2

D14

BYV

26E

C42

1nF +5

V

nF3 G

ND

+Vs

R16

0.47

K

R17

10oh

mR1

827

K

SGN

D3

VCC

213

Vou

t11

DES

AT

14

VEE

12

VCL

AM

P10

VE

16

VLE

D15

AN

OD

E6

CATH

OD

E5

VCC

12

Vs

1

nFA

ULT

3

IC3

TLP5

214

C43

100n

F

R42

2K2

R43

0K1

C44

100p

F

PWM

3

D15

BYV

26E

C45

1nF +5

V

nF4 G

ND

SGN

D3

R22

0.47

K

R23

10oh

mR2

427

K

-Vs

VCC

213

Vou

t11

DES

AT

14

VEE

12

VCL

AM

P10

VE

16

VLE

D15

AN

OD

E6

CATH

OD

E5

VCC

12

Vs

1

nFA

ULT

3

IC4

TLP5

214

C46

100n

F

R44

2K2

R45

0K1

C47

100p

F

PWM

4

D16

BYV

26E

C48

1nF

+5V

nF5 G

ND

+Vs

R28

0.47

K

R29

10oh

mR3

027

K

SGN

D5

VCC

213

Vou

t11

DES

AT

14

VEE

12

VCL

AM

P10

VE

16

VLE

D15

AN

OD

E6

CATH

OD

E5

VCC

12

Vs

1

nFA

ULT

3

IC5

TLP5

214

C49

100n

F

R46

2K2

R47

0K1

C50

100p

F

PWM

5

D17

BYV

26E

C51

1nF+5

V

nF6 G

ND

SGN

D5

R34

0.47

K

R35

10oh

mR3

627

K

-Vs

VCC

213

Vou

t11

DES

AT

14

VEE

12

VCL

AM

P10

VE

16

VLE

D15

AN

OD

E6

CATH

OD

E5

VCC

12

Vs

1

nFA

ULT

3

IC6

TLP5

214

C52

100n

F

R48

2K2

R49

0K1

C53

100p

F

PWM

6

D18

BYV

26E

C54

1nF

GN

D

GN

D

GN

D

GN

D

GN

D

GN

D

Vin

-1

Vin

+2

Vou

t+3

COM

4

Vou

t-5

IC7

DK

E10A

-15

+15V

-15V

GN

D

C55

100u

F

C56

100u

F

C57

100n

F

C58

100n

F

IN1

2

OU

T3

GN

D

VS1

MC7

805C

T

1 2

P8 Tem

p Se

nsor

+15V

+5V

GN

D

C67

100n

FC6

810

0nF

C69

100u

F

SGN

D1

SGN

D3

SGN

D5

C32

100n

F

GN

D

1 2 3

P9 CS D

C B

us

D19

3V9

D20

3V9

D21

3V9

D22

3V9

D23

3V9

D24

3V9

PIC101

PIC1

02

COC1

PIC201

PIC2

02

COC2

PIC301PIC302COC

3

PIC401 PIC402CO

C4

PIC501PIC502 COC

5

PIC601

PIC6

02

COC6

PIC701

PIC7

02

COC7

PIC801PIC802COC

8

PIC901 PIC902CO

C9

PIC1001PIC1002COC10

PIC1101

PIC1

102

COC11

PIC1201

PIC1

202

COC12

PIC1301PIC1302COC13

PIC1401 PIC1402

COC14

PIC1501PIC1502COC15

PIC1601

PIC1

602

COC16

PIC1701

PIC1

702

COC17

PIC1801PIC1802COC18


PIC2001PIC2002COC20

PIC2

101

PIC2102

COC21

PIC2201

PIC2202

COC22

PIC2301PIC2302COC23

PIC2401 PIC2402

COC24

PIC2501PIC2502COC25

PIC2

601

PIC2602

COC26

PIC2701

PIC2702

COC27

PIC2801PIC2802COC28

PIC2901 PIC2902

COC29

PIC3001PIC3002COC30PIC3101 PIC3102

COC31

PIC3201PIC3202COC32

PIC3301PIC3302COC33

PIC3401PIC3402COC34

PIC3501PIC3502COC35

PIC3

901

PIC390

2

COC39

PIC4001PIC4002COC40

PIC4101PIC4102COC41

PIC4201PIC4202COC42

PIC4301PIC4302COC43

PIC4401PIC4402COC44

PIC4501PIC4502COC45

PIC4601PIC4602COC46

PIC4701PIC4702COC47

PIC4801PIC4802COC48

PIC4901PIC4902COC49

PIC5001PIC5002COC50

PIC5101PIC5102COC51

PIC5201PIC5202COC52

PIC5301PIC5302COC53

PIC5401PIC5402COC54

PIC5501

PIC5

502

COC55

PIC560

1PI

C560

2COC5

6

PIC5701

PIC5

702

COC57

PIC580

1PI

C580

2COC58

PIC6701PIC6702COC67

PIC6801PIC6802COC68

PIC6901 PIC6902

COC69

PICO

N101

PICO

N102

PICO

N103

COCON1

PICO

N201

PICO

N202

PICO

N203

COCON2

PICO

N301

PICO

N302

PICO

N303

COCON3

PICO

N401

PICO

N402

PICO

N403

COCON4

PICON501

PICON502

PICON503

COCON5

PICON601

PICON602

PICON603

COCON6

PID101

PID102

COD1

PID201

PID202

COD2

PID301

PID302

COD3

PID401

PID402

COD4

PID501

PID502

COD5

PID601

PID602

COD6

PID701

PID702

COD7

PID801

PID802

COD8

PID901

PID902

COD9

PID1001

PID1002

COD10

PID1101

PID1102

COD11

PID1201

PID1202

COD12

PID1301

PID1302

COD13

PID1401

PID1402

COD14

PID1501

PID1502

COD15

PID1

601

PID1

602

COD16

PID1701

PID1702

COD17

PID1

801

PID1

802

COD18

PID1901

PID1902COD19 PID2001

PID2002COD20 PID2101

PID2102COD21 PI

D220

1PI

D220

2COD22

PID2301

PID2302COD23PI

D2401

PID2402COD24

PIH4

01

PIH402

PIH403

PIH4

04

PIH405CO

H4

PIIC101

PIIC

102

PIIC103

PIIC105

PIIC106

PIIC1010

PIIC1011

PIIC1012

PIIC1013

PIIC1014

PIIC1015

PIIC1016

COIC1

PIIC

201

PIIC

202

PIIC203

PIIC205

PIIC206

PIIC2010

PIIC2011

PIIC2012

PIIC2013

PIIC2014

PIIC2015

PIIC2016

COIC2

PIIC301

PIIC302

PIIC303

PIIC305

PIIC306

PIIC3010

PIIC3011

PIIC3012

PIIC3013

PIIC3014

PIIC3015

PIIC3016

COIC3

PIIC

401

PIIC402

PIIC403

PIIC

405

PIIC406

PIIC4010

PIIC4011

PIIC4012

PIIC4013

PIIC4014

PIIC4015

PIIC4016

COIC4

PIIC501

PIIC502

PIIC503

PIIC505

PIIC

506

PIIC

5010

PIIC

5011

PIIC

5012

PIIC

5013

PIIC

5014

PIIC

5015

PIIC

5016

COIC5

PIIC601

PIIC602

PIIC603

PIIC

605

PIIC606

PIIC

6010

PIIC

6011

PIIC

6012

PIIC

6013

PIIC

6014

PIIC

6015

PIIC

6016

COIC6

PIIC701

PIIC702

PIIC703

PIIC704

PIIC705

COIC7

PIM10E1U

PIM1

0E1V

PIM10E1W

PIM10EUPIM10EV

PIM10EW

PIM10G1

PIM10G2

PIM10G3

PIM10G4

PIM1

0G5

PIM1

0G6

PIM1

0P

PIM1

0T1

PIM1

0T2

PIM10U

PIM10V

PIM10W

COM1

PIP401

PIP402COP

4

PIP501

PIP502

PIP503COP

5

PIP601

PIP602

COP6

PIP701

PIP702

COP7

PIP801

PIP802

COP8

PIP901

PIP902

PIP903COP

9

PIQ101PIQ102

PIQ103COQ

1

PIQ201PIQ202

PIQ203 COQ2

PIQ301PIQ302

PIQ303CO

Q3

PIQ401PIQ402

PIQ403 COQ4

PIQ501PIQ502

PIQ503CO

Q5

PIQ601PIQ602

PIQ603 COQ6

PIQ701PIQ702

PIQ703CO

Q7

PIQ801PIQ802

PIQ803 COQ8

PIQ901PIQ902

PIQ903COQ

9

PIQ1001PIQ1002

PIQ1003 COQ10

PIQ1101PIQ1102

PIQ1103COQ11

PIQ1201PI

Q120

2

PIQ1203 COQ12

PIR101

PIR102

COR1

PIR201

PIR202

COR2

PIR301PIR302 COR3

PIR401 PIR402

COR4

PIR501

PIR5

02CO

R5

PIR601PIR602 COR6

PIR701

PIR702

COR7

PIR801

PIR802

COR8

PIR901PIR902 COR9

PIR1001 PIR1002

COR10

PIR110

1PI

R110

2COR11

PIR1201PIR1202COR

12

PIR130

1PIR

1302

COR13

PIR140

1PIR

1402

COR14


PIR1601 PIR1602

COR16

PIR1701

PIR1

702

COR17

PIR1801PIR1802COR18

PIR1901

PIR1902

COR19

PIR2001

PIR2002

COR20


PIR2201 PIR2202

COR22

PIR2301

PIR2

302

COR23


PIR2

501

PIR2502

COR25

PIR2601

PIR2602

COR26



PIR2901

PIR2902

COR29

PIR3001PIR3002COR30

PIR3

101

PIR310

2COR31

PIR320

1PIR

3202

COR32



PIR3501

PIR3502

COR35


PIR3701PIR3702COR37

PIR3

801

PIR3

802

COR38


PIR4001PIR4002COR40

PIR4

101

PIR4

102

COR41

PIR4201PIR4202COR42

PIR4

301

PIR4

302

COR43

PIR4401PIR4402COR44

PIR450

1PIR

4502

COR45

PIR4601

PIR4602

COR46

PIR4

701

PIR4

702

COR47

PIR4801

PIR4802

COR48

PIR490

1PIR

4902

COR49

PIT101PIT102

PIT103PIT104

PIT105PIT106

PIT107PIT108 COT

1

PIT201PIT202

PIT203PIT204

PIT205PIT206

PIT207PIT208 COT

2

PIT301PIT302

PIT303PIT304

PIT305PIT306

PIT307PIT308 COT

3

PIT401PIT402

PIT403PIT404

PIT405PIT406

PIT407PIT408 COT

4

PIT501PIT502

PIT503PIT504

PIT505PIT506

PIT507PIT508 CO

T5

PIT601PIT602

PIT603PIT604

PIT605PIT606

PIT607PIT608 CO

T6

PIVS101

PIVS102

PIVS103

COVS1

PIC3302 PIC4002 PIC4302 PIC4602

PIC4902PIC5202

PIC6802PIC6901

PIIC

102

PIIC

202

PIIC302

PIIC402

PIIC502

PIIC602

PIM1

0T1

PIR3702 PIR4002 PIR4202 PIR4402

PIR4602

PIR4802

PIVS103

PIIC702

PIP701

PIC302 PIC802 PIC1302 PIC1802

PIC2302PIC2802

PIC5501

PIC580

1

PIC6702PIIC703

PIQ103PIQ203

PIQ303PIQ403

PIQ503PIQ603

PIQ703PIQ803

PIQ903PIQ1003

PIQ1103PIQ1203

PIVS101

PIC3101PIC3202

PID1901

PID2101

PID2301

PIH4

04

PIM1

0P

PIC5

602

PIC5701

PIIC705

PIC902PIC1001

PIC1902PIC2001

PIC2902PIC3001

PIC3102PIC3201

PIC4101 PIC4701

PIC5301

PIIC2012

PIIC2016

PIIC4012

PIIC4016

PIIC

6012

PIIC

6016

PIM10E1U

PIM1

0E1V

PIM10E1W

PIM10EUPIM10EV

PIM10EWPIP402

PIP602

PIR1201 PIR2401

PIR3601

PIT202PIT203

PIT402PIT403

PIT602PIT603

PIIC701

PIP702

PIC301 PIC801 PIC1301 PIC1801

PIC2301PIC2801

PIC3301PIC3501

PIC4001PIC4201

PIC4301PIC4501

PIC4601PIC4801

PIC4901PIC5101

PIC5201PIC5401

PIC5

502

PIC560

1

PIC5

702

PIC5

802

PIC6701PIC6801

PIC6902

PICO

N102

PICO

N202

PICO

N302

PICO

N402

PICON502

PICON602

PIIC101

PIIC105

PIIC

201

PIIC205

PIIC301

PIIC305

PIIC

401

PIIC

405

PIIC501

PIIC505

PIIC601

PIIC

605

PIIC704

PIP802

PIR301 PIR901 PIR1501 PIR2101

PIR2701PIR3301

PIR3901

PIT106PIT107

PIT206PIT207

PIT306PIT307

PIT406PIT407

PIT506PIT507

PIT606PIT607

PIVS102

PIC101

PIQ101

PIT105

PIC1

02

PIR201

PIR302PIC201

PIR102

PIC2

02

PIQ201

PIT108

PIC401PIC502

PID102

PID202

PIIC1013

PIC601

PIQ301

PIT205

PIC6

02

PIR801

PIR902PIC701

PIR702

PIC7

02

PIQ401

PIT208

PIC901PIC1002

PID302

PID402

PIIC2013

PIC1101

PIQ501

PIT305

PIC1

102

PIR140

1

PIR1502PIC1201

PIR130

2

PIC1

202

PIQ601

PIT308

PIC1401PIC1502

PID502

PID602

PIIC3013

PIC1601

PIQ701

PIT405

PIC1

602

PIR2001

PIR2102PIC1701

PIR1902

PIC1

702

PIQ801

PIT408

PIC1901PIC2002

PID702

PID802

PIIC4013

PIC2

101

PIQ901

PIT505

PIC2102

PIR2601

PIR2702PIC2201

PIR2502

PIC2202

PIQ1001

PIT508

PIC2401PIC2502

PID902

PID1002

PIIC

5013

PIC2

601

PIQ1101

PIT605

PIC2602

PIR320

1

PIR3302PIC2701

PIR310

2

PIC2702

PIQ1201

PIT608

PIC2901PIC3002

PID1102

PID1202

PIIC

6013

PIC3402PIIC1014

PIR3

801

PIC3

901

PIH4

01PIP901

PIC390

2

PIH402

PIP902

PIC4102PIIC2014

PIR4

101

PIC4402PIIC3014

PIR4

301

PIC4702PIIC4014

PIR450

1

PIC5002PI

IC50

14PI

R470

1

PIC5302PI

IC60

14PIR

4901

PICO

N101

PIR401

PICO

N201

PIR1001

PICO

N301

PIR1601

PICO

N401

PIR2201

PICON501

PIR2801

PICON601

PIR3401

PID101

PIT104 PID201

PIT101

PID301

PIT204 PID401

PIT201

PID501

PIT304 PID601

PIT301

PID701

PIT404 PID801

PIT401

PID901

PIT504 PID1001

PIT501

PID1101

PIT604 PID1201

PIT601

PID1301

PIR3

802

PID1302PID1902

PID1401

PIR4

102

PID1402PID2002

PID1501

PIR4

302

PID1502PID2102

PID1

601

PIR450

2PI

D160

2PID2

202

PID1701

PIR4

702

PID1702PID2302

PID1

801

PIR490

2PI

D180

2PID2402

PIH403

PIP903

PIH405

PIP401

PIP601

PIIC106

PIR402

PIIC1011

PIR501

PIR602PIIC1015

PIIC206

PIR1002

PIIC2011

PIR110

1

PIR1202PIIC2015

PIIC306

PIR1602

PIIC3011

PIR1701

PIR1802PIIC3015

PIIC406

PIR2202

PIIC4011

PIR2301

PIR2402PIIC4015

PIIC

506

PIR2802

PIIC

5011

PIR2901

PIR3002PI

IC50

15

PIIC606

PIR3402

PIIC

6011

PIR3501

PIR3602PI

IC60

15

PIM1

0T2

PIP801

PIR3902

PIQ102PI

R101

PIQ202

PIR202

PIQ302PI

R701

PIQ402

PIR802

PIQ502PI

R1301

PIQ602

PIR140

2

PIQ702PI

R1901

PIQ802

PIR2002

PIQ902PIR2

501

PIQ1002

PIR2602

PIQ1102PIR3

101

PIQ1

202

PIR320

2

PIC3502

PICO

N103

PIIC103

PIR3701NLnF1 PIC4202

PICO

N203

PIIC203


PICO

N303

PIIC303


PICO

N403

PIIC403

PIR4401NLnF4

PIC5102

PICON503

PIIC503

PIR4601

NLnF5PIC5402

PICON603

PIIC603

PIR4801

NLnF6

PIIC1010

PIM10G1

PIR5

02

NLPWM1

PIIC2010

PIM10G2

PIR1

102

NLPWM2

PIIC3010

PIM10G3

PIR1

702

NLPWM3

PIIC4010

PIM10G4

PIR2

302

NLPWM4

PIIC

5010

PIM1

0G5

PIR2902

NLPWM5

PIIC

6010

PIM1

0G6

PIR3502

NLPWM6

PIC402PIC501

PIC3401

PID2001

PIIC1012

PIIC1016

PIM10U

PIP501

PIR601

PIT102PIT103

PIC1402PIC1501

PIC4401

PID2

201

PIIC3012

PIIC3016

PIM10V

PIP502

PIR1801

PIT302PIT303

PIC2402PIC2501

PIC5001

PID2401

PIIC

5012

PIIC

5016

PIM10W

PIP503

PIR3001

PIT502PIT503

Figure A.4: Schematic for the power stage of the inverter circuit.



A.2.2 Control Stage Schematics

The complete control schematics for the three-phase inverter circuit are givenin this section. The schematic containing the dsPIC, DAC and magnetic pick-up interface circuit is shown in Fig. A.5. The schematic for the analog part ofthe control circuit is shown in Fig. A.6.



11

22

33

44

DD

CC

BB

AA

1 2 3

P1 Mag

netic

Pic

kup

1

3

BA

L/ST

B6

BA

L5

V-

42

7

V+

8IC

1

LM31

1P

GN

D

R1

3K3

R2

3K3

R3

10K

R4

10K

GN

D

+15V

-15V

C1

100n

F

C2

100n

F

GN

D

+5V

R5

1K8

R6

22K

R7

10K

R8

1KG

ND

MC

LR1

AN

0/V

REF

+/C

N2/

RB

02

AN

1/V

REF

-/CN

3/R

B1

3

AN

2/SS

1/LV

DIN

/CN

4/R

B2

4

AN

3/C

N5/

RB

35

AN

4/IC

7/C

N6/

RB

46

AN

5/IC

8/C

N7/

RB

57

PGC

/EM

UC

/AN

6/O

CFA

/RB

68

PGD

/EM

UD

/AN

7/R

B7

9

AN

8/R

B8

10

VD

D11

VSS

12

OSC

1/C

LKI

13

OSC

2/C

LKO

/RC

1514

EMU

D1/

SOSC

I/T2C

K/U

1ATX

/CN

1/R

C13

15

EMU

C1/

SOSC

O/T

1CK

/U1A

RX

/CN

0/R

C14

16

INT0

/RA

1117

IC2/

INT2

/RD

918

OC

4/R

D3

19

VSS

20

VD

D21

OC

3/R

D2

22

IC1/

INT1

/RD

823

EMU

C3/

SCK

1/R

F624

EMU

D3/

U1T

X/S

DO

1/SC

L/R

F325

U1R

X/S

DI1

/SD

A/R

F226

U2T

X/C

N18

/RF5

27U

2RX

/CN

17/R

F428

C1T

X/R

F129

C1R

X/R

F030

VSS

31

VD

D32

EMU

D2/

OC

2/R

D1

33EM

UC

2/O

C1/

RD

034

AN

12/C

OFS

/RB

1235

AN

11/C

SDO

/RB

1136

AN

10/C

SDI/R

B10

37A

N9/

CSC

K/R

B9

38

AV

SS39

AV

DD

40

IC3

DSP

IC30

F401

3-30

I/P

VO

UTB

1V

OU

TA2

VSS

3

VR

EFA

4

VR

EFB

5

GN

D6

LDA

C7

RS

8

CS

9

CLK

10

SDI

11

VR

EFD

12V

REF

C13

VD

D14

VO

UTD

15V

OU

TC16

IC4

AD

7398

BR

Z

IN2

TEM

P3

GN

D4

TRIM

5

OU

T6

NC

7N

C8

NC

1

IC5

REF

02A

P

+15V

GN

DC3

100n

FC

410

0nF

C6

1uF

+G

ND

C5

100n

F8 5

2 3

4

6

7

1

IC2

OP0

7CP

5VP

C7

100n

F

C8

100n

F

GN

D

5VP

5VP

SDI

SDI

SCK

SS

SS

SCK

GN

D

MP

MP

Tp

1 2

X1

10M

HZ

C9

22pF

C10

22pF

DG

ND

IN1

2

OU

T3

GN

D

VS

MC

7805

CT

+15V

+5V

5VP

GN

D

+5V

DG

ND

GN

D

C11

100n

FC

1210

0nF

Ioz5V

P GN

D

PWM

+5V

R9

0K22

R11

0K22

R12

0K22

R13

0K22

DG

ND

DG

ND

D2

D3

D4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

P2 Hea

der 1

6

+15V

-15VG

ND

Ia Ib Ic

PWM

IcIbIaTp Ioz

D5

DG

ND

DG

ND

CN

Err

NO

CN

Err

NO

TEM

P

TEM

P

PIC1

01PI

C102

COC1

PIC2

01PI

C202

COC2

PIC301PIC302COC

3PIC401PIC402

COC4

PIC501PIC502COC5

PIC601PIC602COC

6PIC701PIC702

COC7

PIC801PIC802COC

8

PIC901

PIC9

02

COC9

PIC1

001

PIC1002

COC1

0

PIC1101PIC1102CO

C11

PIC1201PIC1202CO

C12

PID2

01PI

D202

COD2

PID3

01PI

D302

COD3

PID4

01PI

D402

COD4

PID5

01PI

D502

COD5

PIIC101

PIIC102

PIIC103

PIIC104

PIIC105

PIIC106

PIIC107

PIIC108

COIC1

PIIC201

PIIC202

PIIC203

PIIC204PIIC205

PIIC206

PIIC207PIIC208

COIC2

PIIC301

PIIC302

PIIC303

PIIC304

PIIC305

PIIC306

PIIC307

PIIC308

PIIC309

PIIC3010

PIIC3011

PIIC3012

PIIC3013

PIIC3014

PIIC3015

PIIC3016

PIIC3017

PIIC3018

PIIC3019

PIIC3020

PIIC3021

PIIC3022

PIIC3023

PIIC3024

PIIC3025

PIIC3026

PIIC3027

PIIC3028

PIIC3029

PIIC3030

PIIC3031

PIIC3032

PIIC3033

PIIC3034

PIIC3035

PIIC3036

PIIC3037

PIIC3038

PIIC3039

PIIC3040CO

IC3

PIIC401

PIIC402

PIIC403

PIIC404

PIIC405

PIIC406

PIIC407

PIIC408

PIIC409

PIIC

4010

PIIC4011

PIIC

4012

PIIC4013

PIIC4014

PIIC4015

PIIC4016

COIC4

PIIC501

PIIC502

PIIC503

PIIC504

PIIC505

PIIC506

PIIC507

PIIC508

COIC5

PIP101

PIP102

PIP103

COP1

PIP201

PIP202

PIP203

PIP204

PIP205

PIP206

PIP207

PIP208

PIP209

PIP2010

PIP2011

PIP2012

PIP2013

PIP2014

PIP2015

PIP2016

COP2

PIR1

01PI

R102

COR1

PIR2

01PI

R202

COR2

PIR3

01PI

R302

COR3

PIR401PIR402 COR4

PIR501PIR502COR

5

PIR601PIR602COR

6

PIR701PIR702COR

7

PIR801PIR802COR

8

PIR9

01PI

R902

COR9

PIR110

1PIR

1102

COR1

1

PIR1

201

PIR1

202

COR1

2

PIR1

301

PIR1

302

COR1

3

PIVS01

PIVS02

PIVS03

COVS

PIX101 PIX102COX1

PIC502

PIC1202

PIIC105

PIIC106

PIIC108

PIIC301

PIIC3011

PIIC3021

PIIC3032

PIR502PIR702

PIVS03

PIC1

01

PIC302

PIC1102

PIIC207

PIIC502

PIP201

PIP202

PIVS01

PIC2

01

PIIC204

PIP205

PIP206

PIC402

PIC602PIC702

PIC802

PIIC302

PIIC3040

PIIC404

PIIC405

PIIC408

PIIC4013

PIIC4014

PIIC506

NL5VP

PIIC307

PIP209

NLCN

PIIC308

PIP2010

NLErr

PIC1

02

PIC2

02

PIC301PIC401

PIC501

PIC601PIC701

PIC801

PIC901

PIC1

001

PIC1101PIC1201

PID2

02

PID3

02

PID4

02

PID5

02

PIIC101

PIIC104

PIIC303

PIIC3012

PIIC3020

PIIC3026

PIIC3031

PIIC3039

PIIC403

PIIC406

PIIC407

PIIC

4012

PIIC504

PIP102

PIP203

PIP204

PIR401

PIR801

PIVS02

PIIC402

PIP2013

NLIaPIIC401

PIP2014

NLIb

PIIC4016

PIP2015

NLIc

PIIC306

PIP208

NLIoz

PIIC107

PIIC3023

PIR501 PIR602

NLMP

PIC9

02PIIC3013

PIX101

PIC1002

PIIC3014

PIX102

PID2

01PI

R902 PID3

01PI

R120

2

PID4

01PIR

1102

PID5

01PI

R130

1

PIIC102

PIR601

PIR701 PIR802

PIIC103

PIIC206

PIR3

02

PIIC201

PIIC202

PIR1

02

PIR3

01 PIIC203

PIR2

02 PIR402PIIC205

PIIC208

PIIC304

PIIC3010

PIR9

01

PIIC3016

PIR1

201

PIIC3017

PIIC3018

PIIC3027

PIIC3028

PIR1

302

PIIC3029

PIIC3030

PIIC3033

PIIC3034

PIIC3035

PIR110

1

PIIC3036

PIIC3037

PIIC3038

PIIC4015

PIIC501

PIIC503

PIIC505

PIIC507

PIIC508

PIP101

PIR1

01

PIP103

PIR2

01

PIIC309

PIP2011

NLNO

PIIC3019

PIP2016

NLPW

M

PIIC3024

PIIC

4010

NLSC

K

PIIC3025

PIIC4011

NLSD

IPIIC3022

PIIC409

NLSS

PIIC3015

PIP2012

NLTE

MP

PIIC305

PIP207

NLTp

Figure A.5: Schematic for the inverter digital control circuit.



11

22

33

44

55

66

77

88

DD

CC

BB

AA

12

Y1

2MH

zR1 10

MC1 22

pFC2 22

pF

RST

1

CLK

9

D0

3Q

02

D1

4Q

15

D2

6Q

27

D3

11Q

310

D4

13Q

412

D5

14Q

515

VCC

16

GN

D8

IC2

M74

HC1

74B

1R

RST

1

CLK

9

D0

3Q

02

D1

4Q

15

D2

6Q

27

D3

11Q

310

D4

13Q

412

D5

14Q

515

VCC

16

GN

D8

IC3

M74

HC1

74B

1R

R2 1KR3 1K

C4 100n

F

C6 100n

F

C3 100u

FC5 10

0uF

+5V

56

IC1C

M74

HCT

14B

1110

IC1E

M74

HCT

14B

+5V

+5V

+5V

12

IC1A

M74

HCT

14B

34

IC1B

M74

HCT

14B

98

IC1D

M74

HCT

14B

2 31

A

8 4

IC4A

LF35

3N56

7B

8 4

IC4B

LF35

3N

R5 12K

R4 12K

R7 330KR6 33

0K

R8 12K

R9 12K

1312

IC1F

M74

HCT

14B

+15V

+15V

-15V

-15V

C9 100n

F

C8 1nF

C7 1nF

GN

DG

ND

GN

D

Vtri

GN

DG

ND

GN

D

1 2

P1 12V

Sup

ply+1

2V 0VV

in-

1

Vin

+2

Vou

t+3

COM

4

Vou

t-5

IC5

DK

E10A

-15

+15V

-15VC1

210

0uF

C13

100u

F

C14

100n

F

C11

100n

FIN

1

2

OU

T3

GN

D

VS1

MC7

805C

T+1

5V+5

V

C15

100n

FC1

610

0nF

C17

100u

F

GN

DG

ND

C10

100n

F

+5V

GN

D

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

P2

Hea

der 1

6

Ia Ib Ic PWM

Ioz

Tp

GN

D

+15V

-15V

8

1

4

32IC

6ALF

353N

8 4

756

IC6B

LF35

3N

8 4

756

IC8B

LF35

3N

8

1

4

32IC

12A

LF35

3N

8 4

756

IC28

BLF

353N

8

1

4

32IC

8ALF

353N

+15V

+15V

+15V

-15V

-15V

-15V

IN2

TEM

P3

GN

D4

TRIM

5

OU

T6

NC

7N

C8

NC

1

VR1

REF0

2AP

C30

100n

FC3

110

0nF

+15V

GN

DG

ND

+5V

P

Vae

Vbe

Vce

GN

D

R27

120K

R29

120K

R30

470K

R31

22K

R32

22K

R33

470K

C33 1u

F

C34

1uF

+15V

-15V

GN

D

+15V

-15V

R34

10K

GN

DR35

33K

+5V

P

Dea

dT

567

B8 4

IC23

BLF

353N

2 31

A8 4

IC23

ALF

353N

+15V

+15V

-15V

-15V

R80

4K7

R81

4K7

R79

4K7

R82

4K7

R86

4K7

R84

4K7

R85

4K7

R83

4K7

GN

DV

eS2

VeS

1

Vae

Vae

1

23

4

5

6

7

8 IC24

AD

790J

N

1

23

4

5

6

7

8 IC25

AD

790J

N

GN

D+1

5V

+15V

-15V

-15V+5

V

+5V

C58

100n

F

C57

100n

F

C56

100n

F

C60

100n

FG

ND

GN

D

GN

D

GN

DV

tri

Vtri

GN

D

GN

D

Dea

dT

1 23

IC14

A

SN74

HC0

8N

4 56

IC14

B

SN74

HC0

8N

89 10

IC14

C

SN74

HC0

8N

12 1311

IC14

D

SN74

HC0

8N

1 23

IC15

A

SN74

HC0

8N

4 56

IC15

B

SN74

HC0

8N

89 10

IC15

C

SN74

HC0

8N

12 1311

IC15

D

SN74

HC0

8N

1 2 4 5

6

IC16

A

SN74

HC2

1N

9 10 12 13

8

IC16

B

SN74

HC2

1N

8

1

4

32IC

17A

LF35

3N

8 4

756

IC17

BLF

353N

R36

1K

+5V

P

D7

BAT8

5D

8BA

T85

+15V

+15V

-15V

-15V

Ioz

GN

D

1 2 3

P7 PWM

1

1 2 3

P8 PWM

2

nF nF

Vsa

t1

567

B8 4

IC18

BLF

353N

2 31

A8 4

IC18

ALF

353N

+15V

+15V

-15V

-15V

R38

4K7

R39

4K7

R37

4K7

R40

4K7

R44

4K7

R42

4K7

R43

4K7

R41

4K7

GN

DV

eS4

VeS

3

Vbe

Vbe

1

23

4

5

6

7

8 IC19

AD

790J

N

1

23

4

5

6

7

8 IC20

AD

790J

N

GN

D+1

5V

+15V

-15V

-15V+5

V

+5V

C37

100n

F

C36

100n

F

C35

100n

F

C39

100n

FG

ND

GN

D

GN

D

GN

DV

tri

Vtri

GN

D

GN

D

Dea

dT

1 2 3

P9 PWM

3

1 2 3

P10

PWM

4

nF nF

567

B8 4

IC26

BLF

353N

2 31

A8 4

IC26

ALF

353N

+15V

+15V

-15V

-15V

R46

4K7

R47

4K7

R45

4K7

R48

4K7

R52

4K7

R50

4K7

R51

4K7

R49

4K7

GN

DV

eS6

VeS

5

Vce

Vce

1

23

4

5

6

7

8 IC21

AD

790J

N

1

23

4

5

6

7

8 IC22

AD

790J

N

GN

D+1

5V

+15V

-15V

-15V+5

V

+5V

C43

100n

F

C42

100n

F

C41

100n

F

C45

100n

FG

ND

GN

D

GN

D

GN

DV

tri

Vtri

GN

D

GN

D

Dea

dT

1 2 3

P11

PWM

5

1 2 3

P12

PWM

6

nF nF

Vsa

t2

Vsa

t3

Vsa

t4

Vsa

t5

Vsa

t6

Vsa

t1

Vsa

t2

Vsa

t3

Vsa

t4

Vsa

t5V

sat6

Vbu

s

PWM

Tem

pnF

Tem

p

81

432

IC27

ALF

353N

8 4

756

IC27

BLF

353N

R53

1K

+5V

P

D9

BAT8

5D

10BA

T85

+15V

+15V

-15V

-15V

+15V

-15V

+5V

P

8 4

756

IC12

BLF

353N

8

1

4

32IC

28A

LF35

3N

+15V

-15V

R54

8K2

R55

56K

R56

390K

R57

390K

R58

56K

R59

8K2

GN

D

12

P13

Vba

t

12

P14

Vbu

s

GN

D

1 2

P15

Vte

mp

+15V

-15V

GN

D

+15V

-15V

+5V

C49

100n

FC4

810

0nF

C47 10

0nF

GN

D

8 4

756

IC30

BLF

353N

+15V

-15V

R62

560K

R63

39K

R64

8K2

R65

560K

R66

39K

R67

8K2

2 31

A8 4

IC30

ALF

353N

GN

D

+15V

-15V

+5V

P

IN2

VTE

MP

3

GN

D4

TRIM

5O

UT

6N

C8

NC

7N

C1

IC31

REF0

3GP

+5V

GN

D

Vof

faR6

810

K

R71

4k7

R72

4K7

R73

4K7

R74

4K7

R75

4K7

R76

4K7

R77

4K7

R78

4K7

R87

4K7

R88

4K7

R89

4K7

R90

4K7

GN

D

GN

D

GN

D

Ia Ib Ic

C50

100n

F

C51

100n

F

C52

100n

F

C53

100n

F

C54

100n

F

C6210

0nF

C63

100n

F

C65

100n

F

GN

D

+5V

C55

100n

F

GN

DGN

D

GN

DGN

D

GN

D

GN

D

C66

100n

F

1

3

BAL/

STB

6

BAL

5

V-

42

7

V+

8IC

29

LM31

1P

R69

1K2

R70

22K

R91

10K

Vbu

s

GN

D

+15V

-15V

GN

DG

ND

-15V

R92

1KR9

3

330K

R94

1KR9

5

330K

R96

1KR9

7

330K

R98

330K

R99

1K R100

1KR1

01

330K

R102

1KR1

03

330K

-15V

-15V

C44

100n

F

GN

D

+5V

Err

Err

C64

1nF

C71 1n

F

C70

1nF

C67 1n

F

C68

1nF

C69 1n

F

R10

1K

GN

D

C18

100n

F

C20

100n

F

C19

100n

F

C21

100n

F

+15V

GN

D

R11

4K7

R12

4K7

R13

4K7

R14

4K7

R15

4K7

R16

4K7

C22

100n

F

C23

100n

FC2

410

0uF

C25

100u

F

R24

4K7

R25

4K7

R26

4K7

R23

4K7

R17

10K

R18

10K

R19

10K

R20

22K

R21

22K

R22

18K

1 2 3

P6 CS F

B

8

1

4

32IC

9ALF

353N

8 4

756

IC9B

LF35

3N

8

1

4

32IC

10A

LF35

3N

8 4

756

IC10

BLF

353N

+15V

+15V

+15V

+15V

-15V

-15V

-15V

-15V

R61

10K

R60

4K7

R104

10K

R105

3K3

R106

3K3

R107

33K

R108

33K

R109

3K3

R110

3K3

C26

100n

F

C27

100n

F

GN

D

+5V

+5V

P

GN

D

GN

D

Idcf

b

Idcf

b

GN

D

GN

D

Idc

C28

100n

F

GN

D

C29

100n

F

GN

D+5V

P

+5V

P

PIC101PIC102CO

C1PIC201PIC202

COC2

PIC301 PIC302CO

C3PIC401PIC402

COC4

PIC501 PIC502

COC5

PIC601PIC602COC

6

PIC701PIC702CO

C7

PIC801

PIC8

02

COC8

PIC9

01PIC902

COC9

PIC1001PIC1002COC10

PIC1101

PIC1

102

COC11

PIC1201

PIC1

202

COC12

PIC1301

PIC1

302

COC13

PIC1401

PIC1

402

COC14

PIC1501PIC1502COC15

PIC1601PIC1602COC16

PIC1701 PIC1702

COC17

PIC1801PIC1802COC18

PIC1901PIC1902COC19

PIC2001

PIC2002

COC20

PIC2101PIC2102COC21

PIC2

201

PIC2202

COC22

PIC2301PIC2302COC23

PIC2401 PIC2402

COC24

PIC2

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PIP1302PIR5

601

PIP1401 PIR

6501

PIP1

402PIR6

201

PIR902

PIR1

001

PIR1

101

PIR7

702

PIR120

1PIR7801

PIR1

301

PIR7

302

PIR140

1PIR7401

PIR1

501

PIR8

902

PIR1

601

PIR9001

PIR3401PIR3501

PIR5

501

PIR5

602

PIR570

2PIR580

1

PIR6002PIR6

102

PIR6103

PIR6

202PIR630

1

PIR650

2PIR660

1

PIR107

02PIR

10902

PIR10801 PIR11002

PIVR101

PIVR103

PIVR105

PIVR107

PIVR108

PIIC

1402

PIIC

1405

PIIC

1401

0

PIIC

1401

3

PIIC

1503

PIIC

1501

0

PIIC

1501

3NLn

F

PIIC

1505

PIP2016

NLPWM

PIIC1501

PIP2012

NLTemp

PIC1802PIP207

PIP1501

NLTp

PIC6

402

PIIC607

PIR1

102

PIR8

001

PIR8

501

NLVae

PIC700

2 PIIC

801

PIR1

302

PIR3

801

PIR4

301

NLVbe

PIIC1609

PIIC2907

PIR6901

PIR7

001

NLVb

us

PIC680

2

PIIC

807

PIR1

502

PIR4

601

PIR5

101

NLVce

PIIC2301

PIR8202

PIR9

201

NLVeS1

PIIC2307

PIIC2503

PIR8602

NLVe

S2

PIIC1801

PIR4002

PIR9

601

NLVeS3

PIIC1807

PIIC2003

PIR4402

NLVe

S4

PIIC2601

PIR4802

PIR100

01

NLVeS5

PIIC2203

PIIC2607

PIR5202

NLVe

S6

PIIC3106

PIR7

101

PIR7

501

PIR8

701

NLVo

ffa

PIIC1604

PIP703

NLVsat

1

PIIC1602

PIP803

NLVs

at2

PIIC1605

PIP903

NLVs

at3

PIIC1601

PIP1

003

NLVs

at4

PIIC

1601

2

PIP1

103

NLVs

at5

PIIC

1601

3

PIP1203

NLVsat

6

PIIC407

PIIC1903

PIIC2103

PIIC2403

PIR1

002

PIR9

401

PIR9

902

PIR102

01

NLVtri

Figure A.6: Schematic for the inverter analog control circuit.


Appendix B

Printed Circuit Boards

B.1 DC-DC Converter Printer Circuit Boards

The PCBs used for the dc-dc converter prototype circuit are given in thissection.

B.1.1 Power Stage PCB

The two PCBs used to generate the positive and negative dc bus are shown inFig. B.1 and Fig. B.2 respectively. The boards are made from 70 µm coppertracks on both the top and bottom layers. Each PCB contains a half-bridgeconverter topology, gate-drive circuitry and a pre-charge soft-start mechanismas well as current sense resistors.

157


APPENDIX B. PRINTED CIRCUIT BOARDS 158

Inductor

Pre-chargecircuit

MOSFET

Gate-drivecircuit

Current senseresistors

Buscapacitors

Inductor

Pre-chargecircuit

Gate-drivecircuit

Buscapacitors

MOSFET Current senseresistors

Figure B.1: PCB for the top-half of the dc-dc converter circuit producing+175 V.



Inductor

Pre-chargecircuit

MOSFET

Gate-drivecircuit

Current senseresistors

Buscapacitors

Inductor

Pre-chargecircuit

MOSFETCurrent sense

resistors

Gate-drivecircuit

Buscapacitors

Figure B.2: PCB for the bottom-half of the dc-dc converter circuit producing-175 V.



B.1.2 Controller PCB

The two-layer PCB containing the dc-dc converter control circuit is shown inFig. B.3. The tracks on both the top and bottom layers are made from 35 µmof copper. The PCB includes a DKE10-15A 10 W dc-dc regulated dual output(+15 V and -15 V) converter to power the control circuit from one of the 12 Vbatteries.

+5VRegulator

DKE10A15Converter

PWMSignals

PWMSignals

Carrier WaveformGeneration

Figure B.3: Control PCB of the dc-dc converter.



B.2 Inverter Printer Circuit Boards

The PCBs used for the inverter prototype circuit are given in this section.

B.2.1 Power Stage PCB

The PCB used to implement the power stage of the inverter circuit is shownin Fig. B.4. The board is made from 70 µm copper tracks on both the topand bottom layers. The PCB contains the three-phase half-bridge invertertopology located inside the IGBT module, gate-drive circuitry and the dc buscurrent sensor. The PCB includes a DKE10-15A 10 W dc-dc regulated dualoutput (+15 V and -15 V) converter to power the gate-drive circuitry from a12 V bench supply.

IGBT moduleGate-drivecircuitry

Three generator statorterminals

Allegro currentsensor

DC busterminals

Figure B.4: PCB for the power stage of the inverter circuit.



B.2.2 Controller PCB

The two PCBs containing the control circuitry used to control the IGBTs onthe power board are shown in Fig. B.5 and Fig. B.6 and contain the digitaland analog control circuits, respectively. Both PCBs are two-layer boards andthe tracks on the top and bottom layers are made from 35 µm of copper. Theanalog PCB includes a DKE10-15A 10 W dc-dc regulated dual output (+15 Vand -15 V) converter to power the control circuitry on both the analog anddigital PCBs from a 12 V bench power supply.

Magnetic pick-upsignal processing

Control boardinterface

DAC dsPIC

Figure B.5: PCB for the digital inverter control circuit.



dsPIC PCB placement

Carrier waveformgeneration

PWM SignalsPWM Signals

CS <3 AC

Figure B.6: PCB for the analog inverter control circuit.


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