Beyond Innovation: Dealing with the Risks and Complexity of Processor Design in 22nm

Carl Anderson

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Technology and Implementation

• Technology• Threshold voltage variation• Resistive wires• Radical ground rules• Power constraints

Implementation Discipline Transistors per designer Design Tools Education

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Miracle of 22nm

Mark Bohr, 2009 IEEE International Solid-State Circuits Converence

Multiple Billion Transistor Chips

GHz Frequencies

Multiple Cores

Huge Caches

GHz I/O

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Getting 22nm Designs Done

• Many hard technical problems in 22nm Litho and ground rule challenges

• Router complexities Transistor and wiring variability Power density limits Electron migration limits

• Have to have a design methodology that allows abstraction and design efficiency.

• Early technology models are goals not real data. Can not tune a design to the last %.

• A disciplined methodology keeps a design on schedule. Schedule is the most important design goal.

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Stability is #1 requirement of successful implementation

Design Management Is Like Piloting an Oil Tanker

Changing Directions Requires Deliberate Planning

Cannot Change Direction Quickly With the Wind (Whim)

Number 1 Reason for Late Projects

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Exponential Growth of Transistors But Not of Designers

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History of transistors per IBM microprocessor logic circuit designerNot SRAMs, I/O or Register Files

• 1990 – Bipolar Gate Arrays 20-50 Transistors per year

• 1995 – Custom CMOS Mainframe Microprocessor 1,000 – 7,000 Transistors per year

• 2000 – Custom Design Tools Mature & Synthesis in CPU 2,000 – 200,000 Transistors per year

• 2005 – Use of Library Cells in Custom Circuits, More Synthesis and Growable SRAMs and Register Files 10,000 – 1,000,000 Transistors per year

• 2010 – Structured Synthesis Circuits and Large Block Synthesis 40,000 – 5,000,000 Transistors per year

• Logic Circuit Designs are Becoming Integrators and Logic Designers

• No equivalent gains in logic design.

• All improvements in logic verification has been used to extend verification coverage.

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Logic Simulation - First Time Right – Boot OS on Day 1

• 1997 – Full Chip Simulation

8 Way system simulation

• 2001 – 16 Way system simulation – 3rd generation accelerator – 364B cycles

Power on Reset & lowest level firmware

• 2003 – 16 Way system with SMT2 (2 threads per core)

Systematic functional coverage driven verification at core level

• 2006 – 32 way system with I/O chip system - 740B cycles

Soft fail recovery – Virtual Bring Up > 1Trillion cycles (4th gen accelerator)

Full formal verification of FPU data flow

• 2008 - 32 way system, memory subsystem chips, I/O system chips

Power management verification, Virtual Bring Up, Firmware

5th gen accelerator >45 Trillion cycles

Sequential equivalence checking to avoid lengthy regression testing

Targeted use of multi-block level formal verification across all units

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Discipline is an important trait of a design implementation

A design leader has to understand discipline keeps the design on schedule

Once implementation of a design starts only innovation inside the box can be allowed

Design leader types

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Discipline is an important trait of a design implementation

• Managing Implementation

Saying NO to change and reducing churn.• Design changes, model changes, etc

GPA grades for all macros based on design status• All macros have 10s of subgrades.• All macros have to have a GPA of

4.0 for tape out.

Managing teams around the world.

• Rise of the Program Managers

Good or Evil?

Can technical leaders manage large designs?

Schedule vs Head CountA Previous Boss' View

Head Count

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Designers versus EDA Tools

• The most efficient way of improving a design is through intelligent iteration.

• Prefer EDA Tools that are fast and allow designers to iterate the design more often.

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Power4 Adders – A Lesson in Designers and Tools

• One adder on Power4 used dynamic circuits.

Allowed it in a moment of weakness

• Similar static adder on Power4

• Static adder delay was slightly better than the dynamic adder

Tools and the design allowed many iterations through the adder.

• Reduction of a logic stage better than infinite tuning.

The dynamic adder just made it through all the tools in time for the tape out.

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Reduction in circuit complexity

• Logic circuits are now all implemented in static CMOS circuits

• SRAMs and I/O circuits still complex analog circuits.

• No more logic circuit debates.

No more dynamic logic circuits

No more pass gate logic circuits

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Methodology & Technology Ogre – OK to say NONO

• Have to say NO to both bad ideas and good ideas to keep the technology and methodology from getting to complex.

There are limited resources to support all the inovative ideas.

• Hard to convince technology and EDA leaders that it is OK to say NO to new design methodology requests.

• Need to have a technology and methodology Ogre. A consensus mythology by committee will have to many elements and be to complex.

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Innovation Time

• Design Concept is the Time for Innovation.

• Many Innovations Cu BEOL, eDRAM, low k dielectric

Large block synthesis, Incremental tools, etc Multithreading, Decimal Floating Point, Cell Processor, etc

• All innovations need to be evaluated Customer value or development cost reduction Person Year and development cost Risk of success

• Implement only new and old innovations with real value. Explicitly state which innovations that would be implemented and which ones would not

be implemented. No waffling – Innovation not Chaos.

• Many Innovations are great and fun ideas but minimal value for the customer.

• Good designers know the costs of innovations

• Good leaders can make the trade-offs between innovations Understand how to manage with a budget.

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Stability of the Technology Models and Tools

• The innovation plan needs to involve the technology and tools development and support leaders. It is a partnership.

Innovation has to be supported by the technology & tools infrastructure.

Technology and tools need to be ready when needed.

Technology and tools leaders need to be realistic in what can be supported.

• Technology models and tools should be only be changed if there is significant danger of a hardware failure.

Churn even if well intentioned will cause delay.

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The Tentacles Of A New Design Element

• The DNA of designers and tool developers is to innovate and solve problems not to keep things simple.

• Even simple new design elements have tentacles into all parts of the design.

New Design Element

LVS

DRC

TEST

POWER

CHECKING

NOISE

Formal Verification

TIMING

SYNTHESIS

CLOCKING

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Education and Mentoring

• Education and Mentoring probably one of the weakest traits of technical leaders. A problem of time not ability

• Need to increase the skills of all designers to keep up with the increased complexity designs.

• Need to give honest and critical feedback to designers. Balance both feedback and education Giving grades helps to remove confusion in feedback discussion

• To many designers are letting the tools do the thinking. A designer should have an estimation of the result before getting the

result from a tool.

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Technology Wish List• Technology that is designed for automation and reliability

Not designed for absolute smallest features.

• Automation friendly ground rules Layout and wire routing automation are key to productivity. Ground rules that detail what you can do. Not what you can’t.

• Early reliability design and technology trade offs. High Frequency parts are operated at voltages above nominal Small wires and low k dielectrics require oversized wires to meet reliability

requirements on high performance paths. High power density areas on the chip.

• Keep technology model updates to a minimum Models are not that accurate to start with Each update drives significant work

• Keep early models realistic. Need to specify both performance and leakage

• Technology needs to add value to the end customer

• Technology leaders that can say NO.

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Wish List for Tools and Capabilities

• Faster turn around time on tools.

More iterations for designers.

Improved incremental design

• Improvement to logic design efficiency.

• Improvement to verification model generation efficiency.

• Better feedback and AI on failures.

• Better partnership with designers on cost of innovations.

• Tools leadership that says NO

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Summary• Discipline is how 22nm designs will meet their goals and schedules.

Not new but more important as complexity grows.

• Innovation in concept not chaos in implementation.

• Design efficiency needs to continue to increase to implement increasingly large designs with constant size design teams.

• Technology needs to be developed for automation and reliability.

• Designers are responsible for good designs and tools and tool developers need to be their partner and not their substitute.

• All innovations and risks need to be evaluated with respect to customer value.

• Keep it simple is just as important in multi billion transistor designs as it was in 10s of transistor designs.

• Design, Technology and EDA leaders need to take responsibility for overall design, discipline and strategy Tradeoffs between innovation and resource and schedule. Tradeoffs between innovation and customer value. Mentoring and Education of team