Beyond-CMOS Research and Benchmarking: An SRC Perspective · 2017-12-12 · 4 The Pursuit of...

Beyond-CMOSResearchandBenchmarking:AnSRCPerspectiveNovember29,2017

AnChenExecutiveDirector,NRI&nCORE

Outline

• Introduction• Beyond-CMOSresearchinNanoelectronics ResearchInitiative(NRI)

q NRIresearchscopeq HighlightsofNRIachievements

• LessonslearnedfromtheNRIprogram• What’snext?• Summary

2

3

SemiconductorResearchCorporation(SRC)

Private foundation that manages and promotes SRC student training,

tracking, and hiring into areas of interest for our

sponsors

FAMELEAST

C-SPINTerraSwarmCFAR

SONIC

• Center based research program with 6 focus areas

• 5 year duration using [3+2] model

• Longer term research• MCs support all areas• US researchØGov’t sponsor = DARPA

$40M

INDEXCNFDSWAN

SupplementalNSF Grants

• Center based research program with 3 focus areas

• 5 year duration using [3+2] model

• Longer term research• MCs support all areas• US researchØGov’t sponsor = NIST, NSF

$7M

• Individual project management• 12 themes• Shorter duration projects

(2-3 yrs.)• Nearer term research• Flexible MC engagements• International research OKØ Gov’t sponsors = NIST, NSF

T3S

SLD

SSB

PKG NMPLMD

I3T ESHEP3C

CSRCADT

AMS-CSD

$30M

4

ThePursuitofLow-PowerSwitches

Traditional performance improvements (clock freq.andILP)havebeen flattening due topowerconstraint.

Needlower-powerswitchesbeyondCMOS

1.0E+02

1.0E+03

1.0E+04

1990 1995 2000 2005 2010

Clo

ck S

peed

(MH

z)

103

102

104

2004 Frequency Extrapolation

Microprocessor Clock Frequency

Peak cut-off freq. vs. 1/Lg(Lee et al., IEDM 2007)

DeviceFrequency CircuitFrequency

Exascale computingchallenges:• Reducingpowerrequirements• Copingwithrun-timeerrors• Exploitingmassiveparallelism

“TheOpportunitiesandChallenges ofExascale Computing,”SummaryReportoftheAdvanced ScientificComputingAdvisoryCommittee(ASCAC) Subcommittee,DOEOffice ofScience(2010)

5

NRITimelineandResearchVectors20

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2009

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Phase 1 Phase 1.5 Phase 2

STAR

Tnet

star

ted

NISTpartnershipNSF partnershipNRIcenters

nCORE

NRIresearchvectors• Newlow-powerdeviceswithnewstatevariables

• Newwaystoconnectdevices• Newmethodsforcomputation• Newmethodstomanageheat• Newmethodsoffabrication

Outline




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Nanoelectronics ResearchInitiative(NRI)Takingcomputingbeyondthelimitationsofcurrenttechnology

UC Los AngelesUC BerkeleyUC IrvineUC Santa Barbara

Notre DamePurdue Penn StateUT-Dallas

UT-Austin RiceUT-Dallas NCSUU. Maryland Texas A&M

SUNY-AlbanyPurdue ColumbiaHarvard U. VirginiaGeorgia TechMIT

U. Nebraska-Lincoln

U. Delaware U. Wisconsin-

MadisonU. OaklandSUNY Buffalo UC-Irvine

U. AlabamaU. ArkansasBrownCaltechCMUU. ChicagoColumbiaCornellDrexelU. FloridaGeorgia TechHarvardUIUC

U. MarylandU. MassachusettsU. MichiganU. MinnesotaMITNebraska-LincolnNorthwesternNotre DameU. OklahomaPenn StateU. PennsylvaniaU. PittsburghPrincetonPurdueRochesterSUNY-BuffaloStanfordWisconsin-MadisonUC BerkeleyUC-IrvineUC-San DiegoUC-Santa BarbaraUC-RiversideU. Virginia Virginia CommonwealthYale

BenchmarkingGeorgia Tech

2008-20122006-2017

2013-2017

2006-2012

2006-2017

2015-2017

• >1500journalpapers

• >40patents• >300Ph.D./post-doc

Ø MRSECsupplement

Ø NEB2020Ø E2CDA

NRI: a program searching for the “next switch”

MajorNRIdevicecategoriesü Steepslopetransistorsü Spintronicsü vanderWaalsdevices

8

STARnet:SRC-DARPACollaborationSemiconductorTechnologyAdvancedResearchNetwork

Applied MaterialsNovellus

FAME Jane Pei-Chen Chang, Director The mission of FAME is to create and investigate new nonconventional atomic scale engineered materials and structures of multi-function oxides, metals and semiconductors to accelerate innovations in analog, logic and memory devices for revolutionary impact on the semiconductor and defense industries.

TerraSwarm Edward A. Lee, DirectorThe TerraSwarm Research Center aims to enable the simple, reliable, and secure deployment of a multiplicity of advanced distributed sense control-actuate applications on shared, massively distributed, heterogeneous, and mostly uncoordinated swarm platforms through an open and universal systems architecture.

C-SPIN Jian-Ping Wang, DirectorThe Center for Spintronic Materials, Interfaces and Novel Architectures (C-SPIN) seeks to overcome barriers to realizing practical spin-based memory and logic technology by assembling experts in magnetic materials, spin transport, novel spin-transport materials, spintronic devices, circuits, and novel architectures.

SONIC Naresh Shanbhag, DirectorSONIC will be guided by the following mission: To enable equivalent scaling in beyond-CMOS nanoscalefabrics by embracing their statistical attributes within statistical-inference-based applications, architectures, and circuits, to achieve unprecedented levels of robustness and energy efficiency.

LEAST Alan Seabaugh, DirectorThe Center for Low Energy Systems Technology (LEAST) explores the physics of new materials and devices to enable more energy-efficient integrated circuits and systems.

C-FAR Todd Austin, DirectorThe center's research agenda is guided by three initial technical vectors, whose intersections will help realize non-conventional architectures that address these pressing challenges: data-centric architectures, novel architectures based on emerging technologies, and beyond homogenous parallelism.

16 Universities 10 Universities

15 Universities

8 Universities14 Universities

10 Universities

Spintronics

vdW Mater.

Oxidesandinterfaces

Topologicalinsulators

Steep-slopedevices

2Dmaterials

NRI/WIN

NRI/MIND

SelectedHighlightsofNRIResearchAchievements

• InventedCu-basedlarge-scalegrapheneCVDgrowthtechnique§ Akeybreakthroughforgraphenegrowthachievedbyacademia-industrycollaboration;adoptedworldwideandcommercialized

• ProofofelectronopticsingraphenePNjunction§ Nametop10breakthroughsin2016byPhysicsWorld

• DemonstrationofelectricswitchingofboundarymagnetizationinCr2O3• Potentialforlow-powernonvolatilememoryandcomputing

• Exploreroom-temperatureexciton devicesin2Dheterostructures• Potentialforlow-powerswitchandelectronics-opticsintegration

• Inventedthe“negative-capacitanceFET”concept§ A low-powersteep-slopetransistordrivinginterestinferroelectrics

9S.Salahuddin andS.Datta,Nano Lett.8(2),405-410 (2008)

X.Li,etal,Science324,1312-1314 (2009)

S.Chen,etal,Science353,1522-1525 (2016)

X.He,etal,Nat.Mater.9,579-585 (2010);W.Echtenkamp, etal,Phys.Rev.Appl.7,034015-1-7 (2017)

M.M.Fogler,etal,Nat.Comm.5,1-5 (2014);E.V.Calman,etal,Appl.Phys. Lett.108,101901-1-4 (2016)

Outline




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LessonsLearnedfromtheNRIProgram

• Nobeyond-CMOSdevicehasbeenproventobecapableofreplacingCMOSforBooleanlogicandvonNeumannarchitectures.□ IfthereisaCMOSsolution,thedifficultyandrequirementofadoptingabeyond-CMOStechnologywillbesignificantlyhigher.

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12

Beyond-CMOSDeviceBenchmarking

Benchmarkingconsiderations:• Theoretical projection vs.experimental demonstration• Accuracyand rigorousness ofassumptions andparameters

ThedevelopmentofNRIbenchmarking

C.PanandA.Naeemi,DATE(2017)

32-bitadderenergyvsdelay

Phase1: ledbyKerryBernstein(IBM)• Buildcircuitgates(inverter,NAND, adder)withNRIdevicestobenchmark performance(delay,power, area)againstCMOS

• Consider circuitparameters,e.g.,spanofcontrol,noise immunity, logicaleffort

Phase2: ledbyDmitriNikonov andIanYoung(Intel)• Develop uniformandtransparent criteriaandmethodologies forbenchmarking

• Improvequalityofassumptions anddevicedataforbenchmarking

Phase3: ledbyAzadNaeemi (GeorgiaTech)• Expand benchmarkingtoSTARnet devices• Expand benchmarkingtonon-Boolean logicandmemoryapplications

PracticalChallengesofBeyond-CMOSDevices

• Difficulttoachievesustainableimprovement• Generationsofdimensionalscalingisnolongeravailable

• Adoptionbarrier:expensiveandinflexibleinfrastructure• Manufacturing,materials,designstoolsandlibrary,…

• Challengingtimelineforadoptionofanewtechnology

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Incubationtime:12-15yearsStrainedSi:1992– 2003

High-KMetalGate:1996– 2007Raisedsource/drain:1993–2009

Multi-gate:1997–2011

•Drop-inreplacementofCMOStransistors• CMOScompatibilityandenhancement• Significantlyimprovedperformance,reducedcost,ornovelfunctionalitybeyondthecapabilityofCMOS

Desirablefeaturesofanewtechnology



□ Therearestillinterestinglow-powerdevicemechanismsworthexploring

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LowPowerDeviceMechanisms

§ EnergyFiltering– Tunnel-FET–Graphene p-nJunctionDevice

§ InternalPotentialStep-up– Ferroelectric-GateFET

§ InternalTransduction– Spin-FET– ElectromechanicalRelay– PiezoElectronic Transistor(PET)

§ GatedPhaseTransition– Bi-layerPseudo-spinFET(BiSFET)

Deviceconcepts explored intheNRIprogram

Basicphysicalmechanisms definesthepotentialofadevice;however, non-ideal andparasiticcomponents determine deviceperformance.

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Low-PowerDevicesinE2CDA(NSF-SRCCollaboration)

2DElectrostrictiveFET(EFET) 3HJTFET

E-field→Strain→bandgapmodulation Tripleheterojunction↓

Greaterbuilt-in potential↓

Thinner barrier

S.Das,Sci.Rep.6,34811 (2016)



□ Therearestillinterestinglow-powerdevicemechanismsworthexploring□ Beyond-CMOSdevicesmayfindpromisingopportunitiesfornovelcomputingparadigmsbeyondBooleanlogicandvonNeumannarchitectures.

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ExamplesofBeyond-CMOSDevices“Idiosyncrasy”

• Device-levelreconfigurability

• Built-inmemoryinlogicswitches

• Tunableanalogbehaviors

• Programmablerandomness

• Computingelementswithcomplexfunctions,e.g.,nativemajoritylogic

• ……18

Hardwaresecurity,e.g.,logiccamouflaging,…

In-memorycomputing,memory-in-logic,nonvolatilelogic,…

Neuromorphiccomputing,analogcomputing,…

Probabilisticlogic,randomnumbergenerator,…

Moreefficientlogicdesignandcomputingsystems

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In/Near-MemoryComputingandNVLogic

• Breakthe“memorywall”:reducedatamovement, improveefficiencyandthroughput• Massiveparallelismandsuitabilityforbigdataapplications• Bit/gate-levelnonvolatiledatastorage

MTJ, ReRAM, FRAM, FeFET, PCM, Flash …

SRAM, FF, adder, CAM, LUT, FPGA, …

NV gates and logic

Nonvolatile switches

NVM

CMOS logic

FF: flip-flop; LUT: look-up tableCAM: content-addressable memory

Memory-enabledcomputing

Micron’s DRAM-based Automata Processor Nonvolatile (NV) logicbasedonNV-Memory elements andNVswitches

Challenges:• Speed• Endurance• Application specific

P.Dlugosch,etal,IEEETrans.Paral.Dist.Syst.25,3088 (2014)




• Novelmaterialandprocessingareessentialforbeyond-CMOSresearch.□ Thereissignificantmaterialandprocessingbarrierformostbeyond-CMOSdevices.□ Needtofocusandaddressthehardproblem.

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Beyond-CMOSDevicesExploredinNRI

Phonon

Photon

Phase

Exciton

Spin

Charge

Si, III-V Ferromagnetic materials

Ferroelectric materials

Graphene / CNT

TMD

nanophtonics

Thermal logic

BiSFET

Excitonic logic

Nanoribbon FET

PN junction e-lensing

spinFET

spin wave logic

spin torque logic

NML

spin Hall device

resonant injection FET

laterial TFET

TFET

ASL/CSL

NC-FET

ME-MTJ

Fe-FET

FTJ

Molecule / QD

QCA

spinFET

BisFET

ITFET

ITFET Excitoiclogic

TFET

TFET

spin valve/filter

spin tunnel junction

atomic switchVertical hetero TFET

1D TFET

superlattice TFET

spin wave

bi-layer device

graphene spin logic (spinFET, spin Hall, spin torque, etc.)

spin oscillator

Spin logic

spinFET

CDW

charge density wave (CDW)

MaterialsStat

e va

riabl

es

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GraphenePNJunction andBisFET

Exp.

[C. Pan, M. Elahi, A. Naeemi]S.Chen,etal,Science,353,1522 (2016)

AlainDiebold, NRIINDEXReview(2017)

• Edgeroughness• Junction roughness• Gatecontrol• Contact resistance• Collimation

BilayerPseudo-Spin FieldEffectTransistor(BiSFET)

Challenges:• Room-temperature exciton condensate• Chargeimbalance, interlayerrotation,freecarrieranddielectricscreening,…

S.K.Banerjee,etal,EDL30,158 (2009)

Graphene PNjunction device

Veselago lensing Exciton condensate

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Negative-CapacitanceFET(NC-FET)

NC-FETconcept(Proposedin2008)

Oneofthemostactivelypursuedsteepslopetransistors

FerroelectricHfOx alloys

FeFETmemory

NCFinFET

NC-FETwith1.5nmHfZrO

NC-pFET Ge/GeSn

K.S.Li,etal,IEDM2015

M.H.Lee,etal,IEDM2016

J.Zhou,etal,IEDM2016

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STARnet andNRIMaterialBenchmarking

• AcollaborativeeffortconductedbySTARnet andNRIPIstosummarizeandcomparenovelmaterialsproperties,performance,challenges,anddeviceapplicationsacrossresearchprograms.

• GuidedbyaMaterialBenchmarkingCommitteeformedbyindustryandacademia.• CurrentaccesslimitedtoSTARnet/NRIparticipants,withlong-termgoalofsharingwithbroadcommunity.

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Example:2DMaterialsandTopologicalInsulators

Southwest Academy of Nanoelectronics

Bilayer pseudo-spin FET (BiSFET) materialsInterlayer tunneling FET (ITFET) materials Topological Insulator Magneto-Electronics (TIME) materials

Monolayer graphene Bilayer graphene Hexagonal boron nitride MoS2 WSe2 MoTe2

Topological Insulators Ferromagnets

Bi2Se3 Bi2Te3 CoFeB Py Co

Depositionor Processing

Conditions

Deposition or Growth Method

CVD, exfoliation from bulk graphite

CVD, exfoliation from bulk graphite

Exfoliation from bulk,CVD

CVD, MBE, exfoliation from bulk

MBE, exfoliation from bulk

Exfoliation from bulk crystals

MBE for thin film, Bridgman

technique for bulk

MBE for thin film, Bridgman technique for

bulk

sputter deposition

Substrate(s)(typical) Copper foil, SiC Copper foil, SiC Copper Foil or SiC

CVD: SiO2, Si, Al2O3, HOPG

MBE: HOPG, Al2O3, epitaxial graphene

CVD: SiO2, Si, Al2O3, HOPG

MBE: HOPG, Al2O3, epitaxial graphene

N/A

Si, sapphire Si, sapphire Si

Deposition or Growth T (ºC)

~1,000 °C for Cu, ~1,400 °C for SiC

~1,000 °C for Cu, ~1,400 °C for SiC > 1,000 °C 700-800 °C 900-1000 °C N/A 150-200 °C 350 °C RT

Wafer scale process? YES YES NO

YES, but thickness uniformity unclear

YES, but thickness uniformity unclear

No

YES YES YES

Key Properties

Mobilityor

Curie Temp(ferromagnets)

~10,000 cm2/Vs at room temperature

~10,000 cm2/Vs at room temperature N/A

50 cm2/Vs at RT1,000-10,000 below

10K

100 cm2/Vs at RT1-3,000 cm2/Vs below 10 K

20 cm2/Vs at RT

3,000 cm2/Vs 1,700 cm2/Vs 728 – 1008 K 869K 1388

K

Bandgapor

Spin polarization (ferromagnets)

0 eV 0 – 0.2 eV 5-6 eV

Bulk: 1.2 eVSL: 2.1 eV (quasi-

particle gap); 1.9 eV (optical)

Bulk: 1.3 eV SL: 1.65 eV (optical

gap)

Bulk: 0.9 eVSL: 1.1 eV

3. eV 0.15 eV 55 % 48 –55%

35 –42 %

ApplicationDevice Driver BiSFET BiSFET, ITFET BiSFET, ITFET BiSFET, ITFET BiSFET, ITFET BiSFET, ITFET TIME TIME

Function in the Device

Channel (individual layer) material

Channel (individual layer) material

Substrate, inter-layer dielectric

Individual layer,tunnel barrier

Individual layer,tunnel barrier

Individual layer,tunnel barrier Spin channel Spin injector/collector

Material Propertiesor Attributes Critical to the

Device Application

Ability to dope extrinsically Yes (adatoms) Yes (adatoms) N/A

Yes (adatoms, oxygen

vacancies)

Yes(adatoms)

YesNot needed because of small

bandgap N/A

Ability to make ohmic contacts Yes Yes N/A

Yes(using graphene for

nFETs)

Yes(using Pt for pFETs) Yes N/A

Effective mass1 massless

~0.05me, varies with density and

transverse electric field

0.4me (DFT)not measured experimentally

~0.4me

Massless,Fermi velocity vF=4.5×105 m/s

N/ADirac point near mid-gap

Dirac point in valence band

Unique Properties Rotationally aligned double layers with accuracy < 3° Large effective mass Large effective mass





• Aholisticapproachisneededtoaddressnewbeyond-CMOSresearchdirections.□ Benchmarkingisessentialandneedstostartfromthebeginning.

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NewNSF-SRCInitiative:E2CDA

Electronic-Photonic Integration Using the Transistor Laser for Energy-Efficient ComputingU. Illinois/Urbana-Champaign, U. Chicago

EXtremely Energy Efficient Collective ELectronics (EXCEL)Notre DamePenn State, U. ChicagoGeorgia Tech, UC-San Diego

2D Electrostrictive FETs for Ultra-Low Power Circuits and ArchitecturesPenn State

Memory, Logic, and Logic in Memory Using Three Terminal Magnetic Tunnel JunctionsMIT

Center forExcitonic DevicesUC-San DiegoMIT UC-Santa BarbaraPrinceton

Energy Efficient Learning Machines (ENIGMA)UC-Berkeley Stanford

A Fast 70mV Transistor Technology for Ultra-Low-Energy ComputingUC-Santa BarbaraU. VirginiaPurdue

Energy Efficient Computing with Chip-Based PhotonicsColumbiaMITStanfordUC-San Diego

Self-Adaptive Reservoir Computing with Spiking Neurons: Learning Algorithms and Processor ArchitecturesTexas A&M

Target a 100X reduction or more in energy per delivered operation as compared to projected performance of conventional CMOS

architectures and deeply scaled technology at the end of the roadmap

Devices

Systemarchitectures

Interconnect

Circuits

Materials

Energy-Efficient Computing fromDevices toArchitectures

VerticalE2CDACenterExamples:EXCEL&ENIGMA

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computation complexity of dynamical systems, pursue physical hardware demonstration and quantify their efficacy in solving computationally hard problems that are finding ever expanding applications in high-performance data centers, real-time cyber-physical systems and computational medicine.

Over the next decade (until 2025), energy efficiency gains are expected from improved device technologies like fully depleted FinFETs, steep slope FETs, embedded non-volatile memory, circuit design techniques like fine-grained DVFS, heterogeneous integration solutions like 3D monolithic chips, special-purpose digital accelerators and architectural innovations like in-memory computing. Circa 2025, standby power will constitute a smaller fraction of the energy consumed, and active power will once again hold hostage energy efficiency due to slowdown in Moore’s Law (3nm node). Now is the time to rethink and reinvent the fundamental paradigm of computing to transcend the energy efficiency wall imposed by Boolean computing. This pursuit should be complemented by the realization that, in a fast evolving socially interconnected world, we are observing a seismic shift in the amount of unstructured data that need to be processed in real-time. Such processing does not necessarily conform well to the traditional von Neumann representation of the Turing Machine. Thus, we propose a hardware fabric in EXCEL based on the time evolution of coupled dynamical systems that will lead to the next-generation processor or coprocessor executing tasks that are computationally and, hence, energetically hard to solve today.

We draw inspiration from a multitude of examples of real time complex information processing occurring in natural dynamical systems, such as activation patterns of neural circuits, intra and extra-cellular signaling mechanisms, flow of information in social networks etc. Analytical solutions of such systems are rare and numerical simulations run for weeks on our fastest digital supercomputers due to the large number of data points in multiple dimensions. Yet the physical system itself computes its own dynamics in seconds! In this proposal, we show how to harness this extraordinary computing power in an experimentally accessible and scalable solid-state system at a chip scale. We show empirically how a coupled network of oscillators exhibiting electronic phase transitions inherently holds multi-dimensional spatio-temporal information, and how their synchronization dynamics computes the evolution of this large amount of information with unprecedented parallelism, higher speed to task completion and extreme energy efficiency. We harness the same physical hardware platform in conjunction with low voltage stochastic synaptic memory to implement dynamics of several classes of deep learning neural networks relevant in machine learning applications including spike-based reservoir computing.

To achieve our goals, we have assembled a multi-disciplinary group of computer scientists, mathematicians, architects, integrated circuit designers, device physicists and material scientists into a collaborative research center, EXCEL. (Fig. 2.)

We utilize insulator-to-metal electronic phase transitions in complex oxides arising from electron-electron and electron-lattice interactions to construct low power digital FETs, relaxation oscillators and spiking neurons. Doped oxides and/or layered oxy-chalcogenides are utilized for realization of analog memories with extremely low programmable voltages. The dynamics of phase synchronization with interacting oscillators enables implementation of various classes of convex and combinatorial optimization solvers. Intrinsic stochasticity of nanoscale phase transition memories enables implementation of probabilistic spiking neural networks (similar to stochastic counterpart of Hopfield networks) that offer significant

Figure 2: Programmatic overview of EXCEL research S.Datta,EXCELcenter reviewpresentation,2017

EXCEL:EXtremely EnergyEfficient CollectiveELectronics ENIGMA:Energy Efficient Learning Machines

37XEDPimprovement3Xareareduction

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Energy-Efficiencyvs.ComputingPrecision

• Oscillatory behavior• Analog modulation• Nonvolatile • Stochastic behavior• Low voltage/power• Small size• ……

Energy-efficient, data-intensive, cognitive applications

(low-precision)

High-performance scientific computing (high-precision)

Application space

q Isthereafundamentaltradeoffbetweenenergyefficiencyandprecision?

q Cantheseapplication-specificapproacheshelpHPC?

• Massively parallel • Highly scalable • Co-located data

storage & computing • Fault tolerant • Energy efficient• ……

Emerging devicecharacteristics

Novelarchitecturefeatures

Manyapproaches achieveenergyefficiency• For specificapplications• For finiteprecision requirement

Applications

Energy Delay

Area Precision

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ExtendBenchmarkingtoNon-BooleanComputing

Benchmarkingchallengesfornon-Booleancomputing:• Largevarietyofapplications, models, algorithms, implementations …• Numerous technology options withvarying levelofmaturity• Newfigures-of-merit andcriteria

Spindiffusion

Domainwall

SpinHalleffect

SpindiffusionDomainwall

SpinHall effect

AdvantagesofSpintronics forCNN






• Public-privatecollaborationiscriticalforfundingthebasicresearchneededtoadvancethesemiconductorandcomputingtechnologies.

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TheValueofResearchInvestment

• TheimportanceofscientificresearchshouldnotbeevaluatedsolelybasedonthemonetaryROI(returnoninvestment),butshouldalsoconsidertheRONI(riskofnoinvestment).

• Industryinvestmentisinevitablydrivenby“return”.□ Governmentfundingandpolicyguidanceareneededtodrivebasicresearch.

• Consortiummodelreducesrisk,leveragesresources,andpromotescollaboration.□ Achallenge:“sharedmind”inthepost-scalingandbeyond-CMOSera

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Public-PrivateCollaborationThroughSRC

IP

Research

NewTalent

ü TechnologyTransferü BestandBrightestü Create Solutions

SRCMemberCompanies

GovernmentAgencies

ü 1700 Studentsü 600Facultyü 120Universities

SRCin2016

Commercialization

Amechanism foreffectivepublic-private partnership&pre-competitive research

SRCConnection

ü IndustryRelevant Challengesü CompetitorswithCommonGoalsü Leveraged Researchü Gov’t&IndustryConnections

BestUniversities

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UniversityOutput

Outline




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NewScienceTeam(NST)https://www.src.org/about/nst/

Ext. CMOS

BeyondCMOS

RF, Analog

$$

$ $

JUMP nCORE

$

NST

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Joint University Microelectronic Program(DARPA)1. RF to THz Sensor and Communication Systems2. Distributed Computing and Networking3. Cognitive Computing4. Intelligent Memory and Storage5. Advanced Architectures and Algorithms6. Advanced Devices, Packaging, and Materials

nanoelectronic COmputing REsearch program(NSF, NIST, & Other Gov’t Agencies such as DOE*)I. Novel Computing ParadigmsII. Device, Interconnect, and Materials ResearchIII. Advanced Manufacturing and NanofabricationIV. Innovative Metrology and CharacterizationV. Computational models

*Ongoing talks,noconcreteplansyet!

NRIandSTARnet bothendin2017NRI nCORESTARnet JUMP

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JUMPProgramSixJUMPCentersRepresentSixJUMPThemes

Center1

Center3

Center2

Center4

RFtoTerahertzSensors and

CommunicationSystems (V)

DistributedComputingandNetworking(V)

CognitiveComputing(V)

IntelligentMemory andStorage (V)

AdvancedArchitectureandAlgorithms(H)

AdvancedDevices,Packaging,andMaterials (H)

Center6

Center5

Systems-Level

Circuit-Level

Ext.CMOS

BeyondCMOS

RF,Analog

JUMPreceived18fullproposalsrepresenting 304professors at47USuniversities

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nCORE ResearchScope5researchvectorsdefine vertically integrated research

I. Novelcomputingandstorageparadigms,andtheoryofoperation,beyond conventional CMOSdevices,beyond vonNeumann architectures, andbeyond classicalinformation processing andsensing

II. Fundamentalmaterial, device,andinterconnectresearch toenable novel computing andstorageparadigms III. Advancedmanufacturingandnanofabrication toenable thefabrication ofemerging devicesandsystemsIV. Innovativemetrologyandcharacterization tosupport basicdeviceandmaterial research,andtestplatforms

andstandards tobenchmark performance from devicesuptosystems V. Computationalmodels tosupport basic researchfrom emerging devicesandmaterials tonovel systems

Novel&computing&paradigms

Device,&interconnect,&&&material&research

Enable

Characterization&/metrology=Test&platforms/standards=

Advanced&manufacturing

Support

Modeling

Support

Support

I

II IVIII

V

AnIntegratedResearchStructure

Summary:LessonsLearnedfromtheNRIProgram





• Public-privatecollaborationiscriticalforfundingthebasicresearchneededtoadvancethesemiconductorandcomputingtechnologies.

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Beyond-CMOS Research and Benchmarking: An SRC Perspective · 2017-12-12 · 4 The Pursuit of...

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