Besser Materials Innovations SST Talk

8/13/2019 Besser Materials Innovations SST Talk

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Materials innovations are drivingdevice performancePaul R. Besser, Fellow

Solid State Technology WebcastDecember, 2013


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Agenda

2

The need for materials innovation

Examples of materials innovations

Challenges with new materials

1

2

3

A collaborative approach4

Paul Besser, SST Webcast 2013


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Agenda

3

1


Challenges with new materials

2

3


The need for materials innovation



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Market needs drive new requirements:

4

Performance, Power, Cost (PPC)

Multicoreprocessors

High resolutionscreens

Thinnerform factors

Higher data rates,longer battery life

The Convergence is Here

Communication Computing Consumer

Navigation Imaging Video

Performance*Power Cost/Area

A4 A5 A6 A7



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The impact of scaling

5Paul Besser, SST Webcast 2013


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Driving the leading- edge process roadmap

Production Development

* In collaboration with ST

Path-Finding



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Agenda

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The need for materials innovation1

2

Challenges with new materials3





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Innovations in silicon manufacturingnew materials enable innovation

11 Elements

+4 Elements

+45 Elements(Potential)



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Innovations are driven in three areas

Collaboration is Essential to Success

Economics and Environmental Friendliness

ImprovingDevice

Performance

Scaling

Dimensions

Evolving

Connectivity



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Improving performance is about shrinking andexpanding

Improving performance (data access speed, batterylife, etc) is much more than just shrinking thedimensions of the processor.

Novel materials innovations = device performanceimprovements

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CVD W

MOCVD TiN

CoSI2

Stress Liner

Si-Ge

FTEOS ILDCu Barriers

Cu wiring

Bulk Si

Al Wires

Si Strain

ILD Cu capsFTEOS ILD

SOI

Low K ILDCoWP cap

CPI

Low-K ESL

Ultra Low-K

ULK Cap

Eless Cu

High KMetal Gate

Gate First

Si orientation

Stress Liner

Si-C

Cu Contact

Dual Si2

AIR GAP

Porous LK

Cu Alloys

Eless Cu

ALD Metals

ReplacementMetal Gate

MIM CAP

TSVs

SiGe channel

Si-P

MIS

Dual Si2

Sel Metal caps

Porous LK

New Cu BM

Cu Alloys

Eless Cu

Fin FET

Multiple EWF

Si-50%GeGe MOS

MIM CAP II

TiSi2

ALD W

NiPtSi

Technology Node (nm)

350 250 180/130 90 65 /45 45/32 28/20 14/beyond

BEOL

Contacts

Device

Channel

Paul Besser, Semicon West 2013 Paul Besser, SST Webcast 2013


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Device Options: Planar and FinFET

Slide courtesy of Witek Maszara 11

FinFET uses vertical surfaces for channels, forming a double gate

SiO2 (BOX)SOI

S T I

drain

Planar (on SOI)

gate

source

substrate

Finsource

drain

SiO2substrate

FinFET (on SOI)

Paul Besser, Semicon West 2013


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Device performance: planar to FinFET

DensityScaling

GatePitch

Scaling

ContactWidth

Scaling

ContactResistance

Increase( Active power

needs toincrease)

GateLengthScaling

IoffIncrease(Stand-by

powerincrease)

FinFETs

12Slide courtesy of Witek Maszara


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Source-Drain engineering: stress Selective epi of SiGe replacing Si fin in S/D area adds stress to

PMOS FinFET channel.

Stress benefit saturates for fin recess ~20nm below STI surface 3D modeling

F i n

S/D Epi Fin Height=30nmFin width=14nm

Slide courtesy of Witek Maszara 13


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Migration from planar to FinFETs was enabled withnovel materials

In the last few years, the transistor migrated from SOI + Gate Firstmetal gate to FinFET + RMG, for improvedperformance.

While both integrations utilize NiPtSi, CVD TiN, ALD HK, and W contacts, additional novel materials

innovations enable this transition.

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2011 2013

Si-GeSiGe Channel

CVD W

NiPtSi

CVD TiN

ALD Metals

High K

ReplacementMetal Gate

FinFET

CVD W

NiPtSi

CVD TiN

High K

Metal Gate

Gate First

Paul Besser, Semicon West 2013 Paul Besser, SST Webcast 2013

D l f f bl


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Development of a manufacturable processrequires a fundamental understanding oftechnology interactions

Metallization challenges : Cu barriers must be thin, continuous, low resistivity

ALD barriers reduce line resistance Void-less Cu fill Pre-clean prior to barrier metal deposition Cu grain size and texture control

Dielectric challenges: Lower k dielectrics:

poorer mechanical stability moisture sensitive Topography and planarity from CMP Cap layer deposition process and material type

Reliability: BTS, TDDB, EM, SM

Metal/via patterning and etch: straight and smooth sidewalls tapered line and via profile residuals at via bottom

Example = BEOL



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Agenda

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Examples of materials innovations2



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Are materials changes easy?

Historically, materials changes have been challenging. Examples:

While there have been many selective deposition processesresearched, only 3 selective processes have made it into volumemanufacturing: salicides, selective epi Si-Ge, and CoWP metal caps

Case study1 : SiLK SiLK is a low-K polymeric insulator which was investigated as a low-K

dielectric for microprocessors. Spin-on dielectrics are challenged by thermal expansion issues, stress-

migration and other reliability issues In the end, SiLK was dropped.

Case study 2: NiSi (next slide) NiSi was under development by for >4 years before NiPtSi was HVM.

17Paul Besser, Semicon West 2013 Paul Besser, SST Webcast 2013


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Example: challenges with material changes

NiSi was in development by for >4 years before NiPtSi was inserted into HVM NiSi advantages: Lower Rs, lower thermal budget, formation on Si-Ge, linewidth independent

NiSi challenges: Fast diffusion and NiSi2 is stable phase (and will form!)

Pt additions increase silicide Rs, but also limit metal rich phases, alter silicide texture,retard NiSi 2 formation, and delay agglomeration

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D i f f r a c

t e d A n g

l e ( 2 )

J. Patton et al, ISSM (2004)

Nickel Silicide Technology, C. Lavoie, C. Detravenier and P.R. Besser, inSilicide Technology for Integrated Circuits (2005)

S. Thompson et al., IEEE IEDM, 3.2.1 (2002)

100 200 300 400 500 600 700 800 900

Temperature ( C)

0

50

100

150

200

250

Resistance(arb.units)

Ni-Si

Co-Si

CoSiCo2Si

CoSi2

Metal RichPhases NiSi NiSi2

o Paul Besser, SST Webcast 2013


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Agenda

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Examples of materials innovations2



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Materials innovations require early collaborationbetween tool suppliers, materials suppliers, andGLOBALFOUNDRIES

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Engaging early,deeply, openly, and

comprehensively

Collaborative InnovationTapping global talent

Jointly develop newtechnologies and

manufacturing solutions

Focused onshared success

Time to Everything!

Research

Development

Electrical testing, Yield

HVM

Materials Supply

(substrates, resists, gases,

abatement, slurry, targets,precursors, chemicals,and packaging matls )

HVM tooling(Chambers, Platforms,

Productivity)

Unit process

Integration



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Summary

Materials innovations driveperformance improvements in themicroelectronics industry, creatingfaster and smaller devices that use lessenergy and are more reliable.

Materials innovations presenttechnological and economicalchallenges.

Leading-edge nodes are seeing anexplosion of new materials.

Only collaboration can these materialsinnovations which drive performanceand reliability be introduced seamlesslyat an affordable cost and on time.

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cost value



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Trademark Attribution

GLOBALFOUNDRIES , the GLOBALFOUNDRIES logo and combinations thereof, and GLOBALFOUNDRIES other trademarks and service marks areowned by GLOBALFOUNDRIES Inc. in the United States and/or other jurisdictions. All other brand names, product names, or trademarks belong to theirrespective owners and are used herein solely to identify the products and/or services offered by those trademark owners.

2013 GLOBALFOUNDRIES Inc. All rights reserved.

Thank you

Besser Materials Innovations SST Talk

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