Benchmarking Circuits for Model Verification

1HICUM Workshop 2013

Benchmarking Circuits for

Model Verification

Electronics Research Laboratory/DIMESDelft University of Technology, The Netherlands

L. Vera and J.R. Long

May 27, 2013

Benchmarking Circuits for Model Verification 2

HICUM Workshop 2013 L. Vera and J. R. Long

Outline

Motivation

Broadband amplifier (small-signal circuit)- Measurements vs. simulations

- S-parameter verification

- Sensitivity analysis using HICUM

Static frequency divider (large-signal circuit)- Operating above the breakdown voltage

- ECL latch

- Measurement vs. simulation

Conclusions



Independent experiments are required to verify models

extracted from single transistor measurements

Design kit (DK) verification and performance benchmarking

of a technology using multi-transistor circuit configurations

– Early verification of model accuracy and device

performance improves DK quality

Hardware performance benchmarks to guide technology

development and improvements

Motivations



A benchmarking circuit should be:

1. Easy to test: simple set-up; data can be gathered quickly

2. Sensitive to process variation (i.e., can be used to

characterize spread)

3. More complex than a single device (i.e., not just repeating

single device measurements used for model extraction)

4. Differences between simulation and measurement can be

related or traced to model parameters

Benchmarking Circuit Characteristics



Broadband Amplifier

Potential applications:

Wideband gain block

Fiber-optic transceivers, mm-wave phased-array radar or

radio imaging

Digital radio and satellite transceivers



Broadband Feedback Amplifier

Simple biasing

2 port S-parameter characterization

Sensitive to processing variations

Possible to correlate measurements to model or processing

variations



Broadband Amplifier Design

S21 = - gmTotal (RF||RL) ≈ -gm2(RF||50Ω)

Rout= Rin = RF/(1-S21)

For a 50Ω input/output system at low frequency:



Broadband Amplifier Design

S21 = - gmTotal (RF||RL) ≈ -gm2(RF||50Ω) → gm2≈96mS

Rout= Rin = RF/(1-S21) → RF=50(5)=250

For a 50Ω input/output system at low frequency:



Broadband Amplifier Transistor Sizing

For maximum bandwidth:

Given IC2, Q2 is biased at peak fT (sets length L2 of Q2)

Length of Q1 (L1) optimized to provide best input/output

match at higher frequencies

Q1 also biased at peak fT (using RE1)



Ballast resistors RE1 and RE2 provide thermal stability (e.g.,

counteract rise of IC2 due to self-heating)

Adding RE2 decreases gmTotal; IC2 must be increased to

compensate

Broadband Amplifier Biasing



Transistor Bias Voltages

VCB of Q2 = VCE of Q1

Reduced breakdown voltage of newer technologies restricts VCB2

Simulation of Q2 must be accurate between BVCES and BVCEO



Broadband Amplifier Prototype

Feedback amplifier prototype in SiGe:

Low frequency gain of 12dB

Maximum f-3dB determined by the technology

50Ω input/output impedances for simple

characterization

G

S

G

G

S

G



Broadband Amplifier Measurements

Measurements: gain, bandwidth, input/output impedances, etc.

DC supplies

HP 4142B

Agilent 8361A PNA

PicoprobeGSG 110H

PicoprobeGSG 110H



Resistor values adjusted to post-fabrication values for simulation

Alpha and Beta models define different gm values: gm2_Alpha is

14% higher than gm2_Beta

Ballast resistor (RE2) reduces difference in gm to just 2%

Measurement vs. Simulations: LF Gain

11.5 dB

11.1 dB

11.35dB



Measurement vs. Simulations: HF Gain

Initial comparison of measurements vs. simulations showed a >40GHz

difference in -3dB bandwidth using Alpha model

CBC and CCS in Alpha model are one-half of Beta model values

Simulations using Beta model fit measurements better than Alpha model

55 GHz

54 GHz

95 GHz



Input and Output Impedances

|S11| for Alpha and Beta models do NOT agree with measurements

for f > 10GHz

Beta model predicts higher |S11| and |S22| than measured due to:

lower rπ, rb and ro, and higher CBC and CCS



Reconstructing the Amplifier

The amplifier was reconstructed using single transistor S-parameter

measurements (up to 50 GHz), ideal resistors and EM-simulation

datasets for the input and output transmission lines

Method does not account for biasing variations

Layout

Q2

RE1 RE2

RF

Q1

PAD + TL TL + PAD

R (ideal)Transistor

S-param.

Cadence Schematic



Reconstructed Amplifier Comparison

Reconstructed amplifier agrees better with measured data than

simulations with Alpha model

Differences between simulated and reconstructed |S11| are related

to transistor parameters rπ, rb and CBC



Modified Beta Model

Simulated |S11| and |S22| using modified Beta model (higher

CBC and CCS, and lower rπ, rb and ro) approaches

measurements better than original Alpha and Beta models



Monte Carlo and Modified Beta Model

Monte Carlo simulations for 100 cases (gray lines) show the circuit

sensitivity to processing variations

Measurements lie within the Monte Carlo simulation bounds

Simulation setting process parameters in the model close to

fabricated values (red lines) approaches measurements best



Increasing fmax

fmax may be improved changing rb, CBC , or both:

Lower R: 27% lower base resistance, 4% higher collector-base

capacitance, 14% higher fmax

Lower C: 29% lower collector-base capacitance, 20% higher

base resistance, 8% higher fmax

Lower RC: 20% lower base resistance and 34% lower collector-

base capacitance, 37% higher fmax

(E.2)fT

2⋅π⋅rb⋅CBC

fmax =



Broadband Amplifier Analysis

Small-signal amplifier model retains components dominant in the

frequency response

Dominant time constant of the simplified model (eq. E.1) examined

for optimization

(E.1)RF

1+ R’L+RF+ g’mR’LR’Gτp =

[Cin+Cµ(1+g’mR’L)]R’G+(CL+Cµ)R’L



Sensitivity Analysis Using HICUM

Four time constants (τi ) dominate the first pole of the amplifier

Reducing τ1 and τ2 benefit amplifier bandwidth the most

8.7

8.7

8.7

8.7

τ4 = CLR’L(%)

1.8

2

3

2.9

τ3 = CµR’L(%)

75.4

95.5

87.5

100

τTOT = Σ τi

(%)

24.4

33.2

37.2

42.4

τ2 = Cµ(1+gmR’L)R’G(%)

Lower RC

Lower C

Lower R

Fabricated

npn option

40.5

51.6

38.6

46

τ1 = CinR’G(%)



Simulations predict 19.5GHz higher -3dB bandwidth when CBC and

rb are optimized

1.39

1.06

1.10

1

-3dB BW

simulated

1.33

1.10

1.14

1

-3dB BW

analytical

Lower RC

Lower C

Lower R

fabricated

Process

1.37

1.08

1.14

1

fmax

55.7 GHz

50.5 GHz

53.6 GHz 70 GHz

S21

frequency (GHz)

S21 (d

B)

3dB

Sensitivity Analysis Using HICUM



Large-Signal Circuits

Large-signal circuit performance depends on:

Time-varying capacitances

Bias-dependent intrinsic base resistance

Non-quasi-static effects (NQS)

Potential candidates for study are:

Power amplifiers

Switching logic (e.g., frequency divider)



Operating Above Breakdown Voltage

SiGe HBTs reach higher speeds at the cost of reduced breakdown voltages

Some circuits may operate properly with VCE above

BVCEO (e.g., common base amplifier), but other configurations do not function properly under this

condition

Precise and accurate modeling above BVCEO

needed to predict circuit behavior when VCE > BVCEO



Static Divide-by-2

Large-signal benchmark circuit

Output is at one-half the frequency of the input signal

Metrics: maximum toggle frequency, rise/fall time, input

sensitivity, output voltage swing, etc.

Maximum operating frequency is limited by the delay of the

individual latch stages

Master/Slave D-type Flip-Flop

RF IN+ RF IN-

RF OUT+ RF OUT

GND GND

I1

I2V1

V2



ECL Latch

Speed is proportional to RC time

constant at node A as defined by:

CBC, CCS (Q1 and Q3), CBC and CBE

(Q5), and R1

Given an output voltage amplitude,

peak current in Q1,3 goes above

peak fT (i.e., higher diffusion cap.,

smaller R1 – effective RC reduction)

Q7 and Q8 sized to conduct peak

currents around peak fT

VCB of Q3 (and Q4) is VBE of Q5

(Q6), i.e., VCE~2VBE

Key circuit parameters are time

variant



Verifying Model Above Breakdown

Measured and simulated results agree in amplitude and output

frequency

Bias-T bandwidth (50GHz) limits measured rise/fall time

Full characterization of divider requires investment in (multiple) test

sources for K, Ka, V and W-bands

Measurement

200mV

133ps

Beta model

200mV

133ps

Alpha model

66ps



Conclusions

Benchmarking measurements motivate

modifications to transistor rπ, rb, ro, CBC and CCS

Model parameter accuracy improved by

correlating model simulations with benchmark circuit measurements (e.g., Monte Carlo

simulations of modified Beta model for the BBA)

Optimizing a benchmarking circuit is a quantitative

way of evaluating technology development scenarios (e.g., for fmax/fT)

Accurate models for VCE>BVCEO are required

Benchmarking Circuits for Model Verification

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