BEAGLEBONE BLACK ARCHITECTUREmeseec.ce.rit.edu/551-projects/spring2015/2-3.pdf · 2015-05-12 ·...
Transcript of BEAGLEBONE BLACK ARCHITECTUREmeseec.ce.rit.edu/551-projects/spring2015/2-3.pdf · 2015-05-12 ·...
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BEAGLEBONE BLACK ARCHITECTUREMADELEINE DAIGNEAU
MICHELLE ADVENA
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AGENDA● INTRO TO BEAGLEBONE BLACK● HARDWARE & SPECS● CORTEX-A8 ARMV7 PROCESSOR● PROS & CONS● VS RASPBERRY PI● WHEN TO USE BEAGLEBONE BLACK
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Website: http://beagleboard.org/blackWiki: http://elinux.org/Beagleboard:BeagleBoneBlack
Single Board ComputerLow CostSmall Size (Credit Card)Community Supported
Open Sourced (No Licenses Involved with BeagleBone materials)
Cortex-A8 ARM Processor from Texas Instruments
Simple to setup your own board (Linux comes installed)
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http://beagleboard.org/static/images/black_hardware_details.png
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http://cdn.arstechnica.net/wp-content/uploads/2013/04/beaglebone-specs.png
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SPECS
AM335x 1GHz ARM® Cortex-A8 Processor512MB DDR3 RAM4GB 8-bit eMMC on-board flash storage3D graphics acceleratorNEON floating-point accelerator2x PRU 32-bit microcontrollers
Latest: Rev C
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TECHNOLOGIESCortex-A8 Technologies Description
TrustZone Security Device Integrity / Secure Transactions
Jazelle RCT Acceleration / Thumb 2EE
Instruction Set
Fast & Responsive Java Applications
Thumb-2 Instruction Set Greater Performance With Less Code Size
NEON™ Advanced SIMD(+VFPv3) Enhanced Multimedia Experience
Superscalar ARMv7 Core Highest-performance mobile processor
http://processors.wiki.ti.com/index.php/Cortex-A8_Features
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NEON
★ SIMD (Single Instruction Multiple Data) accelerator processor
★ 64/128-bit Hybrid SIMD architecture
★ single instruction performs the same operation on multiple elements that are packed within registers
★ Parallel architecture
★ Two Integer 64-bit ALUs
★ Fully pipelined
http://processors.wiki.ti.com/index.php/Cortex-A8_Features
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NEON
❖ Two Integer 64-bit ALUs operating in parallel➢ Can perform 128-bit length equivalent ALU operation in 1 cycle
❖ Supports 128-bit data streaming from both L1D$ and L2$➢ Byte permute function allows for on-the-fly data shuffling
❖ Two Integer Multipliers of 32x16➢ Each can perform one 32x16, two 16x16 or four 8x8 operations in a
single pass➢ Support 32x32 operation in two passes
http://processors.wiki.ti.com/index.php/Cortex-A8_Features
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SMID LOAD/STORE
Native support for structures (e.g. complex numbers, pixels, coordinates)
Memory treated as an array of structures (AoS)
Eliminates ‘shuffling’ overhead
Optimised memory access as single transfer
Data arranged for efficient SIMD processing
http://processors.wiki.ti.com/index.php/Cortex-A8_Features
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BENEFITS OF NEON+ both aligned and unaligned data access
+ efficient vectorization of SIMD operations
+ both Integer and FP+ broader range of applications (compression decoding, 3D graphics)
+ tightly coupled to ARM core+ single instruction stream & unified view of memory
+ single development platform target+ simpler tool flow
+ large register file with multiple views+ efficient handling of data & minimizes memory accesses
+ better throughput performance
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CORTEX-A8
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HIGH-LEVEL BLOCK DIAGRAM
http://www.ti.com/lit/ds/symlink/am3358.pdf
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http://www.ti.com/lit/ds/symlink/am3358.pdf
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MPU SUBSYSTEM
http://www.ti.com/lit/ug/spruh73l/spruh73l.pdf
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ARM CORTEX-A8 MPU SUBSYSTEM
ARMv7 and Thumb 2 ISA
ISA Efficiency = 2.01 DMIPS/MHz
dual-issue, in-order execution engine
Integrated L1 and L2 caches with NEON™ SIMD (Single Instruction, Multiple Data) Media Processing Unit
Static Scheduling with Instruction Replay on Memory Stall
Fire-And-Forget Issue
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CACHE
● Split Level 1 Caches - Instruction and Datao Both 16 kBo 4-way Set Associativeo Single Cycle Load-Use Penalty
● Unified Level 2 Cache o 256 kBo 8-Way Set Associativeo Minimum Latency - 8 Cycleso High BW Interface to L1 Cache
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MEMORY: GPMC
Fully pipelined
Onboard flash: 4GB, 8-bit embeded MMC
SDRAM Mem: 512MB DDR3L 800MHz
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PIPELINEdual-issue, in-order
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CONTROL
95% Accuracy in Dynamic Branch PredictionDynamic branch predictor components● 512-entry 2-way BTB● 4K-entry GHB indexed by branch history and PC● 8-entry return stack
Branch resolution● resolved in single stage● maintains speculative and non-speculative versions of branch history and
return stack
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INSTRUCTION DECODE
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INSTRUCTIONDECODE
4 entry pending queue➔ decreases fetch stalls➔ increases pairing opportunitiesreplay queue: keeps instructions for reissue on memory system
stallscoreboard: static scheduling to predict register availabilitycross-checks in D3 allow issue of dependent instruction pairs
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INSTRUCTION EXECUTE
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❖ 2 symmetric ALU pipelines: Shift/ALU/SAT❖ Load/store pipe used by instructions in either pipeline❖ Multiply instructions are tied to pipe 0❖ All key forwarding paths supported❖ Static scheduling allows for extensive clock gating
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PIPELINE
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10 STAGE NEON PIPELINE
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NEON PIPELINE
❖ Instruction issue➢ static scheduling with fire-and-forget issue➢ 1 LS + 1 NINT/NFP can issue each cycle
❖ Execution pipelines➢ All pipelines are 64-bit SIMD➢ Floating-point MAC executed using both FADD and FMUL pipelines
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NEON: INTERFACING
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NEONBlock Diagram
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NEON16-Entry Instruction queueDual view register file● 32 x 64-bit● 16 x 128-bit6 Stage execution Pipeline● Integer● Single precision floating pointLoad store permuteNon-pipelined IEEE vector floating point support12 –Entry load data queue
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http://www.ti.com/lit/ds/symlink/am3358.pdf
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PRU-ICSSProgrammable Real Time Unit Subsystem and
Industrial Communication Subsystem Dual PRUsThree 120-byte register banks accessible by eachSupports e.g. EtherCAT, PROFIBUS, PROFINET, EtherNet/IP12KB of Shared RAM With Single-Error Detection (Parity)UART porteCAP moduleDual MII Ethernet PortsSingle NDIO Port
http://www.ti.com/lit/ug/spruh73l/spruh73l.pdf
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POWER
TPS65217C PMIC regulator + LDO
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BEAGLEBONE BLACK VS RASPBERRY PI
Base Cost $45 $35
Processor Speed 1 GHz 700 MHz
GPIO 65 pins 8 pins
Power Consumption 210-460 mA @ 5V 260-350 mA @ 5V
Onboard Storage 4 GB, SD SD card
Cache L1 - 32 kBL2 - 256 kB
L1 - 16 kBL2 - 128 kB
ISA Efficiency 2.01 DMIPS/MHz 1.25 DMIPS/MHz
RAM 512 MB DDR3L 512 MB SDRAM
Video Connections Micro HDMI HDMI, Composite
Audio Connections HDMI HDMI, 3.5 mm Jack
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WHEN TO USE THE BEAGLEBONE BLACK...
o Processing Speed is important
o Constrained Size Requirements
o Projects with Many Hardware Connections
o Projects that may be commercialized
o Open Sourced
o Non-Media Heavy Projects
o Raspberry Pi is a slightly better option here
o Simple Startup
o Linux Distro already installed
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REFERENCEAM335x Sitara Processors Technical Reference Manual (Rev. L)
http://www.ti.com/lit/ug/spruh73l/spruh73l.pdfAM335x Sitara™ Processors (Rev. H) http://www.ti.com/lit/ds/symlink/am3358.pdfNEON & VFP http://processors.wiki.ti.com/index.php/Cortex-A8Cortex A8 Arch http://processors.wiki.ti.com/index.php/Cortex-A8_ArchitectureA8 NEON Arch http://processors.wiki.ti.com/index.php/Cortex-A8_Neon_Architecture
logo (w/ raspi) from http://www.itclips.net/wp-content/plugins/rss-poster/cache/ef657_bbvrpi-e1374615365680.png
logo (larger, w/ wifi) from https://fleshandmachines.files.wordpress.com/2012/07/beagle.png
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QUESTIONS?