Bca 2nd sem-u-2.1-overview of register transfer, micro operations and basic computer organization...

Overview of Register Transfer, Micro Operations and Basic

Computer Organization and Design

Course: BCA-2nd Sem Subject: Computer Organization

And Architecture Unit-2

1

SIMPLE DIGITAL SYSTEMS

• Combinational and sequential circuits can be used to create simple digital systems.

• These are the low-level building blocks of a digital computer.

• Simple digital systems are frequently characterized in terms of– the registers they contain, and

– the operations that they perform.

• Typically,– What operations are performed on the data in the registers

– What information is passed between registers

2

MICROOPERATIONS (1)

• The operations on the data in registers are called microoperations.

• The functions built into registers are examples of microoperations– Shift

– Load

– Clear

– Increment

3

MICROOPERATION (2)

An elementary operation performed (during one clock pulse), on the information stored in one or more registers

R f(R, R)

f: shift, load, clear, increment, add, subtract, complement,and, or, xor, …

ALU(f)

Registers(R) 1 clock cycle

4

ORGANIZATION OF A DIGITAL SYSTEM[1]

- Set of registers and their functions

- Microoperations set

Set of allowable microoperations provided by the organization of the computer

- Control signals that initiate the sequence of microoperations (to perform the functions)

• Definition of the (internal) organization of a computer

5

REGISTER TRANSFER LEVEL[1]

• Viewing a computer, or any digital system, in this way is called the register transfer level

• This is because we’re focusing on– The system’s registers

– The data transformations in them, and

– The data transfers between them.

6

REGISTER TRANSFER LANGUAGE[1]

• Rather than specifying a digital system in words, a specific notation is used, register transfer language

• For any function of the computer, the register transfer language can be used to describe the (sequence of) microoperations

• Register transfer language– A symbolic language

– A convenient tool for describing the internal organization of digital computers

– Can also be used to facilitate the design process of digital systems.

7

DESIGNATION OF REGISTERS

• Registers are designated by capital letters, sometimes followed by numbers (e.g., A, R13, IR)

• Often the names indicate function:– MAR - memory address register

– PC - program counter

– IR - instruction register

• Registers and their contents can be viewed and represented in various ways

– A register can be viewed as a single entity:

– Registers may also be represented showing the bits of data they contain

MAR

8

DESIGNATION OF REGISTERS[1]

R1 Register

Numbering of bits

Showing individual bits

SubfieldsPC(H) PC(L)

15 8 7 0

- a register - portion of a register - a bit of a register

• Common ways of drawing the block diagram of a register

7 6 5 4 3 2 1 0

R215 0

• Designation of a register

9

REGISTER TRANSFER

• Copying the contents of one register to another is a register transfer

• A register transfer is indicated as

R2 R1

– In this case the contents of register R1 are copied (loaded) into register R2

– A simultaneous transfer of all bits from the source R1 to the destination register R2, during one clock pulse

– Note that this is a non-destructive; i.e. the contents of R1 are not altered by copying (loading) them to R2

10

REGISTER TRANSFER

• A register transfer such as

R3 R5

Implies that the digital system has

– the data lines from the source register (R5) to the destination register (R3)

– Parallel load in the destination register (R3)

– Control lines to perform the action

11

CONTROL FUNCTIONS[2]

• Often actions need to only occur if a certain condition is true

• This is similar to an “if” statement in a programming language

• In digital systems, this is often done via a control signal, called a control function

– If the signal is 1, the action takes place• This is represented as:

P: R2 R1

Which means “if P = 1, then load the contents of register R1 into register R2”, i.e., if (P = 1) then (R2 R1)

12

HARDWARE IMPLEMENTATION OF CONTROLLED TRANSFERS

Implementation of controlled transfer

P: R2 R1

Block diagram

Timing diagram

Clock

Transfer occurs here

R2

R1

Control Circuit

LoadP

n

Clock

Load

t t+1

• The same clock controls the circuits that generate the control function and the destination register• Registers are assumed to use positive-edge-triggered flip-flops

13

SIMULTANEOUS OPERATIONS

• If two or more operations are to occur simultaneously, they are separated with commas

P: R3 R5, MAR IR

• Here, if the control function P = 1, load the contents of R5 into R3, and at the same time (clock), load the contents of register IR into register MAR

14

BASIC SYMBOLS FOR REGISTER TRANSFERS[2]

Capital letters Denotes a register MAR, R2

& numerals

Parentheses () Denotes a part of a register R2(0-7), R2(L)

Arrow Denotes transfer of information R2 R1

Colon : Denotes termination of control function P:

Comma , Separates two micro-operations A B, B A

Symbols Description Examples

15

CONNECTING REGISTRS

• In a digital system with many registers, it is impractical to have data and control lines to directly allow each register to be loaded with the contents of every possible other registers

• To completely connect n registers n(n-1) lines

• O(n2) cost– This is not a realistic approach to use in a large digital system

• Instead, take a different approach

• Have one centralized set of circuits for data transfer – the bus

• Have control circuits to select which register is the source, and which is the destination

16

Micro-Operations[2]

A micro-operation is an elementary operation, performed during one clock pulse, on the information stored in one or more registers.R1 ← R1 + R2

17

Register 1 Register 2

Binary Adder

LD1

CLK

R1

R2

2

3

Adder 5

LD1

CLK

R1

R2

2

3

Adder 5

LD1

5

8

Adder

Computer Organization

The organization of a digital computer is best defined by specifying:– The set of registers it contains and their function– The sequence of micro-operations performed on

the binary information stored in the registers– The control functions that initiate the sequence

of micro-operations

18

Register Designation[2]

• Whole register

• Portion of a register

• One bit in a register

19 /

R1

Register

7 6 5 4 3 2 1 0

Individual Bits

R1

Bit Numbering

7 0

Register Fields

DataAddress

Parallel Register Transfer[2]

• Unconditional

R1 ← R2

• Conditional

P: R1 ← R2

• Simultaneous

R1 ← R2 , R3 ← R2

20 /

Register 1

Register 2

ControlLogic

LoadP

CLK

LD1

R1 2 5

Basic Symbols for Reg. Transfer[2]

21 /

Symbol Description Examples

Capital Letters & Numerals

Denotes a register A , MBR , R3

Subscript Denotes a bit of a register A2 , B i

Parenthesis ( ) Denotes a portion of a register I(1– 5) , MBR(AD)

Arrow ← Denotes transfer of information A ← B

Colon : Denotes termination of control function P:

Comma , Separates two micro-operations A ← B , B ← A

Serial Register Transfer

S: A i ← A i – 1 , A 0 ← 0 i = 1, 2, 3

22 /

3 2 1 0A

0

Bus Transfer[2]

23 /

Register A Register B Register C Register D

4

Register R3 Register R2 Register R1 Register R0

4

Bus Transfer

24 /


4

4 4 4 4


4

Bus Transfer

25 /

Register A

A3 A2 A1 A0 B3 B2 B1 B0

Register B

C3 C2 C1 C0

Register C

D3 D2 D1 D0

Register D

S3 S2 S1 S0

Bus Transfer

26 /


MUX

4

4 4 4 4


4

Bus Transfer

27 /

Register A

A3 A2 A1 A0 B3 B2 B1 B0

Register B

C3 C2 C1 C0

Register C

D3 D2 D1 D0

Register D

B3 C3 D3 B2 C2 D2 B1 C1 D1 B0 C0 D0

MUXS1

S0

0 1 2 3

Y

MUXS1

S0

0 1 2 3

Y

MUXS1

S0

0 1 2 3

Y

MUXS1

S0

0 1 2 3

Y

4 - bit Bus

x

y

Bus Transfer

28 /

Register R3 Register R2 Register R1 Register R0

4

2 x 4Decoder

I1

I0

Y3 Y2 Y1 Y0z

wEnableE

Ld Ld Ld Ld

Memory Transfer

MBR ← MM ← MBR

29 /

MARMemory

Unit

Address

MBR

Read

Write

Memory Transfer[2]

MBR ← MMBR ← M [ R1 ]

30 /

MUXMemory

Unit

Address

MBR

Read

Write

Select

R1

R2

Micro-Operation Summary

31 /

Symbolic Description

A ← B Transfer content of register B into register A

MAR ← MBR(AD) Transfer content of AD portion of register MBR into MAR

A ← Constant Transfer binary (code) constant into register A

ABUS ← R1

R2 ← ABUS

Transfer content of R1 into bus A and at the same time transfer content of bus A into R2

MAR Memory address register: holds the address of the memory unit

MBRMemory buffer register: holds the data transferred in or out of the memory

M [ R ]Denotes the memory word specified by the address presently available in register R

MDenotes the memory word specified by the address in an implied register MAR

MBR ← M Memory read operation

M ← MBR Memory write operation

Micro-Operation Types

• Data Transfer

• Arithmetic Operations

• Logic Operations

• Shift Operations

32 /

Micro-Operation Types[2]

• Data Transfer

• Arithmetic OperationsS = A + B



33 /

FA FA FA FA

A3B3

A2B2

A1B1

A0B0

S3 S2 S1 S0C4

C0 Binary Adder

A3B3

A2B2

A1B1

A0B0

C0

S3 S2 S1 S0C4

Addition

S = A + B

34 /

FA FA FA FA

A3B3

A2B2

A1B1

A0B0

S3 S2 S1 S0C4

C0

Time (Propagation) delay = ?Time (Propagation) delay = ?

A0B0

CiCy

S

Addition

S = A + B

t = 0

35 /

FA FA FA FA

A3B3

A2B2

A1B1

A0B0

S3 S2 S1 S0C4

C0


A0B0

CiCy

S

Addition

S = A + B

t =

36 /

FA FA FA FA

A3

B3

A2

B2

A1

B1

A0

B0

S3 S2 S1 S0C4

C0


A0B0

CiCy

S

Addition

S = A + B

t = 2

37 /

FA FA FA FA

A3

B3

A2

B2

A1

B1

A0

B0

S3 S2 S1 S0C4

C0


A0B0

CiCy

S

Addition

S = A + B

t = 3

38 /

FA FA FA FA

A3

B3

A2

B2

A1

B1

A0

B0

S3 S2 S1 S0C4

C0


A0B0

CiCy

S

Addition

S = A + B

t = 4

39 /

FA FA FA FA

A3B3

A2B2

A1B1

A0B0

S3 S2 S1 S0C4

C0

Time (Propagation) delay = 4 Time (Propagation) delay = 4

A0B0

CiCy

S

Addition

EA ← A + B

40 /

Binary Adder C0

Load

A BE

Cy

FlagFlag

Subtraction

A ← A – B _A ← A + ( B + 1 )

41 /

BB

0

BB

1

FA FA FA FA

A3B3

A2B2

A1B1

A0B0

S3 S2 S1 S0C4

M

Increment

A ← A + 1

42 /

FA FA FA FA

A3

0

A2

0

A1

0

A0

0

S3 S2 S1 S0C4

1

Decrement

A ← A – 1

43 /

FA FA FA FA

A3

1

A2

1

A1

1

A0

1

S3 S2 S1 S0C4

0

Arithmetic

44 /

A3 A2 A1 A0

S3 S2 S1 S0C4

B3 B2 B1 B0

FA

0

MUX0 1 2 3

S1

S0Y

1

FA

0

MUX0 1 2 3

S1

S0Y

1

FA

0

MUX0 1 2 3

S1

S0Y

1

FA

0

MUX0 1 2 3

S1

S0Y

1 C2 C1 C0

Arithmetic

45 /

C2 C1 C0 Function

0 0 0 Y = A + B

0 0 1 Y = A + B + 1

0 1 0 Y = A + B

0 1 1 Y = A – B

1 0 0 Y = A

1 0 1 Y = A + 1

1 1 0 Y = A – 1

1 1 1 Y = A

A3 A2 A1 A0

Y3 Y2 Y1 Y0C4

B3 B2 B1 B0

FA

0

MUX0 1 2 3

S1S0Y

1

FA

0

MUX0 1 2 3

S1S0Y

1

FA

0

MUX0 1 2 3

S1S0Y

1

FA

0

MUX0 1 2 3

S1S0Y

1 C2 C1 C0

Arithmetic

46 /

C2 C1 C0 Function

0 0 0 S = A + B

0 0 1 S = A + B + 1

0 1 0 S = A + B

0 1 1 S = A – B

1 0 0 S = A

1 0 1 S = A + 1

1 1 0 S = A – 1

1 1 1 S = A

Arithmetic Unit

A B44

4

S

C2C1C0

Micro-Operation Types[3]

• Data Transfer




47 /

AND: S = A Λ B

OR: S = A V B

XOR: S = A B

AND: S = A • B

OR: S = A + B

XOR: S = A B

Logic

48 /

MUX

0 1 2 3

S1

S0Y

Ai Bi

Fi

C1 C0

Logic

49 /

C1 C0

MUX

0 1 2 3

S1

S0Y

A0 B0

F0

MUX

0 1 2 3

S1

S0Y

A1 B1

F1

MUX

0 1 2 3

S1

S0Y

A2 B2

F2

MUX

0 1 2 3

S1

S0Y

A3 B3

F3

Logic

50 /

C1 C0 Function

0 0 Y = A Λ B

0 1 Y =A V B

1 0 Y = A B

1 1 Y = A

C1 C0

MUX

0 1 2 3

S1

S0Y

A0 B0

F0

MUX

0 1 2 3

S1

S0Y

A1 B1

F1

MUX

0 1 2 3

S1

S0Y

A2 B2

F2

MUX

0 1 2 3

S1

S0Y

A3 B3

F3

Logic

51 /

C1 C0 Function

0 0 F = A Λ B

0 1 F = A V B

1 0 F = A B

1 1 F = A

Logic Unit

A B44

4

F

C1C0

Micro-Operation Types[4]• Data Transfer



• Shift Operations– Logical Shift shl A

shr A

– Arithmetic Shift ashl A

ashr A

– Circular Shift cil A

cir A

52 /

A7 A0 0

A7 A00

A7 A6 A0 0

A7 A6 A0

A7 A0

Logical & Arithmetic Shift

53 /

C1 C0 Function

0 0 F = A

0 1 F = shr A

1 0 F = shl A

1 1 F = ashr A

F3

C1C0

A3 A2 A0A1

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

0A3

F2 F1 F0

0A3

A2 A1


54 /

C1 C0 Function

0 0 F = A

0 1 F = shr A

1 0 F = shl A

1 1 F = ashr A

F3

00

A3 A2 A0A1

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

0A3

F2 F1 F0

0A3

A2 A1


55 /

C1 C0 Function

0 0 F = A

0 1 F = shr A

1 0 F = shl A

1 1 F = ashr A

F3

01

A3 A2 A0A1

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

0A3

F2 F1 F0

0A3

A2 A1


56 /

C1 C0 Function

0 0 F = A

0 1 F = shr A

1 0 F = shl A

1 1 F = ashr A

F3

10

A3 A2 A0A1

MUX

0 1 2 3

S1

S0Y

MUX

0 1 2 3

S1

S0Y

MUX

0 1 2 3

S1

S0Y

MUX

0 1 2 3

S1

S0Y

0A3

F2 F1 F0

0A3

A2 A1


57 /

C1 C0 Function

0 0 F = A

0 1 F = shr A

1 0 F = shl A

1 1 F = ashr A

F3

11

A3 A2 A0A1

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

MUX

0 1 2 3

S1S0Y

0A3

F2 F1 F0

0A3

A2 A1

Logical, Arithmetic, & Circular Shift

58 /

F3

C2

C1

C0

A3 A2 A0A1

MUX

0 1 2 3

S1

S0Y

MUX

0 1 2 3

S1

S0Y

MUX

0 1 2 3

S1

S0Y

MUX

0 1 2 3

S1

S0Y

A3

F2 F1 F0

A3

A2 A1

A3A0

C2 Shift

0 Regular

1 Circular

Logical, Arithmetic, & Circular Shift

59 /

Shifter

A4

C2C1C0

4

F

C2 C1 C0 Function

x 0 0 F = A

0 0 1 F = shr A

0 1 0 F = shl A

0 1 1 F = ashr A

1 0 1 F = cir A

1 1 0 F = cil A

Arithmetic and Logic Unit (ALU)

60 /

Arithmetic Unit

A

4

4

C0C1C2

Logic Unit

B

4

4

Shifter

4

C4C5C6

4

Y

MUXS0 Y

0 1C3

References

1. Computer Organization and Architecture, Designing for performance by William Stallings, Prentice Hall of India.

2. Modern Computer Architecture, by Morris Mano, Prentice Hall of India.

3. Computer Architecture and Organization by John P. Hayes, McGraw Hill Publishing Company.

4. Computer Organization by V. Carl Hamacher, Zvonko G. Vranesic, Safwat G. Zaky, McGraw Hill Publishing Company.

Bca 2nd sem-u-2.1-overview of register transfer, micro operations and basic computer organization...

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