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Transcript of Basic test concepts
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Basic test concepts
J. M. Martins Ferreira
FEUP / DEEC - Rua Dr. Roberto Frias
4200-537 Porto - PORTUGAL
Tel. 351 225 081 748 / Fax: 351 225 081 443
([email protected] / http://www.fe.up.pt/~jmf)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Objectives
• To emphasise the importance of testing in the overall product development cycle
• To introduce the basic concepts in testing and test vector generation
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Outline
• Fault modeling and ss@ faults
• Controllability, observability and testability
• Test vector generation for combinational circuits
• Redundancy and undetectable faults
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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The importance of testing
• No testing, no manufacturing
• Cost of testing is very high, but the cost of defective testing strategies is even higher
• Available test standards
• A brief historical perspective
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Why fault models?
• Possible physical defects are too many and defect spectrum too wide
• Effective test strategies require that the complexity of malfunction models is reduced to an acceptable level
• Fault models are an abstract representation of defective circuit conditions (a fault is at logic level, a defect is at physical level)
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Attributes of a good fault model• Simplicity, to allow efficient test vector
generation procedures
• Defect coverage, to guarantee that the percentage of defective components escaping detection is acceptably low
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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The single stuck-at fault model• A structural fault model assuming that
– Only one node at a time is faulty– Only two types of faults: s@0 and s@1
• Experience has shown that the ss@ fault model has excellent characteristics concerning those attributes that were previously referred
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Controllability of a node
Y
X
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B
C
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A B C Contr. Y=1 A B C Contr. X=0
0 0 X - X X 0 -
0 1 X X X 1 1 0 X -
1 1 X -
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Problems due to low controllability• Low controllability leads to difficult test vector
generation, since:– Our first step to detect a given s@ fault in a node
consists of driving it to the opposite logic value (1 if s@0 or 0 if s@1)
– In an IC, the value at any node can only be controlled from the input pins (the primary inputs of the circuit)
• Low observability, as we shall see, has a similar effect
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Observability of a node
Y
X
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A B C Observ. of Y A B C Observ. of X
X X 0 - 0 0 X X X 1 0 1 X -
1 0 X 1 1 X
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Testability
• Testability is a combined measure of controllability and observability
• High testability facilitates test vector generation and leads to better test effectiveness
• So, why aren’t all circuits highly testable?
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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The D-notation
• Introduced by Paul Roth in the mid-60s for the (test vector generation) D-algorithm
• D is a composite logic value that results from driving a s@0 node to 1 (and /D its dual)
Condition at the node D- notation Description
0/0 0 Fault-free node at 0
0/1 /D s@1 node which we are trying to drive to 0
1/0 D s@0 node which we are trying to drive to 1
1/1 1 Fault-free node at 1
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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The D-algorithm
• Drive the node to the opposite logic value (0 if s@1 and 1 if s@0)
• Propagate the error signal (D or /D) to a primary output
• Justify (backwards) the values that enable the propagation path, until a necessary combination at the primary inputs (a test vector) is found
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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A test generation exampleY s@0
U?A
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1 2
U?A
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U?A
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U?A
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B
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Y s@0
1/0
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U?A
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U?A
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B
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(a ) N o d e Y s @0 . (b ) F a u l t a c t i v a t i o n ( s t e p 1 ) .
Y s@0
1/0
11
0
1/0
U?A
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1 2
U?A
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B
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Y s@0
1/0
11
0
1/0
0
1
1
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B
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(c ) F a u l t p r o p a g a t i o n (s t e p 2 ) . (d ) F a u l t j u s t i fi ca t i o n (s t e p 3 ) .
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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The case of undetectable faults
Y s@0U?A
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1 2
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B F
Y s@0
1/011
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B F
(a ) N o d e Y s @ 0 . (b ) O p p o s i t e v a l u e o f s @ 0 a p p l i e d i n n o d e Y .
Y s@0
1/0
0
11
U?A
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1 2
U?A
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1 2
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U?A
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B F
Y s@0
1/00
0
11
1
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1 2
U?A
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1 2
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B F
( c ) P r o p a g a t i o n ( t e n t a t i v e ) . (d ) J u s t i fi ca t i o n (n o t p o s s i b l e ) .
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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BacktrackingY s@0
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B F
Y s@0
1/0
0
1
1
0
0U?A
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1 2
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1
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U?A
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2
3A
B F
(a ) N o d e Y s @0 . (b ) F i r s t t e n t a t i v e (n o t p o s s i b l e ) .
Y s@0
1/0
0
1
0
1/0
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B F
Y s@0
1/0
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1
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1/0
1
1
1
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1 2
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2
3A
B F
(c ) A l t e r n a t i v e ch o i ce . (d ) P r o p a g a t i o n a n d j u s t i fi ca t i o n .
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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Redundancy and undetectable faults• Redundant product terms degrade
testability for the same reason that they may introduce fault tolerance features (ability to mask faults) A B C
F
X s@0
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108
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/A
A
0 1 3 2
4 5 7 6
/B B
1
C/C /C
F
1
11
Leonardo da Vinci ALLEGRO© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)
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But are those faults really undetectable?• Redundancy may be used to avoid glitches
(correct transient behaviour), which may be visible again if faults are present
A B C
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