basic of op-amp

ANALOG SIGNAL PROCESSING

1

Basic introduction

Copyright 2004 by Oxford University Press, Inc.Microelectronic Circuits - Fifth Edition Sedra/Smith 2

Figure 1.1 Two alternative representations of a signal source: (a) the Thévenin form, and (b) the Norton form.


Figure 1.2 An arbitrary voltage signal vs(t).


Figure 1.3 Sine-wave voltage signal of amplitude Va and frequency f = 1/T Hz. The angular frequency v = 2pf rad/s.


Figure 1.4 A symmetrical square-wave signal of amplitude V.


Figure 1.5 The frequency spectrum (also known as the line spectrum) of the periodic square wave of Fig. 1.4.


Figure 1.6 The frequency spectrum of an arbitrary waveform such as that in Fig. 1.2.


Figure 1.7 Sampling the continuous-time analog signal in (a) results in the discrete-time signal in (b).


Figure 1.8 Variation of a particular binary digital signal with time.


Figure 1.9 Block-diagram representation of the analog-to-digital converter (ADC).


Figure 1.10 (a) Circuit symbol for amplifier. (b) An amplifier with a common terminal (ground) between the input and output ports.


Figure 1.11 (a) A voltage amplifier fed with a signal vI(t) and connected to a load resistance RL. (b) Transfer characteristic of a linear voltage amplifier with voltage gain Av.


Figure 1.12 An amplifier that requires two dc supplies (shown as batteries) for operation.


Figure 1.13 An amplifier transfer characteristic that is linear except for output saturation.


Figure 1.14 (a) An amplifier transfer characteristic that shows considerable nonlinearity. (b) To obtain linear operation the amplifier is biased as shown, and the signal amplitude is kept small. Observe that this amplifier is operated from a single power supply, VDD.


Figure 1.15 A sketch of the transfer characteristic of the amplifier of Example 1.2. Note that this amplifier is inverting (i.e., with a gain that is negative).


Figure 1.16 Symbol convention employed throughout the book.


Figure 1.17 (a) Circuit model for the voltage amplifier. (b) The voltage amplifier with input signal source and load.


Figure 1.18 Three-stage amplifier for Example 1.3.


Figure 1.19 (a) Small-signal circuit model for a bipolar junction transistor (BJT). (b) The BJT connected as an amplifier with the emitter as a common terminal between input and output (called a common-emitter amplifier). (c) An alternative small-signal circuit model for the BJT.


Figure E1.20


Figure 1.20 Measuring the frequency response of a linear amplifier. At the test frequency v, the amplifier gain is characterized by its magnitude (Vo/Vi) and phase f.


Figure 1.21 Typical magnitude response of an amplifier. |T(v)| is the magnitude of the amplifier transfer function—that is, the ratio of the output Vo(v) to the input Vi(v).


Figure 1.22 Two examples of STC networks: (a) a low-pass network and (b) a high-pass network.


Figure 1.23 (a) Magnitude and (b) phase response of STC networks of the low-pass type.


Figure 1.24 (a) Magnitude and (b) phase response of STC networks of the high-pass type.


Figure 1.25 Circuit for Example 1.5.


Figure 1.26 Frequency response for (a) a capacitively coupled amplifier, (b) a direct-coupled amplifier, and (c) a tuned or bandpass amplifier.


Figure 1.27 Use of a capacitor to couple amplifier stages.


Figure E1.23


Figure 1.28 A logic inverter operating from a dc supply VDD.


Figure 1.29 Voltage transfer characteristic of an inverter. The VTC is approximated by three straightline segments. Note the four parameters of the VTC (VOH, VOL, VIL, and VIH) and their use in determining the noise margins (NMH and NML).


Figure 1.30 The VTC of an ideal inverter.


Figure 1.31 (a) The simplest implementation of a logic inverter using a voltage-controlled switch; (b) equivalent circuit when vI is low; and (c) equivalent circuit when vI is high. Note that the switch is assumed to close when vI is high.


Figure 1.32 A more elaborate implementation of the logic inverter utilizing two complementary switches. This is the basis of the CMOS inverter studied in Section 4.10.


Figure 1.33 Another inverter implementation utilizing a double-throw switch to steer the constant current IEE to RC1 (when vI is high) or RC2 (when vI is low). This is the basis of the emitter-coupled logic (ECL) studied in Chapters 7 and 11.


Figure 1.34 Example 1.6: (a) The inverter circuit after the switch opens (i.e., for t 0). (b) Waveforms of vI and vO. Observe that the switch is assumed to operate instantaneously. vO rises exponentially, starting at VOL and heading toward VOH .


Figure 1.35 Definitions of propagation delays and transition times of the logic inverter.


Figure P1.6


Figure P1.10


Figure P1.14


Figure P1.15


Figure P1.16


Figure P1.17


Figure P1.18


Figure P1.37


Figure P1.58


Figure P1.63


Figure P1.65


Figure P1.67


Figure P1.68


Figure P1.72


Figure P1.77


Figure P1.79

Copyright 2004 by Oxford University Press, Inc.

Operational Amplifiers

55


Figure 2.1 Circuit symbol for the op amp.


Figure 2.2 The op amp shown connected to dc power supplies.


Figure 2.3 Equivalent circuit of the ideal op amp.


Figure 2.4 Representation of the signal sources v1 and v2 in terms of their differential and common-mode components.


Figure E2.3


Figure 2.5 The inverting closed-loop configuration.


Figure 2.6 Analysis of the inverting configuration. The circled numbers indicate the order of the analysis steps.


Figure 2.7 Analysis of the inverting configuration taking into account the finite open-loop gain of the op amp.


Figure 2.8 Circuit for Example 2.2. The circled numbers indicate the sequence of the steps in the analysis.


Figure 2.9 A current amplifier based on the circuit of Fig. 2.8. The amplifier delivers its output current to R4. It has a current gain of (1 + R2/R3), a zero input resistance, and an infinite output resistance. The load (R4), however, must be floating (i.e., neither of its two terminals can be connected to ground).


Figure E2.5


Figure E2.6


Figure 2.10 A weighted summer.


Figure 2.11 A weighted summer capable of implementing summing coefficients of both signs.


Figure 2.12 The noninverting configuration.


Figure 2.13 Analysis of the noninverting circuit. The sequence of the steps in the analysis is indicated by the circled numbers.


Figure 2.14 (a) The unity-gain buffer or follower amplifier. (b) Its equivalent circuit model.


Figure E2.9


Figure E2.13


Figure 2.15 Representing the input signals to a differential amplifier in terms of their differential and common-mode components.


Figure 2.16 A difference amplifier.


Figure 2.17 Application of superposition to the analysis of the circuit of Fig. 2.16.


Figure 2.18 Analysis of the difference amplifier to determine its common-mode gain Acm ; vO / vIcm.


Figure 2.19 Finding the input resistance of the difference amplifier for the case R3 = R1 and R4 = R2.


Figure 2.20 A popular circuit for an instrumentation amplifier: (a) Initial approach to the circuit; (b) The circuit in (a) with the connection between node X and ground removed and the two resistors R1 and R1 lumped together. This simple wiring change dramatically improves performance; (c) Analysis of the circuit in‘ (b) assuming ideal op amps.


Figure 2.21 To make the gain of the circuit in Fig. 2.20(b) variable, 2R1 is implemented as the series combination of a fixed resistor R1f and a variable resistor R1v. Resistor R1f ensures that the maximum available gain is limited.


Figure 2.22 Open-loop gain of a typical general-purpose internally compensated op amp.


Figure 2.23 Frequency response of an amplifier with a nominal gain of +10 V/V.


Figure 2.24 Frequency response of an amplifier with a nominal gain of –10 V/V.


Figure 2.25 (a) A noninverting amplifier with a nominal gain of 10 V/V designed using an op amp that saturates at ±13-V output voltage and has ±20-mA output current limits. (b) When the input sine wave has a peak of 1.5 V, the output is

clipped off at ±13 V.


Figure 2.26 (a) Unity-gain follower. (b) Input step waveform. (c) Linearly rising output waveform obtained when the amplifier is slew-rate limited. (d) Exponentially rising output waveform obtained when V is sufficiently small so that the initial slope (vtV) is smaller than or equal to SR.


Figure 2.27 Effect of slew-rate limiting on output sinusoidal waveforms.


Figure 2.28 Circuit model for an op amp with input offset voltage VOS.


Figure E2.23 Transfer characteristic of an op amp with VOS = 5 mV.


Figure 2.29 Evaluating the output dc offset voltage due to VOS in a closed-loop amplifier.


Figure 2.30 The output dc offset voltage of an op amp can be trimmed to zero by connecting a potentiometer to the two offset-nulling terminals. The wiper of the potentiometer is connected to the negative supply of the op amp.


Figure 2.31 (a) A capacitively coupled inverting amplifier, and (b) the equivalent circuit for determining its dc output offset voltage VO.


Figure 2.32 The op-amp input bias currents represented by two current sources IB1 and IB2.


Figure 2.33 Analysis of the closed-loop amplifier, taking into account the input bias currents.


Figure 2.34 Reducing the effect of the input bias currents by introducing a resistor R3.


Figure 2.35 In an ac-coupled amplifier the dc resistance seen by the inverting terminal is R2; hence R3 is chosen equal to R2.


Figure 2.36 Illustrating the need for a continuous dc path for each of the op-amp input terminals. Specifically, note that the amplifier will not work without resistor R3.


Figure 2.37 The inverting configuration with general impedances in the feedback and the feed-in paths.


Figure 2.38 Circuit for Example 2.6.


Figure 2.39 (a) The Miller or inverting integrator. (b) Frequency response of the integrator.


Figure 2.40 Determining the effect of the op-amp input offset voltage VOS on the Miller integrator circuit. Note that since the output rises with time, the op amp eventually saturates.


Figure 2.41 Effect of the op-amp input bias and offset currents on the performance of the Miller integrator circuit.


Figure 2.42 The Miller integrator with a large resistance RF connected in parallel with C in order to provide negative feedback and hence finite gain at dc.


Figure 2.43 Waveforms for Example 2.7: (a) Input pulse. (b) Output linear ramp of ideal integrator with time constant of 0.1 ms. (c) Output exponential ramp with resistor RF connected across integrator capacitor.


Figure 2.44 (a) A differentiator. (b) Frequency response of a differentiator with a time-constant CR.


Figure 2.45 A linear macromodel used to model the finite gain and bandwidth of an internally compensated op amp.


Figure 2.46 A comprehensive linear macromodel of an internally compensated op amp.


Figure 2.47 Frequency response of the closed-loop amplifier in Example 2.8.


Figure 2.48 Step response of the closed-loop amplifier in Example 2.8.


Figure 2.49 Simulating the frequency response of the µA741 op-amp in Example 2.9.


Figure 2.50 Frequency response of the µA741 op amp in Example 2.9.


Figure 2.51 Circuit for determining the slew rate of the µA741 op amp in Example 2.9.


Figure 2.52 Square-wave response of the µA741 op amp connected in the unity-gain configuration shown in Fig. 2.51.


Figure P2.2


Figure P2.8


Figure P2.16


Figure P2.22


Figure P2.25


Figure P2.30


Figure P2.31


Figure P2.32


Figure P2.33


Figure P2.34


Figure P2.35


Figure P2.43


Figure P2.46


Figure P2.47


Figure P2.49


Figure P2.50


Figure P2.51


Figure P2.59


Figure P2.62


Figure P2.68


Figure P2.69


Figure P2.70


Figure P2.71


Figure P2.77


Figure P2.78


Figure P2.108


Figure P2.117


Figure P2.118


Figure P2.119


Figure P2.122


Figure P2.125


Figure P2.126


Table 1.1 The Four Amplifier Types

basic of op-amp

Documents

Transcript of basic of op-amp