Basic Computer Organization and Design · Basic Computer Organization and Design. The Basic...

1997 John D. Carpinelli, All Rights Reserved 1

Basic ComputerOrganization and Design

The Basic Computer was designed by M. Morris Mano specifically as an instructional aid forthe textbook used in this course. It is not meant to compete with CPUs currently used. Rather,it is designed to illustrate the various aspects of CPU design. This module begins withdefinitions and a review of the basic organization of a computer and of a CPU. We alsospecify the internal components of the CPU, i.e. the registers and data paths.

We next describe the instruction formats and instructions for this CPU. The Basic Computerhas three different formats for its instructions; each of the 25 instructions follows only one ofthese three formats. We will review these formats and the overall function of each instruction.

Next we look at the control signals used in this design. These signals are used to triggermicro-operations and coordinate data manipulation within the computer. We also show thehardware to generate these signals.

We then get to the heart of the design: the machine cycles which fetch, decode and executethese instructions. By using the control signals to enable micro-operations properly, the CPUrealizes its instruction set. We first look at the fetch and indirect cycles. Then we review theindividual execute cycles.

We next look at input/output operations and interrupts. The Basic Computer has one inputport and output port, so we don’t have to worry about port addressing in our design. Inputsand outputs are used to trigger interrupts in this computer. We examine the I/O hardware andthe interrupt cycle code.

We then present an example of the hardware design for one of the internal components tofurther illustrate the design process. Finally, concluding remarks are presented.


Outline

u Basic Computer specification andorganization

u Instruction formats and instructionsu Control Signalsu Machine Cyclesu Interruptsu Example hardware design

The instruction code is an opcode plus additional information, such as amemory address. It is not the micro-operations. In terms of programming, itis closest to a single assembly language instruction.


Definition

u Instruction code: a group of bits that tellthe computer to perform a specificoperation

The CPU coordinates data transfers between itself and memory or I/O devices.The paths shown here not only carry data, but also the control signals whichcause data to be transferred. They also carry address information which isused to select the correct memory location or I/O port address.


Computer organization

CPU

I/OMEM

The control unit issues signals to coordinate functions of the ALU, theregisters and external hardware. By issuing these signals in the proper order,they cause a sequence of operations to occur. By performing this sequence, aninstruction is fetched, decoded and executed.


CPU organization

Regs

Control

ALU

Since memory is 4K in size, it requires 12 address bits. Each word of memory contains 16 bitsof data.

The address register (AR) is 12 bits wide, since this system requires that many bits in order toaccess memory. Similarly, the program counter (PC) is also 12 bits wide.

Each data word is 16 bits wide. The Data Register (DR) must also be 16 bits wide, since itreceives data from and sends data to memory. The accumulator (AC) acts on 16 bits of data.The Instruction Register (IR) receives instruction codes from memory which are 16 bits wide.

Of note: TR is a temporary register. Only the CPU can cause it to be accessed. Theprogrammer cannot directly manipulate the contents of TR. Most CPU’s have one or moretemporary registers which it uses to perform instructions.

The input and output registers (INPR and OUTR) are 8 bits wide each. For this CPU, I/Oinstructions only transfer 8 bits of data at a time.

The 3-bit sequence counter (SC) is used to generate the correct timing (T) states.

Other 1-bit registers are the carry out (E), the indirect register (I), the interrupt enable (IEN)and the input and output flags (FGI and FGO).


Basic Computer specification

u 4K x 16 RAMu 12-bit AR, PCu 16-bit DR, AC, IR, TRu 8-bit INPR, OUTRu 3-bit SCu 1-bit E, I, IEN, FGI, FGO

This is the internal design of the CPU for the Basic Computer. The CPU is designed around an internalcommon bus with a common clock. Each register can place its data onto the bus, and has internal tri-statebuffers on the outputs. The control unit must make sure that at most one register (or memory unit) placesdata onto the bus at one time.

The memory unit is external to the CPU. It always receives its address from the address register (AR)and makes its data available to the CPU bus. It receives data from the CPU bus as well. Read and writesignals are supplied by the control unit.

The address registers, program counter (PC) and data register (DR) each load data onto and receive datafrom the system bus. Each has a load, increment and clear signal derived from the control unit. Thesesignals are sychronous; each register combines these signals with the system clock to activate the properfunction. Since AR and PC are only 12-bits each, they use the low order 12 bits of the bus.

The accumulator makes its data available on the bus but does not receive data from the bus. Instead, itreceives data solely from an ALU, labeled “Adder and Logic” in the diagram. To load data into AC,place it onto the bus via DR and pass it directly through the ALU. The synchronous load, increment andclear signals act as in the previous registers. Note that E, the 1-bit carry flag, also receives its data fromthe ALU.

The input register, INPR, receives data from an external input port, not shown here, and makes its dataavailable only to AC. The output register makes its data available to the output port via hardware notshown here. We will examine these two components in more detail later in this module.

The instruction register, IR, can only be loaded; it cannot be incremented nor cleared. Its output is usedto generate Di and Ti. We will look at that hardware later in this module.

TR is a temporary register. The CPU uses this register to store intermediate results of operations. It isnot accessible by the external programs. It is loaded, incremented and cleared like the other registers.


Basic Computer architecture

See figure 5.4, p. 130 of the textbook.

As their name implies, memory reference instructions are those that referencememory. Some read data from memory, others write data to memory, and oneinstruction does both. For these instructions, the most significant bit is theindirect bit. If this bit is 1, the instruction must use indirect memoryaddressing. That is, the address given is not the address of the operand. It isthe address of a memory location which contains the address of the operand.

The next three bits are the OPR field, or operation field. These three bits maytake on any value except for 111; that is reserved for other instructions. TheOPR field tells the CPU which instruction is to be performed.

Finally, the 12 low order bits contain the memory address to be used by thisinstruction (or in the case of indirection the address of a memory locationwhich contains the address to be used by this instruction).


Instruction formats

Memory-reference instructions:

15

I

14-12

OPR ADDRESS

11-0

Register reference instructions are those which access data and manipulate thecontents of registers. They do not access memory. These instructions areexecuted in one clock cycle.

Note that the 12 low-order bits serve a different function depending on theinstruction format used.


Instruction formats

Register-reference instructions:

0 1 1 1

15-12

REGISTER OP

11-0

This class of instructions accesses I/O devices. The instructions in this classalso enable and disable interrupts. Since this computer only allows for a singleinput device and a single output device, no address information is needed.


Instruction formats

I/O instructions:

1 1 1 1

15-12

I/O OPERATION

11-0

The AND instruction performs a bit-wise logical AND.

The ADD instruction performs a regular addition.

The LDA and STA are regular load and store instructions.

The BUN (branch unconditional) is a jump instruction.

The BSA is used to call subroutines in the Basic Computer.

The ISZ instruction is used for program loops. Note the semicolon in thisinstruction. It means that the first part is performed, then the second part isperformed in the following clock cycle.

Later in this module, we will examine exactly how each of these instructions isimplemented on the Basic Computer.


Memory-reference instructionsu AND: AC ←← AC^M[ADDR]u ADD: AC ←← AC+M[ADDR]u LDA: AC ←← M[ADDR]u STA: M[ADDR] ←← ACu BUN: PC ←← ADDRu BSA: PC ←← ADDR+1, M[ADDR] ←← PC+1u ISZ: M[ADDR] ←← M[ADDR]+1;

IF (M[ADDR]=0) THEN PC ←← PC+1

Each register reference instruction is performed in a single clock cycle. Eachinstruction manipulates the contents of a register within the CPU, so therelatively time consuming accesses to memory are avoided. There are 12register reference instructions overall, each of which is encoded by one of the12 low order bits of the instruction code.


Register-reference instructions

u CLA: AC ← ← 0u CLE: E ← ← 0u CMA: AC ← ← ACu CME: E ← ← Eu CIR: EAC ←← cir(EAC)u CIL: EAC ← ← cil(EAC)

These are the other six register reference instructions.


Register-reference instructions

u INC: EAC ← ← AC+1u SPA: IF AC(15)=0 THEN PC ← ← PC+1u SNA: IF AC(15)=1 THEN PC ← ← PC+1u SZA: IF AC=0 THEN PC ← ← PC+1u SZE: IF E=0 THEN PC ← ← PC+1u HLT: HALT

The input/output instructions, like the register reference instructions, areperformed in a single clock cycle. Note that there are no instructions to setFGI or FGO to 1. These flags are set by external hardware when input data isready or output data is requested. When the CPU performs the proper input oroutput instruction (INP or OUT), it resets the flag to allow for future I/O datatransfers.


I/O instructions

u INP: AC(7-0) ← ← INPR, FGI ←← 0u OUT: OUTR ←← AC(7-0) , FGO ←← 0u SKI: IF FGI=1 THEN PC ←← PC+1u SKO: IF FGO=1 THEN PC ←← PC+1u ION: IEN ←← 1u IOF: IEN ←← 0

The T signals occur in sequence and are never skipped over. The only twooptions during a T-state are to proceed to the next T-state or to return to T-state 0.

The D signals decode the instruction and are used to select the correct executeroutine.

I is used to select the indirect routine and also to select the correct executeroutine for non-memory reference instructions.

R is used for interrupt processing and will be explained later.


Control signals

u T0, T1, ... T6 : Timing signalsu D0, D1, ... D7 : Decoded instructionu I: Indirect bitu R: Interrupt cycle bit

This circuit generates the T signals. The sequence counter, SC, is incrementedonce per clock cycle. Its outputs are fed into a 3-8 decoder which generatesthe T signals. Whenever a micro-operation sets SC to zero, it resets thecounter, causing T0 to be activated during the next clock cycle.


Control signals

SC

CLRUP

CLK

SC←←0

DECODER

0123456

T0

T1

T2

T3

T4

T5

T6

The D signals are generated similarly to the T signals. Here the source isIR(14-12) instead of SC. Also note that IR won’t change during theinstruction execution.


Control signals

IR(14-12)

DECODER

01234567

D0

D1

D2

D3

D4

D5

D6

D7

The fetch cycle proceeds as follows. During the first T state, T0, the contentsof the program counter are copied to the address register. This makes theaddress available to the memory unit, which does its internal decoding andfetches the data. In T1, this data is read from memory into the instructionregister for use by the CPU. The program counter is incremented here also, sothat the next time we fetch an instruction, we do so from the next address inmemory. During T2, the D signals are generated. The values of the addressand the indirect bit are stored in AR and I, respectively.

The last statement only occurs when D7 is low and I is high. This is theindirect cycle; it only occurs for memory reference instructions (D7’) whichare indirect (I). When this is the case, the address specified in the instructionis not the actual address; it is the address of a memory location which containsthe actual address.

The fetch cycle will be modified slightly later to incorporate the ability tohandle interrupts.


Fetch and indirect cycles

T0: AR ←← PCT1: IR ←← M[AR], PC ←← PC+1T2: AR ←← IR(11-0), I ←← IR15,

D0, D1, ... D7 ←← Decode IR(14-12)D7’IT3 : AR ←← M[AR](11-0)

In this example, the instruction AND I 500 is fetched from memory location100. During T0, the address (100) is loaded into AR. The memory moduleperforms its internal decoding.

During the next cycle, T1, the instruction code is loaded into IR and theprogram counter is incremented.

In T2, the address portion of this instruction, 500, is loaded into AR. Theindirect register gets 1, the value of the indirect bit of the instruction. Sincebits 14-12 are 000, D0 is activated by the decoder. These tell us that we havean indirect AND instruction.

In T3, D7 is low and I is high, so the address portion of the instruction is not theaddress of the operand. Rather, it is the address of a memory location whichcontains the address of the actual operand. In this cycle, we go back tomemory to get the actual address, 234, which is loaded into AR. If this werenot an indirect instruction, I would be low and this micro-instruction would nothave been executed.


Fetch and indirect cycles

Example: Fetch from 100: AND I 500;M[500] = 234

T0: AR ←← 100T1: IR ←← 8500, PC ←← 101T2: AR ←← 500, I ←← 1, D0 ←← 1D7’IT3: AR ←← M[500](11-0) = 234

In this and all examples, all data is given in hex. Here, the instruction fetchcycle has fetched the AND instruction, determined that this execute routinemust be performed and loaded the address 500 into the AR.

In T4, the data is read from memory and loaded into the DR, 25 in this case.Next, in T5, it is logically ANDed with the current contents of the accumulator,31 here, and the result is stored back into the accumulator. Setting SC to zeroreturns to the fetch routine to access the next instruction.


AND execute cycle

AND:D0T4: DR ←← M[AR]D0T5: AC ←← AC ^ DR, SC ←← 0

Example: AND 500: AC = 31, M[500] = 25D0T4: DR ←← 25D0T5: AC ←← 31 ^ 25 = 21, SC ←← 0

The ADD operation proceeds similarly to the AND operation. The onlydifference is that once the operand is loaded from memory it is arithmeticallyadded to the current contents of the accumulator.


ADD execute cycle

ADD:D1T4: DR ←← M[AR]D1T5: AC ←← AC + DR, SC ←← 0

Example: ADD 500: AC = 31, M[500] = 25D1T4: DR ←← 25D1T5: AC ←← 31 + 25 = 56, SC ←← 0

As in the previous instructions, the CPU reads the data from memory into DRduring T4. In the following cycle, this data is copied into the accumulator.Since the accumulator only receives data from the adder and logic section, thedata from DR is passed into this unit and then passed through it unchanged.


LDA execute cycle

LDA:D2T4: DR ←← M[AR]D2T5: AC ←← DR, SC ←← 0

Example: LDA 500: M[500] = 25D2T4: DR ←← 25D2T5: AC ←← 25, SC ←← 0

The STA instruction is much more straightforward than the LDA instruction.Since the address is already available from AR to the memory unit, we simplymove data directly from the accumulator to the memory unit in a single clockcycle.


STA execute cycle

STA: D3T4: M[AR] ←← AC, SC ←← 0

Example: STA 500: AC = 31, M[500] = 25D3T4: M[500] ←← 31, SC ←← 0

The BUN instruction implements a jump by loading the new address directlyfrom AR into the PC. Unlike many of the other memory referenceinstructions, BUN receives its data as part of the original instruction and doesnot require a secondary memory access.


BUN execute cycle

BUN:D4T4: PC ←← AR, SC ←← 0

Example: BUN 500D4T4: PC ←← 500, SC ←← 0

The BSA instruction implements a subroutine call. A BSA for address Xstores the return address at location X. Note that PC was incremented as partof the opcode fetch and thus contains the return address. Entering T4, ARcontains X. During T4, AR is incremented to X+1, since this is the start of theactual subroutine code. T5 loads the value X+1 into the program counter andreturns to the fetch routine.

Note that this computer cannot implement recursion. If a subroutine calleditself, it would overwrite the original return address and would be caught in thesubroutine forever!

We return from a subroutine by using a BUN I X instruction.


BSA execute cycle

BSA: D5T4: M[AR] ←← PC, AR ←← AR+1 D5T5: PC ←← AR, SC ←← 0

During T4, the return address, 101, is loaded into memory lcoation 200 and ARis set to 201. This value is the location of the first instruction of thesubroutine. During T5 it is loaded into the program counter. The computerwill next fetch the instruction at this location.


Subroutine call using BSA

Example: 100: BSA 200

D5T4: M[AR] ←← PC, AR ←← AR+1M[200] ←← 101, AR ←← 201

D5T5: PC ←← AR, SC ←← 0PC ←← 201, SC ←← 0

In this example we return from the previous subroutine. After executing a fewinstructions which comprise the subroutine, we reach the BUN I 200instruction. During the indirect cycle, we go to location 200 to get the actualaddress we want, in this case 101. During T4, we load this value into theprogram counter, affecting the jump.


Subroutine return using BUN I

Example: 205: BUN I 200M[200] = 101

D7I’T3: AR ←← M[AR](11-0)AR ←← M[200](11-0) = 101

D4T4: PC ←← AR, SC ←← 0PC ←← 101, SC ←← 0

The ISZ instruction is used for program loops. The negative of the count valueis stored in some memory location, say X. At the end of the loop, we place theinstruction ISZ X. During T4, the Basic Computer copies the contents ofmemory location X into the data register. This value is incremented during T5,and written back into memory during T6. (AR still contains the memoryaddress at this point.) Also during T6, this value, still available in DR, is checkto see if it is zero. If so, PC is incremented, in effect skipping the nextinstruction.


ISZ execute cycle

D6T4: DR ←← M[AR]D6T5: DR ←← DR+1D6T6: M[AR] ←← DR, SC ←← 0,

if (DR=0) then PC ←← PC+1

In this example, memory location 200 contains 55, which is loaded into thedata register during T4. It is incremented to 56 during T5 and stored back intomemory location 200. Since it is not zero, we do not increment the PC.


Loop control using ISZ

Example:100: ISZ 200 M[200] = 55

D6T4: DR ←← M[AR] (DR ←← 55)D6T5: DR ←← DR+1 (DR ←← 56)D6T6: M[AR] ←← DR, SC ←← 0,

if (DR=0) then PC ←← PC+1(M[200] ←← 56, SC ←← 0)

Here is an example of how to use the ISZ instruction in a program loop. Theloop starts at some location X and does its work. Then we perform the ISZinstruction, which increments the loop counter. If it is not zero, it does notskip the next instruction. It executes that instruction, which branches back tothe beginning of the loop. If it is zero, it skips the BUN X instruction, exitingthe loop.


Loops using ISZ

X: Start of loop . .ISZ 200BUN XContinue on...

There are 12 register reference instructions, each activated by one of the 12low order bits of the instruction register. Each register reference instruction isexecuted in a single clock cycle.

Of note is the first line, r: SC <-- 0. This means that SC <-- 0 whenever r=1,regardless of the values of IR(11-0). In short, this is equivalent to adding themicro-operation SC <-- 0 to each of these instructions individually.

The CLA and CLE instructions clear AC and E, respectively. CMA and CMEcomplement their respective registers. CIR and CIL perform circular right andleft shifts on the concatenated register pair E/AC.


Register-reference execute cycles

r = D7I’T3 r: SC ← ← 0

(CLA) rIR11: AC ← ← 0(CLE) rIR10: E ← ← 0(CMA) rIR9: AC ← ← AC(CME) rIR8: E ← ← E(CIR) rIR7: EAC ←← cir(EAC)(CIL) rIR6: EAC ← ← cil(EAC)

The INC instruction increments AC, storing the result in register pair E/AC.The next four instructions skip an instruction in the program if AC is positive(SPA), AC is negative (SNA), AC is zero (SZA) or E is zero (SZE). Note thatSPA actually skips an instruction if AC is not negative, since it also skips aninstruction if AC is zero. The HLT instruction shuts down the computer.


Register-reference execute cycles

r = D7I’T3 r: SC ← ← 0

(INC) rIR5: EAC ← ← AC+1(SPA) rIR4: IF AC(15)=0 THEN PC ← ← PC+1(SNA) rIR3: IF AC(15)=1 THEN PC ← ← PC+1(SZA) rIR2: IF AC=0 THEN PC ← ← PC+1(SZE) rIR1: IF E=0 THEN PC ← ← PC+1(HLT) rIR0: HALT

The Basic Computer has one 8-bit input port and one 8-bit output port. Eachport interface is modeled as an 8-bit register which can send data to or receivedata from AC(7-0). Whenever input data is to be made available, the externalinput port writes the data to INPR and sets FGI to 1. When the output portrequests data, it sets FGO to 1.

As will be shown shortly, the FGI and FGO flags are used to trigger interrupts(if interrupts are enabled by the IEN flag).


I/O configuration

u 8-bit input register INPRu 8-bit output register OUTRu 1-bit input flag FGIu 1-bit input flag FGOu 1-bit interrupt enable IEN

Once data is made available to the CPU, it can be read in using the INPinstruction. Note that this not only reads the data into the accumulator, butalso resets FGI to zero. This tells the input port that it may send more data. Ina similar manner, the OUT instruction writes data to OUTR and resets FGO tozero, notifying the output port that data is available.

The SKI and SKO instructions skip an instruction if there is a pending input oroutput request. This is useful in determining the I/O request which caused aninterrupt to occur. ION and IOF enable and disable interrupts. Interrupts willbe explained more fully shortly.


I/O execute cycles

p = D7IT3 p: SC ← ← 0

(INP) pIR11: AC(7-0) ← ← INPR, FGI ← ← 0(OUT) pIR10: OUTR ← ← AC(7-0), FG0 ← ← 0(SKI) pIR9: IF FGI = 1 THEN PC ← ← PC+1(SKO) pIR8: IF FGO = 1 THEN PC ← ← PC+1(ION) pIR7: IEN ← ← 1(IOF) pIR6: IEN ← ← 0

In the Basic Computer, I/O requests are processed as interrupts. This processis followed for input requests. The input will only be processed if interruptsare enabled. It will be ignored, but will remain pending, if interrupts aredisabled.


Input operation

u Input device makes data available and setsFGI=1.

u If interrupt is enabled, Basic Computer callsinterrupt routine at location 0, which disablesfurther interrupts.

u Interrupt routine reads in and processes data,re-enables interrupts and returns. Reading indata resets FGI to zero.

Outputs are handled similarly to inputs. Note that both input and outputinterrupts call an interrupt service routine at location 0. There is only oneroutine for both input and output, so it must distinguish between the two. Thisis where the SKI and SKO instructions become useful.


Output operation

u Output device requests data and sets FGO=1.u If interrupt is enabled, Basic Computer calls

interrupt routine at location 0, which disablesfurther interrupts.

u Interrupt routine processes and outputs data,re-enables interrupts and returns. Writing outdata resets FGO to zero.

It is of the utmost importance to complete the current instruction, otherwise theCPU will not perform properly.

The interrupt service routine is called by the CPU in a manner similar to theexecution of the BSA instruction.


Interrupt processing

u An interrupt occurs if the interrupt isenabled (IEN = 1) AND an interrupt ispending (FGI or FGO = 1).

u Before processing the interrupt,complete the current instruction!!!

u Call the interrupt service routine ataddress 0 and disable interrupts.

An interrupt is asserted by setting R to 1. This occurs when interupts areenabled (IEN) and there is either an input or output request (FGI+FGO). Wemust also have completed the current fetch cycle (T0’T1’T2’).

When we look at the code to implement the interrupt cycle, we see why wemust wait until after T2 to set R to 1. If we set R to 1 during T0, for example,the next micro-instruction would be RT1, right in the middle of the interruptcycle. Since we want to either perform an entire opcode fetch or an entireinterrupt cycle, we don’t set R until after T2.

The interrupt cycle acts like a BSA 0 instruction. During T0 we write a 0 intoAR and copy the contents of PC, the return address, to TR. We then store thereturn address to location 0 and clear the program counter during T1. In T2, weincrement PC to 1, clear the interrupt enable, set R to zero (because we’vefinished the interrupt cycle) and clear SC to bring us back to T0.

Note that IEN is set to 0. This disables further interrupts. If another interruptoccurred while one was being serviced, the second interrupt would write itsreturn address into location 0, overwriting the interrupt return address of theoriginal routine. Then it would not be possible to return to the programproperly.


Interrupt cycle

Activating an interrupt request:

T0’ T1’ T2’(IEN)(FGI + FGO): R ← 1← 1

Interrupt cycle:

RT0: AR ←← 0, TR ←← PCRT1: M[AR] ←← TR, PC ←← 0RT2: PC ←← PC + 1, IEN ←← 0, R ←← 0, SC ←← 0

This is exactly the same as before, but R’ tells us that no interrupts must beserviced.


Modified fetch cycle

R’T0: AR ←← PCR’T1: IR ←← M[AR], PC ←← PC+1R’T2: AR ←← IR(11-0), I ←← IR15,

D0, D1, ... D7 ←← Decode IR(14-12)

Your textbook gives a design example for part of the CPU. Here is anotherexample.

It doesn’t matter to E which micro-instructions read its data, only those thatchange its contents.


Example: design of E register

1. Determine which micro-operationschange the contents of register E

rIR10: E ← ← 0rIR8: E ← ← ErIR7: EAC ←← cir(EAC)rIR6: EAC ← ← cil(EAC)rIR5: EAC ← ← AC+1

For most other registers in this CPU, data is supplied from the data bus. Forthe accumulator, data also comes from the Adder/Logic unit.


Example: design of E register

2. Determine input data logic

All data comes from Adder/Logic unit

3. Determine input signals

We need only a load signal for this register:

LOAD(E) = r^(IR10 ∨ ∨ IR8∨∨IR7∨∨IR6∨∨IR5)

This module has presented the Basic Computer. We have reviewed itsinstruction formats and its instruction set. We have developed the controlsignals necessary to realize this instruction set. We have added interrupts tothe computer and gone through a sample component design.

In the next module we will get more in depth into CPU design, including amore detailed description of the ALU.


Summary

þBasic Computer specificationþ Instruction formats and instruction setþControl signalsþ InterruptsþExample hardware designþNext module: CPU Design

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