Base 1394 Test Suite Definition with Extensions for 1394b...

Document number 2002005

Base 1394 Test Suite Definition with Extensions for 1394b and IEEE-1394-2008

Version 2.3

October 25, 2010 Sponsored by:

1394 Trade Association

Accepted for publication by

1394 Trade Association Board of Directors

Abstract

This document defines the 1394TA's Base 1394 Test Suite test definition.

Keywords

IEEE1394, Test, Compliance.

1394 Trade

Association

Specification

1394 Trade Association Specifications are developed within Working Groups of the 1394

Trade Association, a non-profit industry association devoted to the promotion of and

growth of the market for IEEE 1394-compliant products. Participants in Working Groups

serve voluntarily and without compensation from the Trade Association. Most

participants represent member organizations of the 1394 Trade Association. The

specifications developed within the working groups represent a consensus of the

expertise represented by the participants.

Use of a 1394 Trade Association Specification is wholly voluntary. The existence of a

1394 Trade Association Specification is not meant to imply that there are not other ways

to produce, test, measure, purchase, market or provide other goods and services related to

the scope of the 1394 Trade Association Specification. Furthermore, the viewpoint

expressed at the time a specification is accepted and issued is subject to change brought

about through developments in the state of the art and comments received from users of

the specification. Users are cautioned to check to determine that they have the latest

revision of any 1394 Trade Association Specification.

Comments for revision of 1394 Trade Association Specifications are welcome from any

interested party, regardless of membership affiliation with the 1394 Trade Association.

Suggestions for changes in documents should be in the form of a proposed change of text,

together with appropriate supporting comments.

Interpretations: Occasionally, questions may arise about the meaning of specifications in

relationship to specific applications. When the need for interpretations is brought to the

attention of the 1394 Trade Association, the Association will initiate action to prepare

appropriate responses.

Comments on specifications and requests for interpretations should be addressed to:

Editor, 1394 Trade Association

315 Lincoln, Suite E

Mukilteo, WA 98275

USA

1394 Trade Association Specifications are adopted by the 1394 Trade

Association without regard to patents which may exist on articles,

materials or processes or to other proprietary intellectual property

which may exist within a specification. Adoption of a specification by

the 1394 Trade Association does not assume any liability to any patent

owner or any obligation whatsoever to those parties who rely on the

specification documents. Readers of this document are advised to

make an independent determination regarding the existence of

intellectual property rights, which may be infringed by conformance to

this specification.

Published by

1394 Trade Association

315 Lincoln, Suite E

Mukilteo, WA 98275 USA

Copyright © 2011 by 1394 Trade Association

All rights reserved.

Printed in the United States of America

1394 TA 2002005 Revision 2.3

Copyright ©2011, 1394 Trade Association. All rights reserved.

Table of Contents

1. Overview ..................................................................................................................................................... 1 1.1 Purpose ............................................................................................................................................... 2 1.2 Scope .................................................................................................................................................. 2

2. References ................................................................................................................................................... 3

3. Definitions ................................................................................................................................................... 4 3.1 Conformance Levels .......................................................................................................................... 4 3.2 Glossary of Terms .............................................................................................................................. 4 3.3 Acronyms and Abbreviations ............................................................................................................. 4

4. PHYsical Layer Testing .............................................................................................................................. 5 4.1 Overview ............................................................................................................................................ 5 4.2 System Board Testing ........................................................................................................................ 5

- 4.2.1 Test Equipment for System Board Testing 6 4.2.1.1 Special Test Fixtures ...................................................................................................... 6 4.2.1.2 Standard Test Equipment ............................................................................................. 11

4.3 Data Strobe (DS) Testing ................................................................................................................. 12 - 4.3.1 Termination 12

4.3.1.1 Differential Termination Measurement Method .......................................................... 12 4.3.1.2 Differential Termination Test Results .......................................................................... 13 4.3.1.3 Common Mode Load Measurement Method (DS capable ports only) ........................ 13 4.3.1.4 Common Mode Load Test Results ............................................................................... 15

- 4.3.2 Input Impedance (optional) 15 4.3.2.1 Input Impedance Test Method ..................................................................................... 19 4.3.2.2 Input Impedance Test Result ........................................................................................ 19

- 4.3.3 DS Signal Integrity Test Methods 19 4.3.3.1 DS Transmit Jitter Test Result ..................................................................................... 19 4.3.3.2 DS Transmit Skew Test Result .................................................................................... 20 4.3.3.3 DS Transmit Rise/Fall time Test Result ....................................................................... 21 4.3.3.4 DS Differential Amplitude Test Result ........................................................................ 21

- 4.3.4 Preferred DS Transmit Signal Integrity Test Method 21 - 4.3.5 Legacy DS Transmit Signal Integrity Test Methods 22

4.3.5.1 Legacy DS Transmit Jitter ........................................................................................... 22 4.3.5.2 Test Methods ................................................................................................................ 24

4.3.5.2.1 Connection Signal Integrity Board (SIB) ....................................................................... 24 4.3.5.2.2 DS Jitter Measurement Method 1 ................................................................................... 25 4.3.5.2.3 DS Jitter Measurement Method 2 ................................................................................... 26

4.3.5.3 DS Transmit Skew ....................................................................................................... 27 4.3.5.3.1 Equipment Specialized ................................................................................................... 27 4.3.5.3.2 Test Methods .................................................................................................................. 27

4.3.5.4 DS Transmit Rise/Fall time .......................................................................................... 32 4.3.5.4.1 Equipment Specialized ................................................................................................... 32 4.3.5.4.2 Test Method .................................................................................................................... 33

4.3.5.5 DS Differential Amplitude ........................................................................................... 34 4.3.5.5.1 Equipment Specialized ................................................................................................... 34

4.4 Beta Testing ..................................................................................................................................... 35 - 4.4.1 Beta Transmit Near End Test 35

4.4.1.1 Test Topology .............................................................................................................. 36 4.4.1.2 Connections ................................................................................................................. 36 4.4.1.3 Trigger ......................................................................................................................... 37 4.4.1.4 Digital Sampling Scope Connection ............................................................................ 37

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4.4.1.5 Test Procedure ............................................................................................................. 39 4.4.1.5.1 Differential Measurement .............................................................................................. 39 4.4.1.5.2 Single Ended Measurement ........................................................................................... 39

4.4.1.6 Beta Transmit Test Specification and Methodology ................................................... 39 4.4.1.6.1 Near End Baud Rate ...................................................................................................... 39 4.4.1.6.2 Near End Differential Amplitude ................................................................................... 40 4.4.1.6.3 Near End Rise / Fall Times ............................................................................................ 40 4.4.1.6.4 Near End Eye Validation ............................................................................................... 41 4.4.1.6.5 Near End Differential skew ........................................................................................... 43 4.4.1.6.6 Near End Common mode voltage .................................................................................. 44 4.4.1.6.7 Near and Far End Jitter Measurement Methodology ..................................................... 44 4.4.1.6.8 Near End Jitter Measurements ....................................................................................... 45

- 4.4.2 Beta Transmit Far End Test 46 4.4.2.1 Test Topology ............................................................................................................. 47 4.4.2.2 Far End Baud rate ........................................................................................................ 48 4.4.2.3 Far End Differential amplitude .................................................................................... 48 4.4.2.4 Far End Eye Validation ............................................................................................... 48 4.4.2.5 Far End Differential skew ........................................................................................... 50 4.4.2.6 Far End Common mode voltage .................................................................................. 50 4.4.2.7 Far End Jitter Measurements ....................................................................................... 51

4.4.2.7.1 Far End Deterministic Jitter ........................................................................................... 51 4.4.2.7.2 Far End Random Jitter ................................................................................................... 51 4.4.2.7.3 Far End Total Jitter ........................................................................................................ 51

- 4.4.3 Beta Receiver Test 51 4.4.3.1 Receiver Sensitivity..................................................................................................... 51

4.4.3.1.1 Minimum Amplitude ..................................................................................................... 52 4.4.3.1.2 Receiver Sensitivity Test – Repeat Method ................................................................... 52 4.4.3.1.3 Receiver Sensitivity Test – Port_error Method .............................................................. 52 4.4.3.1.4 Error Rate Calculation ................................................................................................... 53

4.5 Cable Power ..................................................................................................................................... 53 - 4.5.1 Cable Power DC 53

4.5.1.1 Cable Power Suppliers ................................................................................................ 55 4.5.1.2 Cable Power Consumers ............................................................................................. 56 4.5.1.3 Self Powered Devices .................................................................................................. 56

- 4.5.2 Cable Power Testing 56 4.5.2.1 Cable Power Source POWER Test ............................................................................. 58 4.5.2.2 Cable Power Source Voltage Test ............................................................................... 58 4.5.2.3 Cable Power Source Ripple Test ................................................................................. 59 4.5.2.4 Cable Power Current Limiting Test ............................................................................ 59 4.5.2.5 Cable Power Consumption Test .................................................................................. 59 4.5.2.6 Cable Power Energy In-Rush Test .............................................................................. 60 4.5.2.7 Cable Power Repeating/Isolating test .......................................................................... 60

4.5.2.7.1 Test for No power repeated ............................................................................................ 61 4.5.2.7.2 Test for repeats with 1.5 amp limiters ............................................................................ 61 4.5.2.7.3 Test for Repeats without limiters ................................................................................... 62 4.5.2.7.4 Test for Source with diode isolation .............................................................................. 62

5. Link Enabled Node Testing ....................................................................................................................... 63 5.1 Overview .......................................................................................................................................... 63

- 5.1.1 Required Changes for 1394b 63 - 5.1.2 Required Functions 63 - 5.1.3 Optional Functions 64

5.2 Link Enable Testing Procedures ....................................................................................................... 65 - 5.2.1 Transaction Capable 65

5.2.1.1 Determine if Transaction Capable Node Test Procedure ............................................ 65

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Copyright ©2011, 1394 Trade Association. All rights reserved. v

5.2.1.2 Core CSR Register Support Test Procedure ................................................................ 65 5.2.1.2.1 STATE_CLEAR and SET Test Procedure ..................................................................... 65 5.2.1.2.2 NODE_IDS Test Procedure ............................................................................................ 66 5.2.1.2.3 RESET_START Test Procedure .................................................................................... 67 5.2.1.2.4 SPLIT_TIMEOUT Test Procedure ................................................................................. 68

5.2.1.3 Configuration ROM Presence Test Procedure ............................................................. 70 5.2.1.4 Minimal ROM Format Test Procedure ........................................................................ 71 5.2.1.5 General ROM Format Test Procedure ......................................................................... 71 5.2.1.6 Block Packet Support Test Procedure .......................................................................... 72 5.2.1.7 Multiple Speed Transaction Support Test Procedure ................................................... 72 5.2.1.8 Determination of Speed Route Test Procedure ............................................................ 74

- 5.2.2 Isochronous Capable Node 75 5.2.2.1 Isoc General ROM Support Test Procedure ................................................................. 75 5.2.2.2 CYCLE_TIME CSR Test Procedure ........................................................................... 75

- 5.2.3 Cycle Master Capable Node 76 5.2.3.1 CMC General ROM Support Test Procedure .............................................................. 76 5.2.3.2 CYCLE_TIME CSR Test Procedure ........................................................................... 76 5.2.3.3 BUS_TIME CSR Test Procedure................................................................................. 76 5.2.3.4 Generation of Cycle Start Packets Test Procedure ....................................................... 77

- 5.2.4 Isochronous Resource Manager Capable Node 78 5.2.4.1 IRM General ROM Support Test Procedure ................................................................ 79 5.2.4.2 IRM Determination Test Procedure ............................................................................. 79 5.2.4.3 Enhanced IRM Determination Test Procedure ............................................................ 80 5.2.4.4 BUS_MANAGER_ID Test Procedure ........................................................................ 80 5.2.4.5 BANDWIDTH_AVAILABLE Test Procedure ........................................................... 83 5.2.4.6 CHANNELS_AVAILABLE Test Procedure ............................................................... 87 5.2.4.7 BROADCAST_CHANNEL Test Procedure ............................................................... 90 5.2.4.8 Gap_count Optimization Test Procedure ..................................................................... 92

- 5.2.5 Bus Manager Capable Node 93 5.2.5.1 SBM General ROM Support Test Procedure ............................................................... 94 5.2.5.2 Bus Manager Determination Test Procedure ............................................................... 94

5.2.5.2.1 Stability of Bus Manager ................................................................................................ 95 5.2.5.3 TOPOLOGY_MAP CSR Test Procedure .................................................................... 97 5.2.5.4 Other Supported CSRs ................................................................................................. 99 5.2.5.5 Bus Manager Responsibilities Test Procedure ............................................................. 99

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List of Figures

Figure 1: Compliance Logo Program Document Structure. ............................................................................1 Figure 4: SIB 4-pin, 6-pin and 9-pin to 6-pin 1394a Board. ............................................................................8 Figure 5: Signal Integrity Board for IEEE-1394b with test fixture. ................................................................9 Figure 7: DVM Interface Board. ................................................................................................................... 10 Figure 8: Cable Power Tester ........................................................................................................................ 11 Figure 9: TDR Connector Reference. ............................................................................................................ 16 Figure 10: TDR Input Impedance Measurement, Nominal Case. .................................................................. 17 Figure 11: TDR Input Impedance Measurement, Pass with Violation. ......................................................... 17 Figure 12: TDR Input Impedance Measurement, Fail with Violation. .......................................................... 18 Figure 13: TDR Input Impedance Measurement, Fail with Multiple Violations. .......................................... 18 Figure 14: Jitter, Skew, and Rise/Fall Time Test Topologies. ....................................................................... 23 Figure 15: Transmitter Bit Cell Margin at S400 ............................................................................................ 24 Figure 16: Trigger and Next Edge Jitter measurement. ................................................................................. 26 Figure 17: Trigger for Jitter Measurement..................................................................................................... 26 Figure 18: Skew Measurement Trigger. ........................................................................................................ 29 Figure 19: Skew Measurement Bit Location ................................................................................................. 30 Figure 20: Skew Measurement with Three Signal Traces. ............................................................................ 30 Figure 21: Skew Measurement Detailed View .............................................................................................. 31 Figure 22: Rise / Fall Time Measurement on Scope ...................................................................................... 33 Figure 23: Measurement points (half connection is shown) .......................................................................... 35 Figure 24 - Balanced Transmitter Test Circuit .............................................................................................. 36 Figure 25: Test Topology ............................................................................................................................. 36 Figure 26: Trigger Connection ...................................................................................................................... 37 Figure 27: Acquire Diff Probe Connection .................................................................................................... 37 Figure 28: Acquire SEn Connection with two Single Ended Probes ............................................................. 38 Figure 29: Acquire SEn with two Differential Probes ................................................................................... 38 Figure 30: Absolute eye diagram mask at TP2 .............................................................................................. 42 Figure 31: Normalized eye diagram mask at TP2 ......................................................................................... 42 Figure 32: Sample near end eye diagram. ...................................................................................................... 43 Figure 33: Received Load Equivalent Circuit .............................................................................................. 47 Figure 34: Far End Signal Integrity Test Topology. ...................................................................................... 48 Figure 35: Eye diagram mask at point TP3 ................................................................................................... 49 Figure 36: Sample far end eye diagram. ........................................................................................................ 50 Figure 37: General Cable Power Test Configuration..................................................................................... 57 Figure 38: Speed route test topology ............................................................................................................. 74 Figure 39: Gap_count short haul test topology .............................................................................................. 93 Figure 40: Gap_count optical test topology ................................................................................................... 93

1394 TA 2002005 Revision 2.3

Copyright ©2011, 1394 Trade Association. All rights reserved. vii

List of Tables

Table 1: Differential Termination Measurement Results .............................................................................. 13 Table 2: Common Mode Load Measurement Results ................................................................................... 15 Table 3: Input impedance parameters. ........................................................................................................... 15 Table 4: Input Impedance Test Results. ........................................................................................................ 19 Table 5: Two Differential Probe Configuration ............................................................................................ 38 Table 6: One Diff and Two SE Probe Connection ........................................................................................ 39

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viii


Forward (This foreword is not part of 1394 Trade Association Specification 2002005)

This document defines the 1394TA's Base 1394 Test Suite test definition.

There is 1 annex in this specification. Annex A is informative and are not considered part of this

specification.

This specification was accepted by the Board of Directors of the 1394 Trade Association. Board of

Directors acceptance of this specification does not necessarily imply that all board members voted for

acceptance. At the time it accepted this specification, the 1394 Trade Association. Board of Directors had

the following members:

Max Bassler, Chair

Morten Lave, Vice-Chair

Dave Thompson, Secretary

Organization Represented Name of Representative

Littelfuse .............................................................................................................. Max Bassler

PLX Technology .................................................................................................. Don Harwood

Texas Instruments ................................................................................................ Toni Ray

LSI ....................................................................................................................... Dave Thompson

TC Applied Technologies .................................................................................... Morten Lave

Aztek Corp. .......................................................................................................... Richard Mourn

The Compliance Working Group which developed and reviewed this specification had the following

members:

Richard Mourn, Chair

1394 TA 2002005 Revision 2.3

Copyright ©2011, 1394 Trade Association. All rights reserved. ix

Revision history

Revision Draft 2.3 (October 25, 2010)

- Changed Beta differential amplitude to reflect IEEE-1394b-2002 and -2008 Standards

Revision Draft 2.2 (July 8, 2010)

- Change title from Base 1394 Test Suite with Extension for 1394b to Base 1394 Test Suite with

Extension for 1394b and IEEE-1394-2008

- Added figure reference for Cable Power Tester

- Changed S1600 minimum differential amplitude to match IEEE-1394-2008

- Changed S1600 maximum rise/fall time to match IEEE-1394-2008

- Update IEEE-1394b to IEEE-1394-2008

- Update Beta test topology pictures

- Made changes to the Cable Power Test section. Removed some requirements for Primary Power

Providers.

Revision Draft 2.1 (April 27, 2010)

- Added note concerning AC-coupled receiver sensivity test.

Revision Draft 2.1 (April 22, 2010)

- Added new Preferred DS test method

- Added new Beta transmit test parameters include updated Jitter parameters

- Updated test tools – current versions and preferred DS test method

Revision 2.0 (Official 1394TA Release – August 29, 2007)

Revision Draft 1.8.6 (August 29, 2007)

- Adjusted test points to align with p1394r

Revision Draft 1.8.5 (August 27, 2007)

- Clarified test points used for beta transmit testing

- Added test circuits for both Near End and Far End transmit tests

- Reinstated 300mV minimum differential voltage level with 475mV recommendation

- Added Revision history

- Clarified that receiver sensitivity test has controllable outputs

- Adjusted heading for cable power chapter

Revision Draft 1.8.4 (June 19, 2007)

- Clarified Scope to include third party and self-testing

- Clarified test points used fro beta transmit testing

- Increased minimum differential from 300mV to 475mV

Revision Draft 1.8.3 (May 10, 2007)

- Various editorial changes

- Added statement indicating the beta test parameters came for 1394b and errata.

- Adjusted headings

- Adjusted all beta parameters to errata levels

- Added explaination of beta receive repeat and Port_error method

- Added explanation of cable power repeating and isolating

1394 TA 2002005 Revision 2.3

x


Revision Draft 1.8.2 (March 23, 2007)

- Various editorial changes

- Added beta 9 pin test fixtures

- Added receiver sensivity and transmit tester

- Added oscope sample rate requirement

Revision Draft 1.8.1 (February 14, 2007)

- Added Beta test tools

- Added Beta tests

- Made input impedance optional

- Added gap count optimization test

- Added speed trap test

1394 TA 2002005 Revision 2.3


1. Overview

The 1394 Trade Association (1394TA) Compliance Logo Program provides a structure whereby a product

containing an IEEE-1394 interface is able to earn the right to use the 1394TA Compliance Logo1. Within

the structure, a set of tests have been defined to quantify a product‘s potential for interoperability with other

products within the industry and thus provide the user with the best possible experience. The tests have

been grouped into four (4) ‗test suites‘:

- Point-to-Point Private Test Suite(s) (Plugfests)

- Base 1394 Test Suite

- Network Interoperability Test Suite

- Functional Operability Test Suite

Corresponding to this structure there are a growing number of test specifications and procedural

documents, each of which define specific tests or test suite operation.

Point-to-Point

Private

Test Suite

Guideline

Functional

Operability

Test Suite

Definition(s)

Network

Interoperability

Test Suite

Definition(s)

Base 1394

Test Suite

Specification

Electrical

1394/1212

Protocol

OHCI

Test Spec

SBP-2

Mass

Storage Test

Spec

MacOS

Computer

Test

Case(s)

Win-XP

Computer

Test

Case(s)

Test Specifications

Registration

Form

Private

Plugfest

Results

Form

Product

Category

List

Registration

Form

Instructions

Private

Plugfest

Results

Form

Instructions

Figure 1: Compliance Logo Program Document Structure.

1 Please see the 1394TA website for specific guidelines as to the use of the 1394TA Compliance Logo.

1394 TA 2002005 Revision 2.3

2


1.1 Purpose

The 1394TA has developed a logo program. To obtain a license to use the logo, a product must pass a set of

test criteria. This document defines the criteria for the Base 1394 Test Suite and includes the changes and

enhancement of IEEE-1394-2008.

1.2 Scope

This document is intended to define the test requirements for the Base 1394 Test Suite. Base, in this case,

implies all IEEE-1394 layers:

- PHYsical Layer

- Link Layer

- Transaction Layer

- Serial Bus Management Layer

The test suite will be executed at 1394TA-sponsored C&I Workshops, at Third-party test houses or at

companies that have been qualified for self-testing. Given the time scale (approximately 30 minutes)

allowed by the Workshop environment, the level of testing must be limited to fit this constraint yet provide

the maximum indication of proper functionality. To accomplish this it is necessary to require some testing

be completed before coming to the Workshop. While this document does not define the external test

requirements, it does provide pointers to the appropriate documents.

1394 TA 2002005 Revision 2.3

Copyright ©2011, 1394 Trade Association. All rights reserved. 3

2. References

The following standards contain provisions, which through reference in this document, constitute

provisions of this standard. All the standards listed are normative references. Informative references are

given in Annex A. At the time of publication, the editions indicated were valid. All standards are subject to

revision, and parties to agreements based on this standard are encouraged to investigate the possibility of

applying the most recent editions of the standards indicated below.

[R1] IEEE Std 1394-1995, Standard for a High Performance Serial Bus

[R2] IEEE Std 1394a-2000, Standard for a High Performance Serial Bus – Amendment 1

[R3] IEEE Std 1394b-2002, Standard for a High Performance Serial Bus – Amendment 2

[R4] 1394 TRADE ASSOCIATION Power Specification Part 1: Cable Power Distribution

[R5] 1394 TRADE ASSOCIATION Technical Bulletin 1394b Clarifications and Errata 2.0

[R6] IEEE Std 1394-2008, Standard for High Performance Serial Bus

1394 TA 2002005 Revision 2.3

4


3. Definitions

3.1 Conformance Levels

3.1.1 expected: A key word used to describe the behavior of the hardware or software in the design models

assumed by this Specification. Other hardware and software design models may also be implemented.

3.1.2 may: A key word that indicates flexibility of choice with no implied preference.

3.1.3 shall: A key word indicating a mandatory requirement. Designers are required to implement all such

mandatory requirements.

3.1.4 should: A key word indicating flexibility of choice with a strongly preferred alternative. Equivalent

to the phrase is recommended.

3.1.5 reserved codes: A set of codes for a reserved field that are defined in this specification, but not

otherwise used. Future specifications may implement the use of these codes. A product implementing this

specification shall not generate, nor receive these codes.

3.1.6 reserved fields: A set of bits for a reserved field that are defined in this specification, but are not

otherwise used. Products that implement this specification shall zero these fields and shall not check the

reserved field‘s value. Products that implement future revisions of this specification may set these codes as

defined by the specification.

NOTE — The IEEE is investigating whether the ―may, shall, should‖ and possibly ―expected‖ terms will be formally

defined by IEEE. If and when this occurs, draft editors should obtain their conformance definitions from the latest

IEEE style document.

3.2 Glossary of Terms

3.2.1 byte: Eight bits of data, used as a synonym for octet.

3.2.2 CSR Architecture: A convenient abbreviation of the following reference (see clause 2): ISO/IEC

13213 : 1994 [ANSI/IEEE Std 1212, 1994 Edition], Information Technology—Microprocessor systems—

Control and Status Register (CSR) Architecture for Microcomputer Buses.

3.2.3 quadlet: Four bytes of data.

3.3 Acronyms and Abbreviations

PHY IEEE-1394 PHYsical layer silicon device

IUT Implementation Under Test

DUT Device Under Test: For the purposes of this document DUT is interchangeable with IUT

SMA is an acronym for SubMiniature version A connector

1394 TA 2002005 Revision 2.3


4. PHYsical Layer Testing

4.1 Overview

The IEEE-1394-1995, IEEE-1394a-2000, and IEEE-1394b-2002 (which are combined in IEEE-1394-2008)

PHYsical Layer, when implemented, is comprised of three primary components:

- Cable and Connector

- System board

- PHYsical layer silicon device (PHY)

For the purposes of the Base 1394 Test Suite the Implementation Under Test (IUT) will be viewed as a

black box with the 1394 connector as the only access to the IUT. With this limited view and the ultimate

importance of the PHYsical Layer to interoperability of 1394 devices, the Base 1394 Test Suite will rely on

the 1394 Trade Association‘s listing of approved Cables, Connectors, and PHY silicon.

What does this mean?

1394 enabled end-products, which are likely to contain 1394 cables, connectors and PHY silicon, wishing

to receive a 1394 logo for said product, must have the appropriate documentation declaring that the 1394

cables, connectors, and whenever possible the PHY silicon incorporated in the product have passed their

respective tests. Please see the following 1394 Trade Association documents for details about each test:

- 1394 Connector and Cable Compliant Testing Criteria 2009008 (1394 Connector and Cable

Compliant Testing Criteria – Revision 1.0)

- PHY Silicon Test Specification Document 2006022

What is tested:

The only PHYsical layer component specifically targeted by the Base 1394 Test Suite is the system board.

The system board includes:

- 1394 connector connection to the printed circuit board (PCB). This may include any dongle that

connects the 1394 connector to the PCB, i.e. a 1394 connector dongle to PCMCIA card.

- PCB traces

- Termination, loading and filtering

- PCB connection to PHY device

- 1394 cable power

While not specifically targeting the PHY silicon device, certain PHY parameters are measured to verify the

system board‘s effect on those parameters.

4.2 System Board Testing

IEEE-1394 provides methods for testing parameters such as input impedance and crosstalk of cables.

However, these methods fall short when trying to analyze the entire system that make up a 1394

interconnect. Therefore, this document provides new methods that meet the real world requirements of

testing the system board and doing so in a relatively short period of time.

The following tests are conducted:

DS capable ports

- Termination

- Common Mode Load

- Transmit Jitter

- Transmit Skew

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- Transmit Rise and Fall Time

- Differential amplitude

Beta capable ports

- Termination

Transmit baud rate

Transmit jitter

Transmit differential amplitude

Transmit rise/fall time

Transmit eye validation

Transmit differential skew

Transmit common mode voltage

Receiver sensitivity

General

- Cable Power Source Power

- Cable Power Source Voltage

- Cable Power Source Ripple

- Cable Power Current Limiting

- Cable Power Consumption

- Cable Power Energy In Rush

- Cable Power Repeating/Isolating

4.2.1 Test Equipment for System Board Testing

4.2.1.1 Special Test Fixtures

Preferred Data/Strobe (DS) Test Method

Signal Integrity Test Controller and Test Boards

There is one Signal Integrity Test Controller (QP-SSIB) and three versions of Signal Integrity

Board (SSIB-TF): 4-pin, 6-pin and 9-pin (QP-SSIB-TF-4, QP-SSIB-TF-6 and QP-SSIB-TF-9. The

SSIB and SSIB-SIB along with software allows for a more idealistic (as defined by the Standard)

measurements to be taken than the Legacy test fixture mentioned in the next section by allowing

the signals to be measure at the end of net rather than in the middle of the transmission line.

1394 TA 2002005 Revision 2.3


Figure 2: QP-SSIB Test Controller

Figure 3: QP-SSIB-TF

1394 TA 2002005 Revision 2.3

8


Legacy Data/Strobe (DS) Test Method

Signal Integrity Boards – Data/Strobe (DS)

There are three versions of the Signal Integrity Board (SIB): 4-pin, 6-pin and, 9-pin (QP-SIB426,

QP-SIB626 and QP-SIB926) . SIB is essentially a break out board that provides an interface for an

oscilloscope. SIB is used for Skew, Jitter, Amplitude and Rise and Fall Time measurements.

Figure 4: SIB 4-pin, 6-pin and 9-pin to 6-pin 1394a Board.

1394 TA 2002005 Revision 2.3


Transmit Signal Integrity – Beta

Transmit signal integrity requires both hardware and software components (QP-SIGKit4B Rev.

C). The QP-SIGKit4B Rev. C consists of a Signal Integrity Test Controller for 1394b (QP-

SIB4B), test fixture (QP-SIB4B-TF) and Control and Post Processing software. The control

software coupled with the QP-SIB4B provide the connection, speed and ack tones required to put

the IUT into the training phase. QP-SIB4B-TF provides the test loads defined by IEEE-1394 plus

end of net test points for oscilloscope connection.

Figure 5: Signal Integrity Board for IEEE-1394b with test fixture.

Signal Integrity and Receiver Sensitivity Tester – Beta

Signal Quality Tester for 1394b (QP-SQT) provides the same transmit signal integrity test

capability as QP-SIGKit4B rev C plus the receiver sensitivity tester which provides variable

amplitude output and is required by this specification. Please see the beta receiver sensitivity test

for details.

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10


Figure 6: Signal Quality Tester

DVM Interface Board- 1394a

The DVM interface board allows easy connection to most Digital Voltage Meters (referred to as

Digital Multi-Meter (DMM) throughout this document). This board is used to measure termination

and common load of the Implementation Under Test (IUT).

Figure 7: DVM Interface Board.

1394 TA 2002005 Revision 2.3


Cable Power Tester

Please see Annex A: for details.

Used for: All Cable Power testing. Please contact Quantum Parametrics LLC for details about the

cable power tester.

Figure 8: Cable Power Tester

4.2.1.2 Standard Test Equipment

DMM – 3 Digit Resolution

Use: Termination, Common Mode Load, Cable Power Sourcing, Cable Power Sinking tests.

Oscilloscope –

The bandwidth of the oscilloscope should be at least 3x the highest switching frequency of the signal being

measure or 0.35/fastest rise time, whichever is greater.

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Example: Data Strobe – S400

393.216MHz x 3 = 1.18GHz

0.35/500ps = 700MHz

Bandwidth of 1.18 GHz is required for S400 Data Strobe signaling

Example: Beta – S800

983.04MHz x 3 = 2.95GHz

0.35/80ps = 4.38GHz

Bandwidth of 4.38 GHz is required for S800 Beta signaling

The sampling rate of the oscilloscope should be at least 4x the bandwidth requirement and capable of

acquiring at least two samples for each rising/falling edge (between the 10% and 90% points).

Power Supply - +33 volt 1.5A power supply with current limiting and current meter

Use: Cable Power Sourcing and Sinking

4.3 Data Strobe (DS) Testing

4.3.1 Termination

The system board‘s termination of the cables differential characteristic impedance it very important and can

easily be measured by placing an ohmmeter across the differential pair. For DS capable ports the

differential termination network consists of two resistors with a common mode tap between them. TPA

provides the bias voltage through its tap and TPB provides the common mode load through its tap. For Beta

only ports without AC coupling both TPA and TPB have differential termination networks consisting of

two resistors with a common mode tap between them. Unlike DS capable ports this common mode point is

strictly for noise filtering. For the purposes of this test when AC coupled the TPB differential termination is

not measurable.

4.3.1.1 Differential Terminat ion Measurement Method

Connect an ohmmeter across TPA and TPB of each port and verify differential termination for TPA and

TPB. The measured values are assigned to variables ‗RTAn‘ and ‗RTBn‘ respectively.

If using the DVM Interface Board use the following procedure:

Note: IUT should remain off (no power) for the duration of this test.

1. Connect DMM positive lead to TP1

2. Connect DMM negative lead to TP2

3. Connect the IUT to CN1 with the appropriate cable. The resistance of the cable can be significant

therefore calibrating out the resistance of the cable is necessary. To calibrate out the resistance of

the cable measure the resistance of each signal conductor and sum the measured values for each

1394 TA 2002005 Revision 2.3


signal within the pair (TPA + TPA‘ and TPB + TPB‘) and subtract that value from the resistance

measurement for the appropriate pair.

4. To measure the differential termination of TPA, switch SW1 to the TPA Terminator setting. To

measure the differential termination of TPB, switch SW1 to the TPB Terminator setting

5. Select the highest resolution setting on the DMM that will still measure approximately 120Ω or

less

6. Repeat steps 1 through 5 for each port, recording the value reported by the DMM

4.3.1.2 Differential Terminat ion Test Results

Parameter Description Min Max Units

Differential

Termination

Differential characteristic impedance 104 116 Ω

Port Measured Units

Port 0 TPA Variable RTA0 Ω

Port 0 TPB Variable RTB0 Ω

Port 1 TPA Variable RTA1 Ω

Port 1 TPB Variable RTB1 Ω

Port n Variable RTBn Ω

Table 1: Differential Termination Measurement Results

4.3.1.3 Common Mode Load Measurement Method (DS capable ports only)

The system board must implement a common load (RL) for TPB. The load should be 5KΩ +/-5%. The load

is connected from VG to a common mode point between TPB and TPB‘ and is used as the return path for

the bias current.

Using the Differential Termination measurement from TPB (taken in the previous section) together with

the following measurements and calculation the Common Mode Load is determined.

1) Measure the resistance from TPB+ to VG; this value will be called Zn.

2) Measure the resistance from TPB- to VG; this value will be called Zn‘.

The value of Zn and Zn‘ are each made of two components: a common component, the common mode load

resistor (RLn), and an independent but related component, each half of the differential termination resistor

network (Rn and Rn‘). From the previous procedure, the summed value of Rn + Rn‘ was measured and

assigned to the variable RTBn.

Rn + Rn‘ = RTBn

Therefore, Rn = RTBn – Rn‘

Steps 1) and 2) determined the measured values of Zn and Zn‘. These values are used in the following

equations:

Zn = Rn + RLn and

Zn‘ = Rn‘ + RLn

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Substituting, RTBn – Rn‘ for Rn

Zn = RTBn – Rn‘ + RLn

Common Mode Load value (RLn)

RLn = Zn - RTBn + Rn‘

RLn = Zn‘ – Rn‘

Now solve for Rn‘

Zn - RTBn + Rn‘ = Zn‘ – Rn‘

2Rn‘ = (Zn‘ – Zn + RTBn)

Rn‘ = (Zn‘ – Zn + RTBn)/2

Finally substitute (Zn‘ – Zn + RTBn)/2 for Rn‘ in the equation RLn = Zn‘ – Rn‘

RLn = Zn’ – (Zn’ – Zn + RTBn)/2

Example:

RTB0 = 110 Ω

Z = 5,050 Ω

Z‘ = 5,060 Ω

RL + R = Z = RTB0 – R‘ + RL

110 – R‘ + RL = 5,050

-R‘ + RL = 4,940

RL = 4,940 + R‘

RL + R‘ = Z‘

RL + R‘ = 5,060

RL = 5060 – R‘

4,940 + R‘ = 5060 – R‘

2R‘ = 120

R‘ = 60

R + R‘ = 110

R + 60 = 110

R = 50

Common Mode Load value (RL)

RL + R‘ = Z‘

RL = Z‘ – R‘

RL + 60 = 5,060

RL = 5,000

If using the DVM Interface Board use the following procedure:

Note: IUT should remain off (no power) for the duration of this test.

1. Connect DMM positive lead to TP1

1394 TA 2002005 Revision 2.3


2. Connect DMM negative lead to TP2

3. Connect the IUT to CN1 with the appropriate cable. The resistance of the cable can be significant

therefore calibrating out the resistance of the cable is necessary. To calibrate out the resistance of

the cable measure the resistance of each signal conductor and sum the measured values for each

signal within the pair (TPA + TPA‘ and TPB + TPB‘) and subtract that value from the resistance

measurement for the appropriate pair.

4. Switch SW1 to the TPB Common Load setting

5. Select the highest resolution setting on the DMM that will still measure approximately 5,200Ω

6. Using the TPB differential termination measurement taken in the previous section ( RTBn ), divide

it by 2 and subtract it from the measurement taken in step 5. This is the approximate value of RL.

Rmeasured – (RTBn /2) = RL

7. Repeat steps 1 through 6 for each port recording the value

4.3.1.4 Common Mode Load Test Results


Common Mode

Load

TPB‘s common mode load resistor

value

4,750 5,250 Ω

Port Measured Units

Port 0 TPB, RL Common mode resistor Ω

Port 1 TPB, RL Common mode resistor Ω

Port n, RL Ω

Table 2: Common Mode Load Measurement Results

4.3.2 Input Impedance (opt ional)

The AC loading specifications of a system board with the PHY device in the powered off state are specified

in terms of differential TDR (Time Domain Reflectometer) measurements. These measurements govern the

maximum allowable transmission line discontinuities for the port connector, the interconnect leading from

the connector to the transceiver, the transceiver package, but not the PHY IC itself as 1394 has not defined

a test mode to allow powered testing. In the special case of a product with a captive cable, the transmission

line discontinuities of the cable assembly are also governed.

Test Condition Parameter Value Units

Input impedance test conditions:

TDR rise time 500 ps

Input impedance:

Through Impedance 110+/-20 Ω

Table 3: Input impedance parameters.

The following specifications must be met with the incident rise time of the differential TDR set to 500ps.

500ps is the minimum rise/fall time allowed by IEEE-1394-1995. It is important to note that all times are

―as displayed‖ on the TDR and are hence ―round trip‖ times.

Disconnecting the TDR connection from the port connector and noting the time of the open circuit step

determines the connector reference time.

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Through Impedance (ZTHRU) is the impedance measured from 400ps (disregard the connector

impedance) after the connector reference location until the time 500ps before the lowest impedance point

dictated by the powered-down PHY IC. Therefore if the distance from the connector reference to the PHY

is less than 7.92cm, the measurement of this parameter is not applicable. The Through Impedance

parameter as defined by this specification is:

90 Ohms ≤ ZTHRU ≤ 130 Ohms

Within the Through impedance time window the differential impedance may exceed the Through limits.

However, no single excursion may exceed the Through limits for more than twice the TDR rise time of

500ps (1ns), and the average of the total Through impedance time shall not exceed the Through

impedance. In the special case of a product with a captive cable, the same specifications must be met, but

the TDR measurements must be made through the captive cable assembly.

The following picture (Figure 9) shows a waveform of a disconnect SMA to 1394 connector cable. This is

the connector reference time.

110 Ohms

130 Ohms

90 Ohms

Connector Reference

ZTHRU PHY IC Termination400ps

Figure 9: TDR Connector Reference.

The following pictures illustrate several of the possible results of the input impedance test. The first (Figure

10) shows a passing case where the first 400ps are ignored, the ZTHRU impedance is between 130 and 90

ohms the entire time before reaching the PHY device. Next (Figure 11) shows a passing case where a

violation of less than 1ns is observed. The third (Figure 12) picture shows a failing case with a violation

lasting longer than 1ns. The last (Figure 13) picture shows a failing case caused by multiple violations

resulting in the average ZTHRU to be greater than 1ns and is therefore in violation.

1394 TA 2002005 Revision 2.3


110 Ohms

130 Ohms

90 Ohms

Connector Reference


Low Impedance point

dictated by PHY IC

500ps

Figure 10: TDR Input Impedance Measurement, Nominal Case.

110 Ohms

130 Ohms

90 Ohms


Start of Violation End of Violation

< 1ns

Figure 11: TDR Input Impedance Measurement, Pass with Violation.

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110 Ohms

130 Ohms

90 Ohms

ZTHRU PHY IC400ps


> 1ns

Connector Reference

Figure 12: TDR Input Impedance Measurement, Fail with Violation.

110 Ohms

130 Ohms

90 Ohms

ZTHRU PHY IC400ps


> 1ns

Connector Reference

Average of multiple

violations is out of

specification and greater

than 1ns total.

Figure 13: TDR Input Impedance Measurement, Fail with Multiple Violations.

1394 TA 2002005 Revision 2.3


4.3.2.1 Input Impedance Test Method

This document defines one generic method for measuring input impedance using a TDR. This method

assumes the use of an SMA to 1394 connector cable as show in Figure 5 and Figure 6.

1. Connect appropriate SMA cables to TDR (TPA+ and TPA- or TPB+ and TPB-)

2. Set TDR to rise time (or filter) to 500ps

3. Find connector reference as shown in Figure 7

4. Mark (mark A) the point 400ps after connector reference as shown in Figure 7

5. Connect the Device Under Test to the TDR

6. Find the lowest impedance point dictated by the PHY

7. Mark (mark B) the point 500ps before the lowest impedance point dictated by the PHY as shown

in Figure 8

8. Is the time from mark A to mark B less than 1ns? If yes, then this test is not necessary.

9. If you answered No to step 8, observe the waveform and compare it to the definition and examples

provided in this section to determine Pass or Fail criteria

4.3.2.2 Input Impedance Test Result


ZTHRU Through input impedance 90 130 Ω

Port Pass/Fail

Port 0 TPA

Port 0 TPB

Port n TPA/TPB

Table 4: Input Impedance Test Results.

4.3.3 DS Signal Integri ty Test Methods

There are three methods for testing Data/Strobe transmit signal integrity. One is the preferred method and

two are legacy. Section 4.3.4 describes the preferred test method and section 4.3.5describes the two legacy

methods.

Regardless of the test method used, the same test parameters are referenced. The following sections provide

the parameters for which the test results shall be compared.

4.3.3.1 DS Transmit Jitter Test Result

The 1394TA, based on real world experience, allows for a reallocation of the transmitter jitter and skew

budgets. This specification defines the new budget. The IEEE-1394-2008 budget is still valid and devices

meeting this requirement are eligible for the logo. To better reflect implementations the 1394TA

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reallocation gives budget to transmitter jitter and takes budget from skew at S400. Devices shall meet either

the IEEE-1394-2008 or 1394TA requirement for both jitter and skew.

Parameter Description IEEE

Max

1394TA

Max

Units

S100 Tx Jitter 800 800 ps



Port Measured Units

Port 0 (IUT Max Speed)

TPAto TPA

Tx Jitter

TPA rising to TPA falling

Transmit Jitter

ps


TPBto TPB

Tx Jitter

TPB rising to TPB falling

Transmit Jitter

ps

Port n

4.3.3.2 DS Transmit Skew Test Result

The 1394TA, based on real world experience, allows for a reallocation of the transmitter jitter and skew

budgets. This specification defines the new budget. The IEEE-1394-2008 budget is still valid and devices

meeting this requirement are eligible for the logo. To better reflect implementations the 1394TA

reallocation, gives budget from transmitter skew and gives budget to jitter. Devices must meet either the

IEEE-1394-2008 or 1394TA requirement for both jitter and skew.

Parameter Description IEEE

Max

1394TA

Max

Units

S100 Tx Skew 400 400 ps

S200 Tx Skew 250 250 ps

S400 Tx Skew 200 100 ps

Port Measured Units


TPA to TPB

Tx Skew

TPA rising to TPB rising

Transmit Skew

ps


TPA to TPB

Tx Skew

TPA rising to TPB falling

Transmit Skew

ps


TPA to TPB

Tx Skew

TPA falling to TPB rising

Transmit Skew

ps


TPA to TPB

Tx Skew

TPA falling to TPB falling

Transmit Skew

ps

1394 TA 2002005 Revision 2.3


4.3.3.3 DS Transmit Rise/Fal l t ime Test Result


S100 Tx 10-90% Rise/Fall 3.2 ns



Port Measured Units


TPA rising

TPA 10-90% Rise time ns


TPA falling

TPA 10-90% Fall time ns


TPB rising

TPB 10-90% Rise time ns


TPB falling

TPB 10-90% Fall time ns

Repeat for all ports.

4.3.3.4 DS Differential Ampli tude Test Result


S100 Tx Differential Amp 172 mV



Port Measured Units


TPA 1

TPA Differential Amplitude

(TPA+ > TPA-)

mV


TPA 0

TPA Differential Amplitude

(TPA- > TPA+)

mV


TPB 1

TPB Differential Amplitude

(TPB+ > TPB-)

mV


TPB 0

TPB Differential Amplitude

(TPB- > TPB+)

mV

Repeat for all ports

4.3.4 Preferred DS Transmit Signal Integrity Test Method

The preferred DS Transmit Signal Integrity Test Method brings the advantages of the Beta Transmit Signal

Integrity test method to DS testing. The advantages include:

- More ideal test load, as specified in the IEEE-1394 standard

- One capture per speed for all parameters being measured

- Simpler oscilloscope interaction (less automation is required)

- Faster acquisition of test results

- Less requirements for single port devices

Similar to the legacy methods, this method uses an oscilloscope to capture the waveforms however because

the new method post processes the waveform only one acquisition is required per speed. Once the

waveform is captured the data points are placed into Excel for processing.

General Test Flow

1. Connect QP-SSIB-TF (test fixture) to the IUT

2. Connect QP-SSIB (test controller) to the QP-SSIB-TF using a short RJ45 patch cable

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3. Connect the QP-SSIB to the PC running the QP-SIA-SSIB application

4. If the IUT has more than one port connect the port not being tested to the QP-SSIB responder port

otherwise if the the IUT is a single port devices it must be configure to accept write and read block

requests to IEEE-1394 memory location 0xFFFF 0xF0010000 at all supported speeds.

5. IUT or responder node is made root. Transmission of Cycle Starts packets are turns off

6. The 64 byte data pattern is written is written to the memory location listed above, First 48 bytes =

0x33, bytes 49-56 = 0x55, bytes 57-64 = 0xFF to either the IUT or responding node

7. Set the Oscilloscope to trigger on the combination of IUT’s data prefix and the Trigger output

from the QP-SSIB test controller

8. After the QP-SSIB is armed, the QP-SIA-SSIB application performs a Read Request from either

the IUT or the Responder node. When the QP-SSIB test controller sees the acknowledge for the

read, it opens the TPA and TPB switches located on the QP-SSIB-TF test fixtures.

9. The read response triggers the scope and the packet is captured

10. The QP-SIA-SSIB application load the capture data into Excel and starts the necessary macros to

process the data and return the results

4.3.5 Legacy DS Transmit Signal Integrity Test Methods

4.3.5.1 Legacy DS Transmit Jitter

Transmit jitter is very important in determining a good board design and layout. It can be used to determine

poor grounding, board noise issues etc. Note: this test is not designed to do a detailed test of the PHY’s

transmit jitter; that should be done in a controlled environment with optimized data patterns. Testing of this

type should have been completed by the PHY manufacturer or 3rd

party test facility. The jitter tests defined

in this section are designed to measure the transmit jitter with as little control over the device under test as

possible. This is done to accommodate the many 1394 devices that only have one port, which precludes the

repeating of data. Single port devices are recommended to have the test mode capability to transmit the data

patterns described in this section. If the single port device cannot transmit suitable data patterns for testing,

these tests are optional.

When measuring transmit jitter the PHY must transmit a data pattern whereby TPA and TPB provide

transitions on consecutive bit cells. For devices with a single port the local node must provide the stimulus.

Devices having two or more ports, an external node may be used to provide the stimulus to the

Implementation Under Test (IUT). In either case, ideally the data pattern, when looked at repetitively

(infinite persistence), should provide a rising or falling transition and on the following bit cell the opposite

transition. For example, when measuring TPA↑ to TPA↓ a 0xFFFFFFFF pattern on data provides TPA with

a consistent rising transition then on the next bit cell a falling transition (see Figure 16). When measuring

TPB↓ to TPB↑ a 0xAAAAAAAA pattern on data provides TPB with a consistent falling transition while

on the next bit cell a rising transition (see Figure 17).

To increase the stability of the trigger, the node providing the stimulus should be the root node. In the

figure below, top picture, the IUT should be root and in the bottom picture the Stimulus Node should be

root.

1394 TA 2002005 Revision 2.3


Figure 14: Jitter, Skew, and Rise/Fall Time Test Topologies.

Jitter Measurement Basics:

IEE-1394-1995 does not provide explicit methods for measuring transmitter jitter. However, in order to

standardize the 1394 Trade Association‘s Compliance Logo process, this document provides the allowable

methods for making transmitter jitter measurements.

For all the measurement methods found in this document, the following concepts are used.

- Worst case transmitter margin for a given bit cell is:

o (Bit Cell Time – (Data Jitter + Strobe Jitter + Skew)) = Margin

- If a bit cell originates and ends on the same differential pair, the margin is:

o (Bit Cell Time – (Data Jitter + Strobe Jitter)) = Margin

- Within a given bit cell, jitter occurs on both leading and trailing edges.

- This jitter will cause the bit cell width to vary from a minimum value to a maximum value

(leading edge and trailing edges).

- The transmitter jitter parameter is an absolute (neither peak or peak-to-peak) parameter

measurement. It is a measure of how much the bit cell grows and shrinks relative to the PHY‘s

ideal bit cell time.

- The transmitter jitter parameter as specified by IEEE-1394 is one-fourth of the total variation of

the bit cell width.

The following picture represents the worst-case transmitter margin for a given bit cell at S400 using IEEE-

1394-1995 timing.

1394 TA 2002005 Revision 2.3

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Skew

200ps -

100ps

2.54 ns at S400

(One Bit Cell Time)

100ps -150ps

100ps -150ps

100ps -

150ps

100ps -

150ps

Mimimum Bit Cell at

Tx Connector =

2.54ns - 400ps = 2.14ns

Red Text - IEEE-1394 Standard

Black Text - 1394TA Specfication

Figure 15: Transmitter Bit Cell Margin at S400

4.3.5.2 Test Methods

This document defines two methods for measuring jitter. The first method is simple and can be done with

most oscilloscopes having appropriate bandwidth. The second method removes some opportunity for

human error by eliminating the subjectivity, and increases automation but requires an oscilloscope with a

statistics mode.

4.3.5.2.1 Connection Signal Integrity Board (SIB)

Connection from the Implementation Under Test (IUT) should be done through SIB426 or SIB626 or SIB926,

please see Figure 4 for details. This facilitates a very short electrical connection from the IUT and allows a

close representation of the output of the system board to be acquired by the oscilloscope.

Another IEEE-1394 node (sink node) must be connected to the IUT through the SIB. This connection is

made with a long 4.5-meter cable to connector CN1. The sink node must have proper termination. It will be

the receiver node while the IUT is transmitting. A long cable is recommended so that the reflections are

held off (delayed) for several (~40ns) nanoseconds. This allows a clean measurement of transmitted signals

at the very beginning of the packet, prior to the reflections from the sink node coming back to the IUT.

When connecting a Digital Sampling Oscilloscope (DSO) the following connections should be made using

differential probes to the signal pair header pins according to the table below. Note the polarity (+ / -)

indications next to the header pins. If required by the probe, be sure to use the proper ground lead to ground

the probe to the closest GND header pin.

1394 TA 2002005 Revision 2.3


DSO channel Signal Header Pin connection for:

4 pin DUT

Channel 1 TPA H1A

Channel 2 TPB H2A

Note: Duplicate signal pair header pins are provided on the bottom of SIB to allow both probes to be temporarily connected to the same signal pair. This is done to facilitate the de-skewing of the DSO probes. Since both probes are on the same signal, the channel skew can be adjusted until

both scope traces on aligned.

4.3.5.2.2 DS Jitter Measurement Method 1

This section defines the method used to measure transmit jitter from the triggered edge to the next rising or

falling edge of the same differential pair. While several data patterns are appropriate, this method assumes

a 0xFFFFFFFF pattern on data when measuring jitter on TPA and 0xAAAAAAAA pattern on data when

measuring jitter on TPB.

1) Connect IUT to SIB as described in section 4.3.5.2.1

2) Connect IUT to a stimulus node if needed, see Figure 14

3) Generate the appropriate data pattern for either TPA or TPB jitter measurement

4) Trigger the oscilloscope on the appropriate rising edge (TPA) or falling edge (TPB) at a threshold

of 0v differential (Figure 17).

5) Using infinite persistence measure the jitter of the trigger’s edge (Tjitter). The Trigger jitter is the

width of distribution of the trigger’s edge after at least 200 acquisitions by the oscilloscope. Many

oscilloscope acquire approximately 20 to 30 times a second.

6) Next, using infinite persistence measure the Next edge jitter of the next edge after the trigger edge.

Again, allow at least 200 acquisitions by the oscilloscope (Figure 16).

7) Calculate Transmit Jitter by subtracting the Trigger jitter from the Next edge jitter and dividing

that by 4.2

8) Repeat for both pairs (TPA and TPB).

9) Repeat for all ports.

2 The method of subtracting the Trigger jitter from the Next edge jitter doesn‘t eliminate the fact the both the leading

and trailing edges effect the bit cell time. In fact, the leading and trailing edge jitter are summed into the Next edge

jitter. Therefore, the total width of the Next edge jitter is the absolute jitter measurement and must be divided by 4.

1394 TA 2002005 Revision 2.3

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Trigger on Zero Crossing

of First Transition

Pre-trigger on

DATA_PREFIX

One Bit Cell

Time

Width of edge is

Trigger Jitter

Width of next edge is

Next Edge Jitter

Figure 16: Trigger and Next Edge Jitter measurement.


of First Transition

Pre-trigger on

DATA_PREFIX

One Bit Cell

Time

Measure Jitter of next

edge following trigger.

Measurement taken at

zero crossing

Figure 17: Trigger for Jitter Measurement.

4.3.5.2.3 DS Jitter Measurement Method 2

This section defines the method used to measure transmit jitter using the scope’s cycle time measurement

function in conjunction with the scope’s statistics mode. To make this measurement, trigger on the first

transition of data or strobe (data for 0xAAAAAAAA pattern and strobe for 0xFFFFFFFF pattern). While

1394 TA 2002005 Revision 2.3


several data patterns are appropriate, this method assumes a 0xFFFFFFFF pattern on data when measuring

jitter on TPA and 0xAAAAAAAA pattern on data when measuring jitter on TPB.



3) Generate the appropriate data pattern for either TPA or TPB jitter measurement

4) Trigger the oscilloscope on the appropriate rising edge (TPA) or falling edge (TPB) at a threshold

of 0v differential.

5) Using the scopes Pulse-width time measurement function, measure as many Pulse-widths as

possible before reflects effect the signal quality3.

6) Turn on the statistics mode to allow for tracking of Minimum width and Maximum width.

7) Let scope acquire at least 200 acquisitions.

8) Calculate the Transmit jitter by the following equation4:

Jitter = (Max Pulse-width time – Min Pulse-width time) / 4


4.3.5.3 DS Transmit Skew

Transmit skew is very important in determining a good board design and layout. It can be used to determine

trace length, and board loading issues. Note: this test is not designed to do a detailed test of the PHY’s

transmit skew. That should be done in a controlled environment with optimized data patterns. Testing of

this type should have been completed by the PHY manufacturer or 3rd

party test facility. The skew tests

defined in this section are designed to measure transmit skew with as little control over the IUT as possible.

This is to accommodate the many 1394 devices that only have one port, which precludes the repeating of

data. Single port devices are recommended to have the test mode capability to transmit the data patterns

described in this section. If the single port device cannot transmit suitable data patterns for testing, these

tests are optional.

The following four combinations are measured:

- TPA↑ to TPB↑

- TPA↑ to TPB↓

- TPA↓ to TPB↑

- TPA↓ to TPB↓

4.3.5.3.1 Equipment Special ized

When measuring transmit skew the PHY must transmit a data pattern whereby TPA and TPB provide all

transitions listed above. For implementations with a single port PHY device, the local node must provide

the stimulus. Implementations having two or more ports, an external node can be used to provide the

stimulus to the Implementation Under Test (IUT).

4.3.5.3.2 Test Methods

This document defines two methods for measuring skew. The first method is simple and can be done with

most oscilloscopes having appropriate bandwidth. The second method removes some opportunity for

human error by eliminating the subjectivity, and increases automation but requires an oscilloscope with a

statistics mode.

4.3.5.3.2.1 DS Skew Measurement Method 1

3 Note, the measurement method used is independent of the trigger; therefore, the trigger jitter is not part of this

equation. 4 This method requires a divide by 4 because the positive and negative jitter of both the leading and trailing edges are

included in the measurement.

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This section defines the method used to measure transmit skew using the scope and manual measurements

of overlaid waveforms. The objective is to place both a rising and falling edge of TPB on the same cell

boundary as a rising edge of TPA. This will allow us to measure the following skews:

- TPA↑ to TPB↑

- TPA↑ to TPB↓

This is accomplished by alternating between three different patterns such that all are overlaid on the scope

via infinite persistence. The patterns are:

0x3CCCCCCC (TPA↑)

0x29999999 (TPB↑)

0x26666666 (TPB↓)

Next we want to place both a rising and falling edge of TPB on the same cell boundary as a falling edge of

TPA. This will allow us to measure the following skews:

- TPA↓ to TPB↑

- TPA↓ to TPB↓

This is accomplished by alternating between three different patterns such that all are overlaid on the scope

via infinite persistence. The patterns are:

0x33333333 (TPA↓)

0x29999999 (TPB↑)

0x26666666 (TPB↓)

1) Connect IUT to SIB as described in section 4.3.5.2.1 (use long cable)


3) Generate the appropriate 3 data patterns for the skew measurement as described above.

4) De-skew the scope channels and probes as recommended by the scope manufacturer.

5) Zero out any DC offset between the scope channels and probes as recommended by the

manufacturer.

6) Trigger the scope on the falling edge of TPB at a 0v differential threshold (Figure 18).

7) With infinite persistence turned on, make at least 200 acquisitions for each data pattern type.

8) Zoom in on the transitions that occur 7 cell periods from the trigger edge (falling edge of TPB).

This is necessary as the patterns are designed to provide a constant time between

transitions before and after the cell boundary of cell 7 and cell 8. This is to eliminate the

affect of Inter-symbol interference (ISI) (Figure 19).

9) Make the skew measurement between TPA rising and TPB rising, see Figure 20 and Figure 21.

(When measuring skew it is impossible to eliminate the effects of jitter; therefore the

average point within the jitter, on the zero crossing, is used. To increase the stability of

the trigger, make sure the source of the data pattern is root.)

10) Make the skew measurement between TPA rising and TPB falling, see Figure 20 and Figure 21.




11) Repeat for TPA falling to TPB rising/falling measures with the appropriate 3 data patterns.


1394 TA 2002005 Revision 2.3



of First Transition

Pre-trigger on

DATA_PREFIX

Greater Than 140ns

TPB = Data

TPA = Strobe

All data patterns used

have this transition

Figure 18: Skew Measurement Trigger.

1394 TA 2002005 Revision 2.3

30



of First Transition

Pre-trigger on

DATA_PREFIX

TPB = Data

TPA = Strobe

0 0 1 1 1 1 1 10 0 0 0

0x3CCCCCCC

1 2 3 4 5 6 7 8 9 10

Zero Crossing of TPA

Rising Edge

Low for 2 Bit Cells

High for 2 Bit Cells

Figure 19: Skew Measurement Bit Location


of First Transition

Pre-trigger on

DATA_PREFIX

TPB = Data

TPA = Strobe

0x3CCCCCCC + 0x29999999 + 0x26666666

1 2 3 4 5 6 7 8 9 10

Zero Crossing of TPA

Rising Edge

Low or High for 2 Bit Cells

Low or High for 2 Bit Cells

Figure 20: Skew Measurement with Three Signal Traces.

1394 TA 2002005 Revision 2.3


TPA Rising

TPB Rising

TPB Falling

TPA Rising to TPB RisingTPA Rising to TPB Falling

Figure 21: Skew Measurement Detailed View

4.3.5.3.2.2 DS Skew Measurement Method 2

Skew measurement method 2 is very similar to method 1 however the scopes must be capable of measuring

the amount of time from trigger to a specified edge (the bit cell boundary between bit cell 7 and 8) in

multiple packets. The scope must then calculate the average time over multiple packets.

The objective is to place both a rising and falling edge of TPB on the same cell boundary as a rising edge of

TPA. This will allow us to measure the following skews:

- TPA↑ to TPB↑

- TPA↑ to TPB↓

- TPA↓ to TPB↑

- TPA↓ to TPB↓

This is accomplished by alternating between four different patterns such that all edge combinations occur

on the transition between the 7th

and 8th

bit cells. The patterns are:

0x3CCCCCCC (TPA↑)

0x29999999 (TPB↑)

0x26666666 (TPB↓)

0x33333333 (TPA↓)





manufacturer.

5) Trigger the scope on the falling edge of TPB at a 0v differential threshold (Figure 18)

1394 TA 2002005 Revision 2.3

32


6) Generate the appropriate data pattern as described above

7) Let the scope acquire at least 200 acquisitions for each data pattern type.

8) Have the scope measure the average time from the trigger to the transition of the edge that occurs

between the 7th

and 8th

bit cell time.




9) Record the measurement taken in step 8).

10) Repeat steps 8) and 9) for all data patterns.

11) TPA↑ to TPB↑ skew is the difference in time recorded for data patterns 0x3CCCCCCC and

0x29999999

12) TPA↑ to TPB↓ skew is the difference in time recorded for data patterns 0x3CCCCCCC and 0x26666666

13) TPA↓ to TPB↑ skew is the difference in time recorded for data patterns 0x33333333 and

0x29999999

14) TPA↓ to TPB↓ skew is the difference in time recorded for data patterns 0x33333333 and

0x26666666


4.3.5.4 DS Transmit Rise/Fal l t ime

Transmit Rise/Fall time is very important in determining a good board design and layout. It can be used to

determine excessive trace length and capacitive loading issues. Note: this test is not designed to do a

detailed test of the PHY’s transmit Rise/Fall time. That should be done in a controlled environment with

optimized data patterns. Testing of this type should have been completed by the PHY manufacturer or 3rd

party test facility. The Rise/Fall time tests defined in this section are designed to measure transmit Rise/Fall

with as little control over the IUT as possible. This is done to accommodate the many 1394 devices that

only have one port, which precludes the repeating of data. Single port devices are recommended to have the

test mode capability to transmit the data patterns described in this section. If the single port device cannot

transmit suitable data patterns for testing, these tests are optional.

The Rise and Fall times are measured from the 10 to 90 percent of mean amplitude. This eliminates

measurement variation due to differences in overshoot, which may differ based on cable length and other

loading factors.


When measuring transmit Rise/Fall times, the transmit pattern may make it difficult to determine the rise

and fall time independent of overshoot. Therefore a 0x33333333 pattern is recommended for this

measurement. When measuring Rise/Fall time cable length is important. Longer cables increase loading,

therefore slowing edges. However, the longer round trip delay allows the measurements to be taken before

reflections affect them. Shorter cables reduce loading, therefore allow the transmitter to drive the edges

faster. However, if to short or if the length is such that reflects fall on transitions, this may affect the rise/fall

time measurement. In general, a long cable (4.5 meters) can be used however; if a failure occurs the test

should be redone using a short cable (2 meters or less). If no failures occur the test passes.

The Rise and Fall time shall be measured for both TPA and TPB. The pattern of 0x33333333 provides

symmetrical transitions on both pairs, for the purpose of the Rise/Fall measurements.

For implementations with a single port PHY device, the local node must provide the stimulus.

Implementations having two or more ports, an external node can be used to provide the stimulus to the

Implementation Under Test (IUT).

1394 TA 2002005 Revision 2.3


4.3.5.4.2 Test Method

This document defines one method for measuring Rise/Fall time. This method is simple and can be done

with most oscilloscopes having appropriate bandwidth and amplitude measurement function.

4.3.5.4.2.1 DS Rise/Fall t ime Measurement Method

This section defines the method used to measure transmit Rise/Fall using the scope‘s amplitude

measurements function. The objective is to measure the mean amplitude, then determine the 10-90%

threshold crossing points. The Rise or Fall time is the time between the 10 and 90 percent crossings.

1) Connect IUT to SIB as described in section 4.3.5.2.1.


3) Generate the appropriate data pattern for the Rise/Fall measurement as described above.



manufacturer.

6) Trigger the scope on the falling edge of TPB at a 0v differential threshold.

7) Zoom in on the transition of interest (rising or falling edge of TPA or TPB)

8) Make the 10-90% rise/fall time measurement, see Figure 22.

9) Repeat for both Rising and Falling edges.

10) Repeat for both TPA and TPB.


Mean

Amplitude80% of Amplitude

Rise Time (10% to 90%)

Figure 22: Rise / Fall Time Measurement on Scope

1394 TA 2002005 Revision 2.3

34


4.3.5.5 DS Differential Ampli tude

Differential Amplitude is very important in determining a good board design and layout. It can be used to

determine excessive trace length and capacitive loading issues and reflections. Note: this test is not

designed to do a detailed test of the PHY’s transmit Differential Amplitude. That should be done in a

controlled environment with optimized data patterns. Testing of this type should have been completed by

the PHY manufacturer or 3rd

party test facility. The Differential Amplitude tests defined in this section are

designed to measure transmit Differential Amplitude with as little control over the IUT as possible. This is

done to accommodate the many 1394 devices that only have one port, which precludes the repeating of

data. Single port devices are recommended to have the test mode capability to transmit the data patterns

described in this section. If the single port device cannot transmit suitable data patterns for testing, these

tests are optional.

The Differential Amplitude is measured as the minimum amplitude measured over at least 200 acquisitions.


When measuring transmit Differential Amplitude, the transmit pattern may make it difficult to determine

the amplitude independent of overshoot. Therefore a 0x33333333 pattern is recommended for this

measurement. When measuring Differential Amplitude cable length is important. Longer cables increase

loading, therefore slowing edges and reducing amplitude. However, the longer round trip delay allows the

measurements to be taken before reflections affect them. Shorter cables reduce loading, therefore allow the

transmitter to drive the edges faster. If to short or if the length is such that reflects fall on transitions, this may

also affect the amplitude measurement. In general, a long cable (4.5 meters) can be used; however, if a

failure occurs the test should be redone using a short cable (2 meters or less). If no failures occur the test

passes.

The Differential Amplitude of 1 and 0 shall be measured for both TPA and TPB. The pattern of

0x33333333 provides symmetrical transitions on both pairs, for the purpose of the amplitude measurement.

For implementations with a single port PHY device, the local node must provide the stimulus.

Implementations having two or more ports, an external node can be used to provide the stimulus to the

Implementation Under Test (IUT).

4.3.5.5.1.1 Test Method

This document defines one method for measuring Differential Amplitude. This method is simple and can

be done with most oscilloscopes having appropriate bandwidth and amplitude measurement function.

4.3.5.5.1.2 DS Different ial Ampli tude Measurement Method

This section defines the method used to measure transmit amplitude using the scope‘s amplitude

measurements function. The objective is to measure the minimum amplitude over at least 200 acquisitions,



3) Generate the appropriate data pattern for the Differential Amplitude measurement as

described above.



manufacturer.

6) Trigger the scope on the falling edge of TPB at a 0v differential threshold.

1394 TA 2002005 Revision 2.3


7) Zoom in on the transition of interest (1 and 0 level of TPA and TPB)

8) Make Differential Amplitude measurement for both 0 and 1 states,

9) Repeat for both TPA and TPB.


4.4 Beta Testing

This specification defines beta transmit signal integrity at test points:

- TP2 for the Near End test and

- TP3 for the Far End test

The test fixtures used to make both the Near End and Far End measures provide a Receiver Network. For

both the Near and Far End tests, the receiver network, as defined in Figure 24 and Figure 33 respectfully,

along with oscilloscope probes only deteriorate the signal therefore the system implementer may consider

the measurement worst case.

This specification also defines a beta receiver sensitivity test. The tester is calibrated using the Far End test

methodology. The measurement points for the tests are shown below.

Figure 23: Measurement points (half connection is shown)

The tests parameters defined in this section are defined in IEEE-1394-2008 unless otherwise specified by

this document.

4.4.1 Beta Transmit Near End Test

The following test procedure describes two oscilloscope configurations: a) two differential probes

configuration b) one differential probe and two single-ended probe configuration.

1394 TA 2002005 Revision 2.3

36


Figure 24 - Balanced Transmitter Test Circuit

4.4.1.1 Test Topology

The following topology is used for all near end transmitter tests. The specific probe connections will be

described later in this section. The near end transmit test topology is done at TP2.

QP-SQT Oscilloscope

Test Fixture DUT

Trigger

GPIB/Ethernet

ProbesTones to make

connection8B10B Signal

Figure 25: Test Topology

4.4.1.2 Connections

The PC running QP-SQT must have a GPIB/Ethernet or equivalent connection to the oscilloscope (scope).

The PC also connects through IEEE-1394 to the “To Host PC” connection of QP-SQT or QP-SIGKit4B

Rev.C. This is a real 1394 connection however this should be a point to point connection between the PC

running QP-SIB4B Rev. C or QP-SQT.

The TX Test Fixture Connector connects the QP-SQT or QP-SIGKit4B Rev. C to the test QP-SIB4B-TF.

1394 TA 2002005 Revision 2.3


All probes connect to QP-SIB4B-TF. Please see the following sections for details. QP-SIB4B-TF also

connects directly to the device under test.

4.4.1.3 Trigger

QP-SIGKit4B Rev. C and QP-SQT enable a low cost non-disruptive trigger. For all tests, connect the

“Auxiliary In” trigger (Aux In) of the oscilloscope to the trigger out located on the back of the unit. The

trigger has low bandwidth requirements therefore a low bandwidth probe or passive connection maybe

used. The trigger is created by QP-SIGKit4B Rev. C or QP-SQT and starts the capture approximately 4 ms

after the start of 8B10B data.

Figure 26: Trigger Connection

4.4.1.4 Digital Sampling Scope Connect ion

When connecting a Digital Sampling Oscilloscope (DSO or scope) the following connections should be

made using listed probe types to the signal pair header pins according to the tables below. Note the polarity

(+ / -) is indicated next to the header pins. When using single ended probes make sure to use the proper

ground lead to ground the probe to the closest GND header pin.

Figure 27: Acquire Diff Probe Connection

1394 TA 2002005 Revision 2.3

38


Two Differential Probe Configuration

DSO channel Probe

type

Test Connection

Channel 1 Diff Cal

Diff

TP2G to +

TP2G to -

Channel 1 Diff Acquire

Diff

TP1+ to +

TP1 - to -


SE1

TP1+ to +

TP2G to -


SE1

TP1- to +

TP2G to -


SE2

TP1- to +

TP2G to -


SE2

TP1+ to +

TP2G to -

Table 5: Two Differential Probe Configuration

Figure 28: Acquire SEn Connection with two Single Ended Probes

Figure 29: Acquire SEn with two Differential Probes

1394 TA 2002005 Revision 2.3


One Differential and Two Single End Probe

Configuration

DSO

channel

Probe

type

Test Connection

Channel 1 Diff Cal Diff TP2G to +

TP2G to -


Diff

TP1+ to +

TP2 - to -

Channel 3 Single Acquire

SE1

TP1 +

TP2 G to G


SE1

TP1 –

TP2 G to G


SE1

TP1 -

TP2 G to G


SE1

TP1 +

TP2 G to G

Table 6: One Diff and Two SE Probe Connection

4.4.1.5 Test Procedure

4.4.1.5.1 Differential Measurement

This is an automated process. Please follow the instructions provided with the tool used to make the

measurement.

4.4.1.5.2 Single Ended Measurement

This is an automated process. Please follow the instructions provided with the tool used to make the

measurement.

4.4.1.6 Beta Transmit Test Specif icat ion and Methodology

This section defines both the Near and Far End specification requirements and test methodology. The

measurement methodology used requires a oscilloscope sample rate such that between the 10% and 90%

points of each edge has at least 2 samples. At this sample rate the oscilloscope must be able to acquire at

least 3500 + 10% complete UIs.

4.4.1.6.1 Near End Baud Rate

The baud rate is calculated from all the edge times in the 3500 UI differential sample stream.

First a calibrated zero value is set by capturing a sample with both leads of the differential probe connected

to ground. If calibration is not performed for a given run, the previous calibration result is used. If

calibration has not been performed for any run, 0 Volts is used. Edge times in the sample stream are

calculated by interpolating the two samples on either side of the calibrated zero level for each zero

crossing.

1394 TA 2002005 Revision 2.3

40


The UI period is calculated by fitting a least sum of squares line to all the calculated edges and their

corresponding UI number. The slope of that line is the UI period. The inverse of the calculated UI period

yields the baud rate.

Parameter Limits

Baud rate (S400b) < 491.470 MBd and > 491.569 MBd



4.4.1.6.2 Near End Differential Amplitude

IEEE-1394b requires K28.5 characters to measure differential amplitude presumably to allow isolation of a

steady state level during the 5 UI pulse. Since K28.5 characters are relatively rare in the short captured

stream, all pulses of 4 or 5 UI are used to calculate amplitude.

Capture samples of all 3500 UI are scanned to identify runs of samples above or below the calibrated zero

for more than 3.5 UIs. To reduce the impact of overshoot, undershoot, reflections, and launch points only

the samples from the 3rd

UI of these pulses are averaged to produce the amplitude of that pulse. Then all

positive pulse averages are averaged for the 1 differential amplitude and negative pulse averages are

averaged for the 0 differential amplitude.

Parameter IEEE-1394b Limits

1 differential amplitude (S400b) <= 800 mV and >= 300/475 mV (Note A)

0 differential amplitude (S400b) >= -800 mV and <= -300/475 mV (Note A)

1 differential amplitude (S800b) <= 800 mV and >= 350/600 mV (Note A)

0 differential amplitude (S800b) >= -800 mV and <= -350/-600 mV (Note A)

1 differential amplitude (S1600b) >= 800 mV and >= 555 mV

0 differential amplitude (S1600b) >= -800 mV and >= -555 mV

Note A: 300mV and 350mV are the minimum requirement, but new designs are recommended to have a

minimum differential amplitude of 475mV and 600mV at S400β and S800β respectfully.

4.4.1.6.3 Near End Rise / Fal l T imes

Rise / fall times are measured on select edges in the 3500 UI differential sample stream. To emulate the

IEEE-1394b requirement to use a D21.5 character stream for rise / fall measurements only edges following

two single UI pulses and preceding another single UI pulse are analyzed for rise / fall times.

The 90% and 10% levels are calculated from the previously described differential amplitude measurements.

The min and max samples between the 90% and 10% levels around each of qualifying edges are

interpolated out to the 90% and 10% levels to estimate rise and fall time.

If the samples do not reach 10% or 90% within 0.5 UI of the edge, the edge is ignored for rise / fall

purposes (level failures will be caught in the eye diagram tests.)

1394 TA 2002005 Revision 2.3


Parameter Limits

Rise 10-90% (S400b) <= 400 ps and >= 80 ps

Fall 10-90% (S400b) <= 400 ps and >= 80 ps

Rise 10-90% (S800b) <= 350 ps and >= 80 ps

Fall 10-90% (S800b) <= 350 ps and >= 80 ps

Rise 10-90% (S1600b) <= 175 ps and >= 80 ps

Fall 10-90% (S1600b) <= 175 ps and >= 80 ps

4.4.1.6.4 Near End Eye Validat ion

Transmit eye validation is performed on the samples in the center 250 UIs of the 3500 UI differential

sample stream.

An ideal clock is constructed from the UI period calculated for the baud rate measurement and the intercept

(phase) from the least sum of squares calculation. All samples times are adjusted by subtracting the time of

their preceding ideal clock edge. Then all samples are evaluated against the absolute and relative eye

requirements of this document.

The IEEE-1394-2008 eye mask restricts the maximum amplitude to a level that is often violated by silicon

shipping at the time this specification was written. It is the understanding of the 1394 Trade Association

that the maximum amplitude levels were set to protect future silicon that may implement low voltage

tolerant inputs. It is the observation of the 1394 Trade Association that currently no 1394 implementations

will be adversely affected by raising the maximum absolute eye mask level from 800mV to 1000mV so

long as the near end differential amplitude as defined in section 4.4.1.6.2 does not exceed 800mV. In

addition, the maximum normalized eye mask which permits 0 violations will permit 20% of the total

acquisitions to be in violation. NOTE: future PHY silicon designs should take this change into account.

This test verifies to both the IEEE-1394-2008 and newly defined maximums defined by this specification.

The samples are plotted with their adjusted times (0 to 1 UI) and their voltage levels. Samples incurring

the eye or exceeding maximums are highlighted.

Parameter IEEE1394-2008 Limit 1394TA Limit

Absolute Eye diagram violating samples 0 0

Normalized Eye diagram violating samples 0 20% of total

1394 TA 2002005 Revision 2.3

42


800 mV

-800 mV

0 mV

+Vmin

-Vmin

X1 X2 1-X2 1-X10 1

Normalized time (% of unit internval)

1000 mVSo long as the near end differential amplitude is less than 800mV

-1000 mVSo long as the near end differential amplitude is less than -800mV

IEEE-1394-2008 specific text

Base 1394 Test Suite Definition specific text

Figure 30: Absolute eye diagram mask at TP2

Some Violations Permitted

Some Violations Permitted1.1

-0.1

0.5

0.8

0.2

X1 X2 1-X2 1-X10 1

Normalized time (% of unit internval)

Norm

aliz

ed a

mp

litude

1.0

0

Base 1394 Test Suite Definition specific text

Figure 31: Normalized eye diagram mask at TP2

1394 TA 2002005 Revision 2.3


Figure 32: Sample near end eye diagram.

4.4.1.6.5 Near End Differential skew

The single ended probe captures are only used to calculate differential skew and common mode voltage.

A calibration pass should be run to account for timing differences in oscilloscope channels or probes. The

calibration run is exactly the same as the measurement acquisition except both probes are connected to the

same signal. Any skew detected on this capture is assumed to be a test system constant. If calibration is

not run at all, system skew is assumed to be 0. If calibration is not run for a given run, port, or speed, the

most recent calibration results are used.

Single ended samples are captured first with a zero offset using a relatively low vertical resolution. Then

the common mode voltage is calculated and the signals are captured again offset by the common mode

voltage and at higher vertical resolution.

High and low amplitudes are calculated similar to the differential amplitudes. The resulting amplitudes are

then used to find the normalized 50% crossover point.

Edge times for both channels are calculated similar to the differential sample edge times except the 50%

crossover point is used instead of the calibrated zero volt level.

Near End Eye Diagram

Time

Am

plitu

de (

mV

)

Samples

Normalized Incursions

Normalized Eye

Absolute Eye

Calculated Levels

1394 TA 2002005 Revision 2.3

44


The edge times for the two channels are compared and the average difference minus any calibrated skew is

reported as the differential skew.

Parameter Limit

Differential skew (S400b) <= 50 ps



4.4.1.6.6 Near End Common mode voltage

While capturing the single ended samples, an average of one channel across many pulses is calculated to

yield the common mode voltage.

Parameter Limits

Common mode voltage <= 2.415 V

4.4.1.6.7 Near and Far End Jit ter Measurement Methodology

Jitter is only calculated for edges in the center 250 UI of the 3500 UI sample. The calculated clock from

the eye validation is compared to the edge times from the baud rate calculation. The jitter for each edge is

calculated by subtracting the calculated clock time from the calculated edge time.

4.4.1.6.7.1 Measured Total Jit ter

The maximum minus the minimum of all the calculated edge jitters represents the peak to peak total jitter

(TJpp).

If the measured total TJpp is greater than the total jitter allowance value listed in this document, then the

port under test fails the jitter test.

Note: Meeting the TJpp limit is not sufficient to pass the test because the sample size is not sufficient

to ensure statistical validity of random jitter.

4.4.1.6.7.2 Calculated Determinist ic J it ter

The jitter value of each edge is analyzed to quantify effects of various deterministic jitter sources.

To ensure edge type jitter correlation is not double counted, the affect of each deterministic jitter category

is removed from each edge before calculating the remaining deterministic jitter categories.

4.4.1.6.7.2.1 Edge type rising vs. falling

First, estimate edge type deterministic jitter. Average the jitters of all the rising edges in the center 250 UIs

of the stream. This is the rising edge deterministic jitter. Likewise, average the falling edge jitters to

estimate the falling edge deterministic jitter. The lowest average jitter value is subtracted from the highest

to provide DJedge type.

4.4.1.6.7.2.2 Pulse duration (T state)

Next, the edges are sorted by the number of preceding UIs of the same logic level (1, 2, and 3-5). Logic

high runs and logic low runs are combined because edge type differences were accounted for in the edge

type calculations above. The jitters are averaged for each of these run length categories separately. The

lowest of the averages is subtracted from the highest to provide DJrun length.

1394 TA 2002005 Revision 2.3


4.4.1.6.7.2.3 Running disparity

The running disparity for the edges in the stream is calculated, and the edges are grouped by the running

disparity at each edge (>2, 1, 0, -1, <-2). Averaging these groups provides the deterministic jitter of each

group. The lowest average is subtracted from the highest to provide DJrunning disparity.

4.4.1.6.7.2.4 Sinusoidal jitter patterns

The remaining jitter samples are processed by a modified Discrete Fourier Transform that accounts for the

irregular sample spacing of the jitter samples. The largest magnitude sample in the frequency domain

optimized for frequency, phase and magnitude and labeled DJfrequency 1.

With DJfreqency 1 removed from the jitter samples, the same process is run again to isolate DJfrequency 2.

4.4.1.6.7.2.5 Sum of deterministic jitter

DJpp = DJedge typepp + DJrun lengthpp + DJrunning disparitypp + DJfrequency 1pp + DJfrequency 2pp

If the calculated sum of Deterministic jitter is greater than the DJpp allowance value listed in this

document, then the port under test fails the jitter test.

Note: Meeting the DJpp limit is not sufficient to pass the test because unmeasured sources of

deterministic jitter may be present.

4.4.1.6.7.3 Random Jit ter

After subtracting all the deterministic jitter categories from each corresponding edge, the remaining edge

jitters are considered random. An RMS calculation to provides the estimate of random jitter (RJrms).

The RJrms limits are informative in IEEE-1394-2008 so exceeding the limit is not considered a failure. RJrms

is calculated for use in statistically estimating TJpp in the next section.

4.4.1.6.7.4 Calculated Total Jit ter

The calculated TJpp equals DJpp + (RJrms * 14). This provides the statistical worst-case peak-to-peak jitter

for 10-12

UI.

Note: Exceeding the TJpp limit is not sufficient to fail the test because unmeasured sources of

deterministic jitter may still be present in the random jitter estimate.

4.4.1.6.8 Near End Jitter Measurements

The following near end jitter measurements are required for all IEEE-1394-2008 enabled devices wanting

to pass the Base 1394 Test Suite Definition.

4.4.1.6.8.1 Near End Determinist ic Jit ter

Parameter Limits

Calculated Deterministic Jitter S400b < 244 ps



1394 TA 2002005 Revision 2.3

46


4.4.1.6.8.2 Near End Random Jit ter

Parameter Limits

Calculated Random Jitter (RMS) S400b < 22.38 ps


Calculated Random Jitter (RMS) S1600B < 4.00 ps

4.4.1.6.8.3 Near End Total J it ter

Parameter Limit

Calculated Total Jitter (peak to peak) S400b < 557 ps



4.4.2 Beta Transmit Far End Test

The beta transmit far end test includes the cable network into the system under test. This should aid system

implementers in selecting the appropriate cables. This test is optional for devices having a compliant IEEE-

1394 receptacle (such as the 4, 6, or 9 pin receptacle). This test is mandatory for devices not having a

compliant IEEE-1394 receptacle and therefore requires a non-standard cable.

The procedure and methodology are identical to the Near End test, only the test topology and parameters

have changed therefore this section only defines the new test topology and parameters.

1394 TA 2002005 Revision 2.3


Figure 33: Received Load Equivalent Circuit

4.4.2.1 Test Topology

The following topology is used for all far end transmitter tests. The far end transmit test point is at TP3

with idealized RC termination and oscilloscope probe test points and no PHY silicon. The actual system

implementation from TP3 to TP4 will vary.

1394 TA 2002005 Revision 2.3

48


QP-SQT Oscilloscope

Test Fixture DUT

Trigger

GPIB/Ethernet

ProbesTones to make

connection8B10B Signal

DUT’s Cable

Figure 34: Far End Signal Integrity Test Topology.

4.4.2.2 Far End Baud rate

Parameter Limits




4.4.2.3 Far End Differential amplitude

Parameter Limits

1 differential amplitude (S400b) >= 200 mV

0 differential amplitude (S400b) <= -200 mV


0 differential amplitude (S800b) <= -200 mV


0 differential amplitude (S1600b) >= -200 mV

4.4.2.4 Far End Eye Validat ion

Transmit eye validation is performed on the samples in the center 250 UIs of the 3500 UI differential

sample stream.

An ideal clock is constructed from the UI period calculated for the baud rate measurement and the intercept

(phase) from the least sum of squares calculation. All samples times are adjusted by subtracting the time of

their preceding ideal clock edge. Then all samples are evaluated against the absolute eye requirements of

IEEE-1394b.

The samples are plotted with their adjusted times (0 to 1 UI) and their voltage levels. Samples incurring

the eye or exceeding maximums are highlighted.

1394 TA 2002005 Revision 2.3


Parameter Limit

Absolute Eye diagram violating samples 0

Figure 35: Eye diagram mask at point TP3

Speed Symbol Value Units Equivalent ps from idealized

threshold

S400 X1 0.18 Unit Intervals (UI) 376

X2 0.38 Unit Intervals (UI) 783





Table 7: Normalized time intervals for TP3

1394 TA 2002005 Revision 2.3

50


Far End Eye Diagram

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

Time

Am

pli

tud

e (

mV

)

Samples

Absolute Eye STP_Receive_S400

Calculated Levels

Figure 36: Sample far end eye diagram.

4.4.2.5 Far End Differential skew

Parameter Limit

Differential skew (S400b) <= 5% of UI



4.4.2.6 Far End Common mode voltage

While capturing the single ended samples, an average of one channel across many pulses is calculated to

yield the common mode voltage.

Parameter Limits

Common mode voltage <= 2.915 V

1394 TA 2002005 Revision 2.3


4.4.2.7 Far End Jitter Measurements

4.4.2.7.1 Far End Determinist ic Jit ter

Parameter Limits




4.4.2.7.2 Far End Random Jitter

Parameter Limits



Calculated Random Jitter (RMS) S1600B < 4.00 ps

4.4.2.7.3 Far End Total Ji tter

Parameter Limit




4.4.3 Beta Receiver Test

Unlike Data/Strobe signaling which uses both differential pairs for transmit and receive, Beta signaling

uses TPB for transmit and TPA for receive. Given this characteristic, to verify the system it is necessary to

test both transmit and receive of the IUT.

This specification defines one method of stressing the receiver and two methods for calculating error rate.

Both methods are necessary as some PHY implementations do not correctly implement the IEEE-1394-

2008 defined port_Error register(s).

4.4.3.1 Receiver Sensit ivi ty

The receivers‘ ability to receive and recover a signal is stressed using a controlled output device to create a

valid IEEE-1394-2008 signal with minimum amplitude.

Note: The QP-SQT beta signal quality tester‘s output is AC-coupled. Some beta implementation may not

support being AC-coupled and may require external circuitry to enable this test.

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4.4.3.1.1 Minimum Amplitude

IEEE-1394-2008 for short haul copper specifies a minimum differential sensitivity of 200mV. The tester

shall provide a valid 8B10B stream with minimum amplitude at TP3. Calibration of the tester output shall

be done using the beta transmit amplitude test defined in this document with TP3 minimum amplitude

range of 200mV to 220mV.

4.4.3.1.2 Receiver Sensit ivi ty Test – Repeat Method

The Repeat Method may be used if the IUT has two or more ports. This method requires that the tester

provide the test data to one port (the port under test) of the IUT and receives the test data from another IUT

port. The tester shall then verify the test data sent with that received. With the tester‘s output calibrated as

define in this specification; the tester shall generate an adequate number of data bits in the packet payload

to verify with 90% confidence an error rate of 10-12

or less. If four (4) errors are detected before 90%

confidence is reached the test maybe terminated. The tester shall verify that all packets sent are received.

The tester shall verify the packet payload CRC for all packets.

Errors – the follow items constitute an error:

1) The number of packets sent is more than the packets received (one error for each packet)

2) The packet payload CRC fails (one error for each packet)

3) Unsolicited bus reset

4) Unsolicited disconnect (bit errors can cause the disconnect)

4.4.3.1.3 Receiver Sensit ivi ty Test – Port_error Method

The Port_error register is incremented when the port receives an INVALID codeword, unless the value is

already 255. The Beta PHY implements a Port_error register for each port, The Port_error register can be

found at address 0xC of the port page register.This register is cleared when read. All codewords (data

packet payload and non-data are verified). To maintain consistency with the repeat method5, with the

tester‘s output calibrated as define in this specification, the tester shall generate an adequate number of data

bits in the packet payload to verify with 90% confidence an error rate of 10-12

or less. If four (4) errors are

detected before 90% confidence is reached the test maybe terminated. At the start of the test the tester shall

read the Port_error register of the port under test (PUT) to clear its content. The tester shall periodically

read the PUT‘s Port_error register to verify the running error rate and to calculate the number of data bits

required to achieve the 90% confidence level.

Errors – the follow items constitute an error:

1) Port_error register increments (one error per increment)

2) Unsolicited bus reset

3) Unsolicited disconnect (bit errors can cause the disconnect)

5 It is expected that the tester will generate data packet utilizing approximately 90% or higher bus utilization therefore

using packet payload to determine the number bits transmitted only increases test time by 10% or less.

1394 TA 2002005 Revision 2.3


4.4.3.1.4 Error Rate Calculat ion

The bit error rate shall be calculated as follows:

Bits = Packet payload bits transmitted

Error Rate = Errors/Bits

90% confidence is achieved when:

n number of bits evaluatede number of errors detected

1210/1 error rate goal

np

1standard deviation of the sample proportion

nec / critical proprotion

p

cZ

critical Z-score

The standard normal cumulative distribution function at Z returns the probability

the device under test does not meet the error rate goal, the risk.

1-f(Z) yields the probability that the device under test meets the error rate goal,

the confindence.

4.5 Cable Power

The tests defined in this section utilize specifications defined by IEEE-1394-2008, and 1394 Trade

Association Power Specification Part1: Cable Power Distribution v1.0 unless otherwise noted.

4.5.1 Cable Power DC

The power class bits found in the self-ID packet specifies the cable power sinking/source requirements or

capability of a node. These power class bits are not always static and can change on subsequent bus resets

to reflect the devices current sinking/sourcing capabilities. As such, a device may be tested in more than

one role. Anytime a device changes its power class bits it shall initiate a bus reset to notify the power

management of the change in power class.

The Cable Power Distribution specification defines the following cable power configurations or types.

Device Type Condition (Note 1)

Power Type Description # of 6-pin or 9-pin connectors

Device Power is ON

Device Power is Off (with sufficient cable voltage to power PHY)

Device Power if Off (without sufficient cable voltage to power PHY)

1 Primary Power Provider 1 PC = 1,2,3 PHY is not active PHY is not active

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(PHY is always self powered) (Note 2)

2 PC = 1,2,3

Diode Isolation

PHY is not active

Diode Isolation

PHY is not active

Diode Isolation

3+ PC = 1,2,3

Diode Isolation

PHY is not active

Diode Isolation

PHY is not active

Diode Isolation

2 Primary Power Provider (PHY is powered by cable in power off state) (Note 3 and 4

1 PC = 1,2,3 PC=4 PHY is not active

2 PC = 1,2,3

Diode Isolation

PC = 4

repeat w/o limitation

PHY is not active

Diode Isolation or repeat w/o limitation

3+ PC = 1,2,3

Diode Isolation

PC = 4

repeat w/1.5 amp limiters

PHY is not active

Diode Isolation or repeat w/1.5 amp limiters

3 Alternate Power Provider (PHY is powered by cable in Power off state)

1 PC = 4 PC = 4 PHY is not active

2 PC = 4


PC = 4


PHY is not active


3+ PC = 4


PC = 4


PHY is not active

repeat w/ 1.5amp limiters

4 Self Powered (Cable power is never used)

1 PC = 0 PHY is not active PHY is not active

2 PC = 0

Isolation

PHY is not active

Isolation

PHY is not active

Isolation

3+ PC = 0

Isolation

PHY is not active

Isolation

PHY is not active

Isolation

5 Self Powered (PHY is powered by cable in power off state) (Note 4)

1 PC = 0 PC = 4 PHY is not active

2 PC = 0

Isolation

PC = 4


PHY is not active

Isolation or repeat w/o limitation

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3+ PC = 0

Isolation

PC = 4

repeat with 1.5 amp limiters

PHY is not active

Isolation or repeat with 1.5 amp limiters

6 Cable Powered (Cable power is always used)

1 PC = 4,6,7 PC = 4,6,7 PHY is not active

Not allowed Multi-port Not allowed Not allowed Not allowed

Note 1: Some device may have a ―stand-by‖ state, in which a device may follow ―ON‖ or ―OFF‖ rule

depending on whether PHY is powered or not powered by the design. See Note 2 and 3.

Note 2: Type 1 device may optionally turn off supplying power to the cable in a ―standby‖ mode, in that

case the device acts as type 4 device.

Note 3: Type 2 device may optionally turn off supplying power to the cable in a ―standby‖ mode, in that

case the device acts as type 5 device.

Note 4: Type 2 and 5 devices have to change connection between the power pin of the connectors.

4.5.1.1 Cable Power Suppliers

Primary Power Provider

Primary Power providers have power class bits of 1, 2 or 3. They can be single port or multiple port, and

must only have 6 and/or 9 pin connectors (3 are recommend). A primary power provider must be tested to

insure that it is capable of sourcing the POWER specified by the power class bits. (See 4.5.2.1) The

quality of the power provider must also be verified. The VOLTAGE (See 4.5.2.2) and RIPPLE (See

4.5.2.3) are tested to insure this quality.

The following is defined by the Power Distribution specification:

Primary Power providers must not repeat power if their system power is present and provide

power domain isolation. If the Primary Power provider‘s system power is lost, it must become a

self-powered device (See 4.5.1.3), reported on the power class bits, and must, at this point, repeat

power. (See 4.5.2.7 for power REPEATING and ISOLATION test).

This document changes the requirement to:

Primary Power providers may repeat power if their system power is present and may provide

power domain isolation. If the Primary Power provider‘s system power is lost, it may become a

self-powered device (See 4.5.1.3) and shall report the change on the power class bits, and may, at

this point, repeat power. (See 4.5.2.7 for power REPEATING and ISOLATION test).

Primary Power providers must never exceed 1.5 amps sourcing on any port (See 4.5.2.4 for Current

LIMITING test)

Alternate Power provider

Alternate Power providers should have a power class bit setting of 4. They can be single port or multiple

port, and must only have 6 and/or 9 pin connectors (2 are recommend). The voltage output of an alternate

power provider is less than that of a primary power provider, but must still meet a minimum requirement of

8 volts, though 9.25 volts is recommended. A maximum of 30 volts output is expected.

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Isolation rules are recommended but not mandatory per this specification if the output voltage is greater

than 20 volts, but at 20 volts and less, diode isolation may or may not be implemented. (See 4.5.2.7 for

Isolation test). Current limiters (if not using diode isolation) should limit current output 1.5 amps (See

4.5.2.4). If isolation diodes are employed, then if device ceases to provide power, it must become a self-

powered PHY and must set power class bits to 0. They should trickle power the PHY from the cable power

(See 4.5.1.3 for self power consumption).

4.5.1.2 Cable Power Consumers

Cable power consumers must report power class of 4, 6 or 7 and must have only one 6 or 9 pin connector.

The device‘s PHY must be tested to operate with an input cable voltage of 7.5.

Power consumption should be limited to 3 watts prior to link activation. After link activation, power

consumption should not exceed the amount specified by the power class bits (See Power consumption test

4.5.2.5).

4.5.1.3 Self Powered Devices

Self powered devices can be single port with a power class of 0 or multi-port with a power class of 0 or 4.

If it is a multi-port device, then it must be tested to cable power the PHY when the devices power is not up.

In this mode, the cable power consumptions should not exceed 3 W (See 4.5.2.5).

Self powered devices must be tested to insure that they never source power.

If the device has only 2 ports, then it should repeat power without limiters, but if more than 2 ports, then

each port should employ a 1.5 amp current limiter (See Current Limiting 4.5.2.4).

4.5.2 Cable Power Test ing

Cable power testing can be accomplished using a lab bench power supply and a 1394 cable, Cable Power

Tester as specified in schematic form (please see attached schematic).

The Cable Power Tester (CPT) can be plugged in series between two nodes, typically a cable power

provider and a cable power consumer. The Implementation Under Test (IUT or DUT) should be plugged

in the ‗To DUT‘ connector for proper perspective of current and power direction. A test node can be

plugged into the ‗OTHER‘ connector. The test node can also provide a means to confirm Power class bit,

link active status, and occurrence of bus reset.

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Figure 37: General Cable Power Test Configuration

This Cable Power Tester (CPT) performs the following functions:

Power regulated loads of: 15, 30 and 45 Watts

Current regulated loads of 0.66, 1.33, 2.0 amps

Digital measurements of cable:

o Voltage

o Ripple (peak to peak)

o Current (amps) sourced or sinked

o Power (watts) sourced or sinked

LED indicator if current direction: (whether IUT is: sourcing or sinking)

Snap-shot detectors for:

o > 18mJ 3mS inrush energy

o <7.5 volts input

o > 0 watts consumed




o > 1.5 amps sourced

o > 1 volt peak to peak ripple sourced

o < 8 volts sourced

CPT

DUT

Load Device (if used)

Power Supply (if needed)

DUT

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o > 33 volts sourced

A reset button is provided to clear the detector LEDs. Once a detector is tripped, the associated LED

will stay lit until the reset button is pressed. This allows for momentary events to be noticed that

would otherwise not be detected with a DVM, without requiring the use of a digital sampling O-scope.

An external supply can be plugged in to allow the CPT to supply cable power to the IUT.

4.5.2.1 Cable Power Source POWER Test

The cable power source POWER should be tested on primary and alternate power providers, if a

description of power sourcing is available. To test power sourcing, a port should be momentarily loaded

with the specified power load as indicated by table below, based on the Power Class. This is done by

pressing either the 15W button, the 30W button or both the 15W and 30W buttons for 45W load. Select

WATTS on the CPT‘s DPM. With the IUT supplying power, be sure that the Power indicated on the DPM

equals the intended load. Walk load through each port and repeat test. Repeating the test on all ports is

necessary to confirm adequate printed circuit layout (trace width) to all connectors. If the voltage being

sourced is fairly low (less than 10V), it is recommended that multiple connectors of the IUT be connected

to the CPT in parallel, prior to loading down the IUT. This is to avoid exceeding 1.5 amp per connector

limit.

No bus reset should occur when load is activated or deactivated.

Power Class Power Load Pass/Fail

1 15 watts

2 30 watts

3 45 watts

4 Not determined

4.5.2.2 Cable Power Source Voltage Test

The cable power source voltage should be tested on primary and alternate power providers. In the case of

primary power providers, a port should be test with no load and momentarily loaded with the specified

power load as indicated by table below, based on the Power Class. This is done by pressing either the 15W

button, the 30W button or both the 15W and 30W buttons for 45W load. Select VOLTS on the CPT‘s

DPM. With the IUT supplying power, be sure that the voltage stays within the values indicated below on

all ports during the power load. Select WATTS on the CPT‘s DPM and repress the load button(s),

confirming that the load is occurring. Walk load through each port and repeat test. Repeating the test on

all ports is necessary to confirm adequate printed circuit layout (trace width) to all connectors.


1394 TA 2002005 Revision 2.3


Power Class Minimum source

voltage output

Maximum source

voltage output

Power Load Measured Vout

1 20 volts 33 volts 15 watts

2 20 volts 33 volts 30 watts

3 20 volts 33 volts 45 watts (use 2 or

more DUT

connectors in

parallel to the

CPT)

4 8 volts

(9.25volts

preferred)

30 volts 0 watts

4.5.2.3 Cable Power Source Ripple Test

The cable power source Ripple from a power provider should never exceed 1 volt peak to peak. This

should be verified by connecting the appropriate load (<15W, 15W, 30W, 45W). Setting of the ripple

indicator at the time of connection should be ignored. After the connection has settled apply the load for 10

second. The Max ripple indicator should not light at any time and the measured ripple should stay below 1

volt P-P. Repeat this test 4 times for each port.

4.5.2.4 Cable Power Current Limiting Test

The cable power current limiting should be tested on power providers to not exceed 1.5 amps. To test

current limiting, a port should be momentarily loaded with an attempted current load higher than 1.5 amps.

This is done by pressing both the 0.66 amp button and the 1.33 amp button at the same time. This attempts

a 2.0 amp load on the IUT. Select AMPs on the CPT‘s DPM. With the IUT supplying power, be sure that

the current indicated on the DPM does not exceed 1.5 amps. Walk load through each port and repeat test.

Repeating the test on all ports is necessary to confirm the limiters are correctly implemented on all ports.


Power Providers should be able to accept a short to ground on cable power output. Connect IUT to the

CPT and confirm the IUT is outputting voltage. Momentarily short the banana jack inputs of the CPT. No

bus reset should occur. If IUT has more than one port monitor the other ports to see if the other port

maintain a voltage will the CPT port is shorted.

4.5.2.5 Cable Power Consumption Test

The cable power consumption can be measured using the CPT. Select the CPT‘s DPM to WATTS.

Connect an external power supply to the CPT‘s banana jacks. Set the voltage to 33 volts. Plug the IUT

into the IUT connector on the CPT. The power consumption should be verified with the link NOT active

and with the link active. Using the table below, based on Power Class bits and link active, determine if the

power consumptions is within limits.

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Case Maximum power

consumed

Measured Power

consumption

Link NOT active 3 watts

Power Class = 4

Link active

3 watts

Power Class = 6

Link active

6 watts

Power Class 7

Link active

10 watts

4.5.2.6 Cable Power Energy In-Rush Test

To test power consumer device‘s Energy In-rush, reset the CPT‘s snapshot detectors. Turn on supply

connected to the banana jacks or use an adequate cable provider plugged into the ‗OTHER‘ connector.

Connect the IUT to one of the CPT‘s ―TO DUT‖ connectors. Be sure the In-Rush detector does not light.

Activate link of the IUT. Make sure the In-Rush detector still doesn‘t light. If the In-rush detector does

light, then the device has exceeded the 18mJ in 3 mS specification for energy in-rush.

4.5.2.7 Cable Power Repeat ing/Isolating test

The rules for repeating (accepting power on one port and passing it through to other port(s)) and isolating

power (accepting power on one port an NOT passing it through to other ports) are such that multiple

scenarios must be tested for each type of device, based on the power class bits, whether devices system

power in on or off, and how many 6 and/or 9 pin ports it has.

The table below indicates the power class that should be reported in different scenarios as well as the mode

the device should be operating in, in term of isolating power, repeating power and the use current

limitation.

The device must be tested both in the ―device‘s main power OFF‖ condition and ―device‘s main power

ON‖ condition. In each condition, look up the device‘s behavior from the table and use the tests that are

described below to confirm the behavior.

# of ports (6 pin or 9 pin)

Device’s main power is ON

Devices main power is OFF (PHY should be trickle powered from the cable)

Devices main power is OFF (with insufficient voltage to power the PHY)

Primary Power Provider

1 Not Applicable

2 PC=1, 2, 3, source may limit with diode isolation, handles shorts

PC = 0, repeat w/o limitation

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3+ PC=1, 2, 3, source limited with diode isolation, handles shorts

PC = 0, repeats w/ 1.5amp limiters

Alternate Power Provide

1 Not Applicable

2 <=20volts output

PC = 4, source limited with diode isolation or must discontinue sourcing if greater cable voltages is sensed.


> 20 volts output

PC=4, source with diode isolation


3+ <=20volts output

PC = 4, source limited with diode isolation or must discontinue sourcing if greater cable voltages is sensed.


> 20 volts output

PC=4, source with diode isolation


Power Consumer

1 Not Applicable

Self Powered 2 PC = 0, No power repeated

PC = 4, repeats w/o limiter

No power repeated

3+ PC = 0, No power repeated

PC = 4, Repeats w. 1.5 amp limiters

No power repeated

4.5.2.7.1 Test for No power repeated

To test for no power repeated, simply attach a power provider to one port of the IUT. Walk the CPT

through the other ports, confirming that no voltage is being output.

4.5.2.7.2 Test for repeats with 1.5 amp limiters

To test for 1.5 amp limited repeating requires the use of a 1394 to banana plug cable to supply power to one

port and a CPT to load the other ports to confirm current limiting.

With the 1394 to banana plug cable, plug external power supply into one of the IUT connectors. Set power

supply to 12 volts and current limiting to 2 amps.

With the CPT, walk through the other IUT ports. At each port, press both the 0.66 amp and 1.33 amp load

buttons while reading the current on both CPT’s. Both should read only 1.5 amps even though a 2 amp

load is being attempted. Repeat on all ports. Note: some commonly used current limiters may take a few

seconds to react the 2 amp load. If the current limiter doesn’t response within 5 seconds of applying the

limiter fails.

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4.5.2.7.3 Test for Repeats without l imiters

To test non-limited power repeating requires the use of a 1394 to banana plug cable to supply power to one

port and a CPT to load the other ports to confirm non-limitation.

With the 1394 to banana plug cable, plug external power supply into one of the IUT connectors. Set power

supply to 12 volts and current limiting to 2 amps.

With the CPT, walk through the other IUT ports. At each port, press both the 0.66 amp and 1.33 amp load

buttons while reading the current.

The CPT should read 2.0 amps on each port.

4.5.2.7.4 Test for Source with diode isolat ion

To test for Source with diode isolation requires the use of a 1394 to banana plug cable to supply power to

one port and a CPT to load the other ports to confirm the isolation of the other ports.

With the CPT plugged into a connector on the IUT, measure the Voltage output with CPT’s DPM. Note

this reading.

With the 1394 to banana plug cable, plug external power supply into the banana jacks. Set power supply

to 3 volts higher than voltage level being output from the IUT.

Walk the CPT through the other ports and confirm that they only output the original voltage of the DUT,

not the higher voltage of the external supply.

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5. Link Enabled Node Testing

5.1 Overview

An IEEE-1394 node may consist of a PHY only. However, if the link layer is active, an entire set of

requirements must be implemented. The requirements span the link, transaction and serial bus management

layers. Given the generic black box nature of this test environment, testability can only be guaranteed if

required functions are used to test the node. This is not to say the optional features won‘t be tested, they

will, but they are not required to guarantee testability of the node.

The following test environment will be used for all tests unless otherwise specified:

Bus Analyzer---Tester---IUT

5.1.1 Required Changes for 1394b

IEEE-1394b primarily enhanced the capabilities of 1394‘s PHYsical layer. However some of these

PHYsical layer changes require changes to the link layer and above. While IEEE-1394b enhancements are

meant to be backward compatible they do introduce opportunities for non-interoperability. Therefore of

some tests target both IEEE-1394b and legacy devices.

Enhancements with tests for both IEEE-1394b and legacy devices:

- New Self-ID packet support

- Port Dependent Speed Routes

- Appropriate setting of Gap_Count

Enhancements with tests for only IEEE-1394b devices:

- Transmit of packets at faster data rates

- Transmit of bigger packets when sending at high data rates (Not tested in this document)

- Use of 1394b packet formats when on beta bus (Not tested in this document)

- Support of Standby Mode (Not tested in this document)

5.1.2 Required Functions

Any node on the Serial bus with an enabled link layer shall be transaction capable, i.e., capable of

origination of and response to asynchronous transactions with other transaction capable nodes on the bus.

Additionally, transaction capable nodes shall implement configuration ROM, either minimal or general

formats. This test suite relies on the configuration ROM to determine the nodes capability and determine

which tests can be run.

A transaction capable node shall implement the following:

- Base Rate (S100 for the cable environment)

- Quadlet read and write transaction support

- The following Core CSR registers

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o STATE_CLEAR

o STATE_SET

o NODE_IDS

o RESET_START

o SPLIT_TIMEOUT

- General format Configuration ROM

- Speed routes

The validity of the configuration ROM format will be verified as part of the test. The content of the

configuration ROM will be used to determine the node‘s capabilities.

5.1.3 Optional Functions

The general format configuration ROM can be used to determine what optional IEEE-1394 facilities are

supported. The facilities supported in turn require the support of several functions. The facilities are:

- Isochronous capable (isc)

- Cycle master capable (cmc)

- Isochronous resource manager capable (irmc)

- Bus manager capable (bmc)

- Power manager capable (pmc)

While there are some interdependencies between each facility and the functions required too support them,

in general there is a progression of support. The functions required by each facility are listed below:

Isochronous capable

- Implement configuration ROM in general ROM format

- Implement the CYCLE_TIME serial bus dependant CSR

Cycle master capable

- Implement configuration ROM in general ROM format

- Implement the CYCLE_TIME serial bus dependant CSR

- Generate cycle start packets

- Implement the BUS_TIME serial bus dependant CSR

Isochronous resource manager capable

- The following Serial Bus Dependant Register:

o BUS_MANAGER_ID

o BANDWIDTH_AVAILABLE

o CHANNELS_AVAILABLE

o BROADCAST_CHANNEL

- Have the ability to analyze received self-ID packet to determine the physical ID of the isochronous

resource manager from all the contender nodes.

- Implement the general configuration ROM format

- Execute the responsibilities of the isochronous resource manager (IRM)

- In the absence of a bus manager, the IRM must be able to perform the following functions:

o gap count optimization

o limited power management

o set a node‘s force root flag true

Bus manager capable


o BUS_MANAGER_ID

o BANDWIDTH_AVAILABLE

o CHANNELS_AVAILABLE

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o BROADCAST_CHANNEL

o TOPOLOGY_MAP

- Have the ability to analyze received self-ID packet to determine the physical ID of the isochronous

resource manager from all the contender nodes.

- Implement the general configuration ROM format

- Execute the responsibilities of the isochronous resource manager (IRM)

- Perform the following functions:

o gap count optimization

o power management

o set a node‘s force root flag true

5.2 Link Enable Testing Procedures

5.2.1 Transact ion Capable

5.2.1.1 Determine if Transaction Capable Node Test Procedure

The first step, determine if IUT is a transaction capable node.

ID Question Answer Standard

Reference6

TC11 Is link_active = TRUE within IUT‘s self-ID packet? Yes or No 4.3.4.1

TC12 If link_active = FALSE send link-on packet addressed to

IUT. Initiate a bus reset. Is link_active = TRUE within

IUT‘s self-ID packet?

Yes or No 4.3.4.2

Check

Point

If you answered “No” to TC11 and TC12, IUT is not a

transaction capable node. STOP HERE!

5.2.1.2 Core CSR Register Support Test Procedure

5.2.1.2.1 STATE_CLEAR and SET Test Procedure

This section describes the tests for STATE_CLEAR and SET CSRs. In this section only the action of

reading and writing the gone bit generically and the reserved fields are tested as the abdicate, linkoff, and

cmstr bits are tested in the Serial Bus Manager, Power Management, and Cycle Master sections

respectively. The following fields are not tested: lost, dreq, elog, atn, off, and state.


Reference

TC211 At S100 speed, read one quadlet from the

STATE_CLEAR register, address:

Destination offset high = ffff16

Destination offset low = f000_000016

Is the response rcode in the read response quadlet payload

016?

Yes or No IEEE-1394a-2000

8.3.2.2.1

6 Unless stated otherwise all section reference numbers refer to IEEE-1394-1995.

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Check

Point

If you answered “No” to TC211, IUT failed the read of

STATE_CLEAR register. FAILURE!

Note: Examine the rcode, if the rcode is 4, a possible

but rare condition occurred. Retry transaction. If

condition persists, FAILURE!

TC212 At S100 speed, write 0000780016 to the STATE_SET

register, address:



Is the response rcode in the write response quadlet payload

016?

Yes or No

Check

Point

If you answered “No” to TC212, IUT failed the write of

STATE_SET register. FAILURE!




TC213 At S100 speed, read one quadlet from the

STATE_CLEAR register, address:



Is the value read equal to the value read in ID TC211?

Yes or No

Check

Point

If you answered “No” to TC213, the reserved IUT

failed the write of STATE_CLEAR register.

FAILURE!




5.2.1.2.2 NODE_IDS Test Procedure

The NODE_IDS test procedure primarily tests the IUT‘s bus_id field support and, in the process, verifies

both read and write transactions to this CSR.


Reference

TC221 At S100 speed, read the NODE_IDS register, address:

Bus_ID = 3ff16, local bus access



Is the rcode in the read response packet 016?


8.3.2.2.3

Check

Point


NODE_IDS register. FAILURE, Stop NODE_IDS test!




TC222 Was the NODE_IDS.offset_id value correct? Yes or No

Check

Point

If you answered “No” to TC222, IUT returned an

inconsistent value for the NODE_IDS.offset_id field.

FAILURE, Stop NODE_IDS test!

TC223 At S100 speed write the bus_id field within the

NODE_IDS register with a valid value that is different

Yes or No

1394 TA 2002005 Revision 2.3


than value read in TC221. The NODE_IDS register

address is:



Is the rcode in the write response packet 016?

Check

Point


the NODE_IDS register. FAILURE, Stop NODE_IDS

test!




TC224 At S100 speed, read the NODE_IDS register using the

bus_id value previously written. The NODE_IDS register

address is:




016?

Yes or No

Check

Point






TC225 Is the bus_id field value equal to what was written in

TC223?

Yes or No

Check

Point



TC226 At S100 speed, read the NODE_IDS register with bus_id

indicating local bus access. The NODE_IDS register

address is:




016?

Yes or No

Check

Point






- Set bus_id field back to original value. -

5.2.1.2.3 RESET_START Test Procedure

The RESET_START test procedure primarily tests the IUTs ability to handle a write to the

RESET_START register, which should immediately initiate a command reset. The RESET_START

register, a write only register, is also read to see if an rcode of resp_type_error (6) is returned in the

response packet.

Note: the command reset may not be visible outside the IUT; therefore this test doesn‘t guarantee the

command reset is executed.

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68



Reference

TC231 At S100 speed write the RESET_START register, value

doesn‘t matter. RESET_START register address is:


Destination offset low = f000_000C16


Yes or No 8.3.2.2.4

Check

Point


the RESET_START register. FAILURE, Stop

RESET_START test!




TC232 At S100 speed, read the RESET_START register, address:



Is the rcode in the read response packet 616?

Yes or No

Check

Point

If you answered “No” to TC232, IUT did NOT handle

the read of RESET_START register correctly.

WARNING!

5.2.1.2.4 SPLIT_TIMEOUT Test Procedure

The SPLIT_TIMEOUT test procedure verifies the default value of SPLIT_TIMEOUT_HI and LO. It also

sets the value to both the maximum and minimum values. The time for the IUT to respond to a request is

also measured.

The consistency of all nodes SPLIT_TIMEOUT registers is tested in the Serial Bus Manager section.


Reference

TC241 At S100 speed, read the SPLIT_TIMEOUT_HI and

SPLIT_TIMEOUT_LO register, addresses are:


Destination offset low = f000_001816 HI

Destination offset low = f000_001C16 LO

Is the rcode for each read response packet 016?


8.3.2.2.6

Check

Point


SPLIT_TIMEOUT_HI and LO registers. FAILURE,

Stop SPLIT_TIMEOUT test!




TC242 Is the value of SPLIT_TIMEOUT_HI and LO greater than

or equal to 100ms (0000000016, 1900000016)?

Yes or No

Check

Point

If you answered “No” to TC242, IUT’s default value is

less than 100ms. FAILURE!

TC243 At S100 speed write the SPLIT_TIMEOUT_HI and LO

registers with the maximum value of: 0000000716,

F9F8000016. SPLIT_TIMEOUT_HI and LO register

addresses are:



Yes or No

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Check

Point

If you answered “No” to TC243, IUT failed the write

of the SPLIT_TIMEOUT_HI and LO registers.

FAILURE, Stop SPLIT_TIMEOUT test!





SPLIT_TIMEOUT_LO registers, addresses are:





Yes or No

Check

Point







TC246 Is the value of SPLIT_TIMEOUT_HI and LO to 8

seconds (0000000716, F9F8000016)?

Yes or No

Check

Point

If you answered “No” to TC246, IUT’s didn’t accept

write to maximum value. FAILURE!

TC247 At S100 speed write the SPLIT_TIMEOUT_HI and LO

registers with the minimum value of 1ms (0000000016,

0008000016). SPLIT_TIMEOUT_HI and LO register

addresses are:





Yes or No

Check

Point

If you answered “No” to TC247, IUT failed the write

of the SPLIT_TIMEOUT_HI and LO registers.

FAILURE, Stop SPLIT_TIMEOUT test!





SPLIT_TIMEOUT_LO registers, addresses are:





Yes or No

Check

Point







TC249 Is the value of SPLIT_TIMEOUT_HI and LO 1ms Yes or No

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70


(0000000016, 0008000016)?

- Note: The node should accept the write to the minimal

value, however it should behave as though the split

timeout is 100ms.

-

Check

Point

If you answered “No” to TC249, IUT’s didn’t accept

write to minimum value. FAILURE!

- Note: Can’t control the response time of the IUT and

can’t guarantee the IUT can independently initiate a

request to the Tester Node. Therefore verification of the

split timer itself can’t be guaranteed. However we can

verify the response time of IUT.

-


SPLIT_TIMEOUT_LO registers, address:




Was the response packet received in less than a

SPLIT_TIMEOUT time (100ms)?

Yes or No

Check

Point

If you answered “No” to TC2410, IUT’s didn’t

respond to the read request quickly enough.

FAILURE!

5.2.1.3 Conf iguration ROM Presence Test Procedure

The Configuration ROM Presence Test tests to determine if the configuration ROM is present, and if it is,

does it support minimal ROM or general ROM formats.


Reference

TC31 At S100 speed, read one quadlet from address:




Yes or No 8.3.2.5.2

Check

Point


1st location of configuration ROM. FAILURE, Stop

testing!




TC32 Is the most significant byte of the quadlet read response

payload = 0116?

Yes or No

Check

Point

If you answered, “Yes” to TC32, IUT supports the

Minimal ROM Format. Proceed to Minimal ROM

Format Test.

TC33 Is the most significant byte of the quadlet read response

payload = 0416?

Yes or No 8.3.2.5.3

Check

Point

If you answered “No” to TC32 and TC33, IUT does not

support a ROM. FAILURE, Stop Testing!

Check

Point

If you answered, “Yes” to TC33, IUT supports the

General ROM Format. Proceed to General ROM

Format Test!

1394 TA 2002005 Revision 2.3


5.2.1.4 Minimal ROM Format Test Procedure


Reference

- Protocol Implementation eXtra Information for Test

(PIXIT).

Vendor_ID =

- 8.3.2.5.2




Are the 3 least significant bytes of the quadlet read

response payload = Vendor_ID?

Yes or No

Check

Point

If you answered “No” to TC41, Vendor_ID isn’t valid.

FAILURE, Stop Testing! Else SUCCESS, Stop

Testing!

5.2.1.5 General ROM Format Test Procedure


Reference




Is the crc_length (bits 8 through 15) field greater than or

equal to 4 and less than or equal to 255?

Yes or No 8.3.2.5.3

Check

Point

If you answered “NO” to TC51, IUT’s crc_length is

invalid. FAILURE, Stop Testing!

- Warning: IEEE-1212-2001 strongly recommends the

info_length and crc_length be equal.

TC52 Starting at ROM offset 040416 read one quadlet (S100

speed) at a time until the number of quadlets specified in

the crc_length field has been read. Calculate the 16-bit

CRC on the data read.


Destination offset low = f000_040416 to (040416+

crc_length)

Is the calculated CRC equal to the rom_crc_value (offset

40016, bits 16 through 31) field?

Yes or No IEEE-1212r 7.3

Check

Point

If you answered “NO” to TC52, IUT’s rom_crc_value

is invalid. FAILURE, Stop Testing!

TC53 Does the first quadlet of the bus_info_block



contain 3133393416 (ASCII for 1394)?

Note: The contents of the bus_info_block were read in

TC52.

Yes or No

Check

Point

If you answered “No” to TC53, IUTs is not an IEEE-

1394 Device. FAILURE, Stop Here!

- The details of each remaining field of the bus information

will be verified in their respective sections.

-

TC54 Continue to parse the remainder of the Configuration

ROM and verify that each section‘s CRC value is correct.

Was the remainder of the Configuration ROM correctly

structured and did each CRC value correctly calculate?

Yes or No

Check If you answered “No” to TC54, IUT’s overall ROM

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72


Point structure is invalid. FAILURE!

5.2.1.6 Block Packet Support Test Procedure

Using max_ROM field determine what block transaction size is supported. If the value is 0, still try to read

first 5 quadlets from ROM as a single block transaction.

Note: IEEE1394a-2000 states: ―Devices that report a max_ROM value of zero should support block read

request capable of returning the first five quadlets of configuration ROM in one transaction.‖


Reference




From the read response payload record the value of

max_ROM (bit 22-23) and max_rec (bit 17-20)

- IEEE-1394a2000

8.3.2.5.4

TC61B If max_ROM is nonzero is max_rec greater than or equal

to 2max_ROM+1

+1?

Yes or No

TC62 If max_ROM is 0, at S100 speed using a read block

request, read the first 5 quadlets from the ROM starting at

address:



Did IUT return the first 5 quadlets of the configuration

ROM and was the response code field = 0016?

Yes or No

Check

Point

If you answered “NO” to TC62, block read of IUT’s

bus information block is not supported. Warning!

TC63 If max_ROM is 1, at S100 speed using a read block

request, read the first 16 quadlets (64 bytes) from the

ROM starting at address:





Yes or No

Check

Point

If you answered “NO” to TC63, max_ROM of 1 is not

correctly supported. FAILURE!

TC64 If max_ROM is 2, at S200 or S400 or S800 speed using a

read block request read the first 256 quadlets (1024 bytes)

from the ROM starting at address:





Yes or No

Check

Point

If you answered “NO” to TC64, max_ROM of 2 is not

correctly supported. FAILURE!

5.2.1.7 Mult iple Speed Transact ion Support Test Procedure

Using PHY speed found in self-ID packet and link_spd field found in the Bus_Info_Block, determine the

maximum supported speed. (Assumes the tester node is capable of maximum speed and IUT is directly

connected to the tester node.)

Read the Configuration ROM multiple times at all speeds from base rate to maximum supported speed.

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Reference




From the read response payload, record value of link_spd

(bit 29-31).

- IEEE-1394a-2000

8.3.2.5.4

TC72 From IUT‘s self-ID, record the value of sp. Is sp == 11b? - IEEE-1394a-2000

4.3.4.1

Check

Point

If you answered “Yes” to TC72, the PHY is not legacy,

go to TC76.

TC73 Set max_speed to the lesser of link_spd and sp. -

TC74 Send 1000 read quadlet requests at each supported speed

from base rate to max_speed. Send each request to

location:



Was each packet sent and received correctly?

Yes or No

Check

Point

If you answered “NO” to TC74, quadlet read of IUT at

multiple speeds did not complete correctly. FAILURE!

TC75 Send 1000 read block (used max_ROM to determine size)

requests at each supported speed from base rate to

max_speed. Send each request to location:




Yes or No

Check

Point

If you answered “NO” to TC75, block read of IUT at


Stop and go to next section.

TC76 Using remote PHY register access read port register 0xA

for each supported port. Record Max_port_speed and

Cable_speed for each port.

-

TC77 Set variable max_spd_n (where n is port number) to the

lesser of Max_port_speed and Cable speed. (Make sure the

tester supports max_spd_n)

-

TC78 For each port send 1000 read quadlet requests at each

supported speed from base rate to max_speed_n. Send

each request to location:




Yes or No

Check

Point

If you answered “NO” to TC78, quadlet read of IUT at


TC79 For each port send 1000 read block (used max_ROM to

determine size) requests at each supported speed from base

rate to max_speed. Send each request to location:




Yes or No

Check

Point

If you answered “NO” to TC79, block read of IUT at


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74


5.2.1.8 Determination of Speed Route Test Procedure

With the introduction of IEEE-1394b the self-ID packet‘s speed field is no longer adequate to determine

the speed map of the 1394 bus. This specification doesn‘t attempt to test the method used to determine the

speed map, instead it only tests whether the implementation under test adequately determines the speed

path for devices it needs to talk with.

For this test the following topology shall be used.

Figure 38: Speed route test topology


Reference

TC81 Connect Tester1 and Tester 2 to IUT as shown in Figure

38. Tester2 shall support all speeds supported by IUT.

Tester1 shall connect at speed(s) less than IUT‘s

maximum operating speed, unless IUT is an S100 only

device. In either case the sp field of Tester1 shall be 11b.

-

TC82 Verify data after bus reset caused by connection to

determine if IUT initiates bus traffic (request packets). Did

IUT initiate requests?

Yes or No

Check

Point

If you answered “No” to TC82, the IUT doesn’t initiate

autonomous requests. Non-conclusive, end test7!

TC83 Were IUT‘s requests S100 only? Yes or No

Check

Point

If you answered “Yes” to TC83, the IUT only initiates

S100 packets for generic transactions. If so, look for

another method for determining speed route.

TC84 Did IUT attempt to find the maximum speed route

between IUT and Tester18?

Yes or No

Check

Point

If you answered “No” to TC84, IUT didn’t attempt to

determine speed route yet used packets greater then

S100. FAILURE, end test!

7 The network test suite (one of the four required test suites) should test speed route in a more device specific manor.

For the purposes of this test it is non-conclusive. 8 There is more than one method to determine the speed route. Currently two methods are commonly used. The first

reads the appropriate PHY and Configuration ROM locations for each device in the path and from that derives the

speed route; the second simply tries packets at higher and higher or lower and lower speeds until the maximum

functional speed is found.

Tester 2 IUT Tester 1

1394 TA 2002005 Revision 2.3


5.2.2 Isochronous Capable Node

An isochronous capable node shall have the isc bit in the bus_info_block set to one. In addition to the isc

bit an isochronous capable node shall implement the CYCLE_TIME CSR.

5.2.2.1 Isoc General ROM Support Test Procedure


Reference

IC11 At S100 speed, read one quadlet from address:



Is the isc (bit 2) field set to 1?

Yes or No 8.3.2.5.4

Check

Point

If you answered “NO” to IC11, then IUT is not an

isochronous capable node. Proceed to Cycle Master test

section.

IC12 At S100 speed, write a 0 to the isc field which is bit 2 at

the following address:



At S100 speed, read one quadlet from address:



Is the isc (bit 2) field set to 1?

Yes or No 8.3.2.5.4

Check

Point

If you answered “No” to IC12, then isc is not a read

only location. FAILURE! Proceed to CYCLE_TIME

CSR test!

5.2.2.2 CYCLE_TIME CSR Test Procedure

Both Isochronous (isc) and Cycle Master (cmc) capable nodes shall support the CYCLE_TIME CSR. This

procedure reads the CYCLE_TIME register multiple times to determine if it is incrementing. The

CYCLE_TIME register rolls over every second. Therefore the algorithm used to determine if the cycle

timer is incrementing must take this into account.

Detailed timing of the CYCLE_TIME register as it applies to cycle start packets is tested in the Cycle

Master section.


Reference

IC21 At S100 speed, read one quadlet from address:



Is the cmc (bit 1) or isc (bit 2) field set to 1?

Yes or No 8.3.2.5.4

Check

Point

If you answered “NO” to IC21, then IUT is not cycle

master or isochronous capable node. End

CYCLE_TIME CSR test.

IC22 At S100 speed, read the CYCLE_TIME register repeatedly

at fixed intervals. The CYCLE_TIME register is located at

address:



Is the CYCLE_TIME registers timer free running and

rolling over?

Yes or No 8.3.2.3.1

Check If you answered “NO” to IC22, the CYCLE_TIME is

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76


Point not functioning correctly. FAILURE!

5.2.3 Cycle Master Capable Node

If a node claims to be Cycle Master Capable (cmc) in its configuration ROM it shall support

CYCLE_TIME and BUS_TIME CSRs and support the generation of cycle start packets. The node must

also follow the rules that govern the enabling of the cycle master and generation of cycle start packets.

5.2.3.1 CMC General ROM Support Test Procedure


Reference

CM11 At S100 speed, read one quadlet from address:



Is the cmc (bit 1) field set to 1?

Yes or No 8.3.2.5.4

Check

Point

If you answered “No”to CM11, then IUT is not cycle

maser capable node. Proceed to next test step.

CM12 At S100 speed, write the opposite value to the cmc field,

which is bit 1 at the following address:






Did the cmc (bit 1) field change?

Yes or No 8.3.2.5.4

Check

Point

If you answered “Yes” to CM12, then cmc is not a read

only location. FAILURE, Proceed to next check point.

Check

Point

If cmc is not set then proceed to next test group. If cmc

is set, proceed to next the next section.

5.2.3.2 CYCLE_TIME CSR Test Procedure

Please refer to section 5.2.2.2.

5.2.3.3 BUS_TIME CSR Test Procedure

Cycle Master (cmc) capable nodes shall support the BUS_TIME CSR. This procedure reads the

BUS_TIME register multiple times to determine if it is incrementing. The BUS_TIME register rolls over

every ~136 years. Therefore the algorithm used to determine if the BUS_TIME is incrementing must take

this into account.


Reference

CM31 Force IUT to be root and write STATE_CLEAR.cmstr bit

to 1.

-

CM32 At S100 speed, read the BUS_TIME register repeatedly at

fixed intervals. The BUS_TIME register is located at

address:



Is the BUS_TIME registers timer free running?

Yes or No 8.3.2.3.2

Check If you answered “No” to CM32, the BUS_TIME is not

1394 TA 2002005 Revision 2.3


Point functioning correctly. Failure!

CM33 At S100 speed, write the BUS_TIME register with a value

n seconds from rolling over (ffff_ffcx16). Wait at least n

seconds and at S100 speed read the BUS_TIME register

which is located at address:



Did the BUS_TIME roll over (back to ~0) successfully?

Yes or No

Check

Point

If you answered “No” to CM33, BUS_TIME is not

rolling over correctly. FAILURE!

CM34 Force IUT to not be root. -

CM35 At S100 speed, read the BUS_TIME register repeatedly at

fixed intervals. The BUS_TIME register is located at

address:



Is the BUS_TIME registers timer free running?

Yes or No

Check

Point

If you answered “No” to CM35, BUS_TIME is not

functioning correctly. FAILURE!

5.2.3.4 Generat ion of Cycle Start Packets Test Procedure

IEEE-1394-1995 and IEEE-1394a-2000 define a set of rules that govern the generation of cycle start

packets. This section tests to determine if the IUT follows these rules correctly.


Reference

CM41 With tester node SBM force IUT to not be root. -

CM42 At S100 speed, read the STATE_CLEAR CSR. The

STATE_CLEAR register is located at address:



Is the STATE_CLEAR.cmstr bit 0?

Yes or No 8.3.2.2.1, 8.4.2.6

and IEEE-1394a-

2000 8.3.2.2.1

Check

Point

If you answered, “NO” to CM42, the value of

STATE_CLEAR.cmstr is incorrect. FAILURE!

CM43 Is IUT NOT sending cycle start packets? Yes or No

Check

Point

If you answered, “NO” to CM43, IUT is incorrectly

sending cycle start packets. FAILURE!

CM44 At S100 speed, write the STATE_SET.cmstr bit to 1. The

STATE_SET register is located at address:



-






Yes or No

Check

Point

If you answered, “NO” to CM45, IUT didn’t clear the

STATE_CLEAR.cmstr bit. FAILURE!

CM46 With tester node SBM force IUT to be root and don‘t set

STATE_SET.cmstr bit to 1.

-





Yes or No

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78



Check

Point



CM48 Is IUT sending cycle start packets? Yes or No 1394a desired

behavior

Check

Point


sending cycle start packets. WARNING!

CM49 At S100 speed, write the STATE_SET.cmstr bit to 1. The

STATE_SET register is located at address:



-






Yes or No

Check

Point

If you answered, “NO” to CM410, IUT didn’t set the

STATE_CLEAR.cmstr bit. FAILURE!

CM411 Is IUT sending cycle start packets? Yes or No

Check

Point

If you answered, “NO” to CM411, IUT is not sending

cycle start packets. FAILURE! (Skip step CM412)

CM412 Are cycle start packets going out every 125μsec

(nominally)?

Yes or No

Check

Point

If you answered “NO” to CM412, cycle start packets

are not going out every 125μsec. FAILURE!

CM413 Initiate bus reset. (Remember IUT was forced to be root in

step CM46)

-

CM414 Did IUT resume sending cycle start packets immediately

after bus reset? (Immediately means within 125μsec)

Yes or No

Check

Point

If you answered “NO” to CM414, IUT didn’t

automatically start sending cycle start packets after a

bus reset. FAILURE!

CM415 Force IUT to not be root. -

CM416 Is the STATE_CLEAR.cmstr bit 0? Yes or No

Check

Point



CM417 Is IUT NOT sending cycle start packets? Yes or No

Check

Point


sending cycle start packets. FAILURE!

CM418 With tester node SBM force IUT to be root and don‘t set

STATE_SET.cmstr bit to 1.

-

CM419 Is IUT sending cycle start packets? Yes or No 1394a desired

behavior

Check

Point


sending cycle start packets. WARNING!

5.2.4 Isochronous Resource Manager Capable Node

Isochronous Resource Manger (IRM) capable nodes shall have the irmc bit in the Bus_Info_Block set one.

The active IRM shall support the following CSRs:

- BUS_MANAGER_ID

- BANDWIDTH_AVAILABLE

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- CHANNELS_AVAILABLE_HI AND LO

- BROADCAST_CHANNEL (IEEE-1394A-2000)

In addition an IRM Capable node must participate in the IRM selection process.

In the absence of a Serial Bus Manager (SBM), the IRM should be able to perform the following functions:

- Gap count optimization

- Limited power management

o Set the linkoff bit in the bus_depend field of the STATE_CLEAR register to 1

o Issue a link_on packet

o Set a node‘s force root flag true (10.27)

Used to:

Make the root a Cycle Master Capable node

Select root that supports enhanced IRM functions

(BROADCAST_CHANNEL register).

5.2.4.1 IRM General ROM Support Test Procedure


Reference

IRM11 At S100 speed, read one quadlet from address:



Is the irmc (bit 0) field set to 1?

Yes or No 8.3.2.5.4

Check

Point

If you answered “No” to IRM11, then IUT is not an

IRM contender node. Proceed to next test group.

IRM12 At S100 speed, write a 0 to the irmc field at the following

address:






Is the irmc (bit 0) field set to 1?

Yes or No

Check

Point

If you answered “No” to IRM12, then irmc is not a

read only location. FAILURE!

5.2.4.2 IRM Determination Test Procedure

To determine the IRM the following algorithm is used:

From all IRM-capable nodes one is selected as follows:

a) An IRM-capable node that wishes to contend for the role of isochronous resource manager shall,

during the self ID process, transmit its own self ID packet with both the c bit (contender) and the L

bit (link active) set to one.

b) Each of these contenders shall also monitor all received self-ID packets in order to observe the

largest physical ID from a packet with both the c and L bits set.

c) The candidate node with the largest physical ID wins the role of the isochronous resource

manager.

IRM = ((Largest Physical ID) & (c == 1) & (L == 1))

Note: All Bus Manager-capable nodes shall be IRM capable.

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80



Reference

IRM21 Examine IUT‘s self-ID packet and determine the value of

the c and L bits.

Are the c and L bits and the irmc (see test step IRM11) all

1?


8.4.2.3

IRM21A Are the c and irmc bits equal? Yes or No

Check

Point

If you answered “No” to IRM21A, then IUT doesn’t

consistently indicate its IRM contender capability.

Failure!

Check

Point

If you answered “No” to IRM21, then IUT is not an

IRM contender node. Proceed to next test group.

5.2.4.3 Enhanced IRM Determination Test Procedure

Enhanced Isochronous Resource Manager Support:

IEEE-1394a-2000 requires the IRM to provide facilities that are not supported by IEEE-1394-1995. To

determine if the current IRM is IEEE-1394a-2000 compliant:

- Receives a write request to the tester nodes BROADCAST_CHANNEL register.

- Read the IRM‘s BROADCAST_CHANNEL register and the most significant bit is set to 1.

- Reading the IRM‘s generation field in the ROM and it is a non-zero value.


Reference

IRM31 Force IUT to become root. -

IRM32 At S100 speed, read the BROADCAST_CHANNEL CSR

located at address:



Is the rcode of the read response packet 016?


8.4.2.3

IRM32A If IRM32 is Yes, is the msb set to 1? Yes or No

IRM32B If IRM32 is No, is the rcode of the read response packet

A16?

Yes or No

IRM33 At S100 speed, read the Configuration ROM address

location:



Is the generation field (bits 24-27) greater than one (1)?

Yes or No

Check

Point

If you answered “No” to IRM32 or IRM33 then IUT is

not an Enhanced IRM node.

IRM34 If you answered “Yes” to IRM32 and IRM33 then

IUT is an Enhanced IRM node and supports IEEE-

1394a-2000 functions.

5.2.4.4 BUS_MANAGER_ID Test Procedure

The active Isochronous Resource Manager (IRM) maintains the BUS_MANAGER_ID register. As

previously described, of all the competing IRM capable nodes, only one becomes the active IRM. This set

of tests verifies the following:

1394 TA 2002005 Revision 2.3


- Verify BUS_MANAGER_ID register only supports quadlet read and lock compare and swap

transactions

o Verify operation if arg_value of lock compare and swap is incorrect.

- Verify the BUS_MANAGER_ID resets to the default value after a bus reset.


Reference

IRM41 Note: the following test assumes the tester node is the

incumbent SBM; therefore the tests described below have

125ms to complete.

- 8.4.2.5

IRM42 Force IUT to become IRM (e.g: skip test from IRM42 –

IRM414 for devices that are not IRM capable).

-

IRM43 Initiate Bus Reset -

IRM44 At S100 speed, read the BUS_MANAGER_ID CSR

located at address:




Yes or No

Check

Point

If you answered “No” to IRM44, IUT failed the read

of BUS_MANAGER_ID registers. FAILURE, Stop

BUS_MANAGER_ID test!




IRM45 Does the bus_mngr_id field (bits 26-31) contain the 3F16? Yes or No

Check

Point

If you answered “No” to IRM45 the

BUS_MANAGER_ID did not reset to the default

value. FAILURE, Stop BUS_MANAGER_ID test!

IRM46 Initiate a compare and swap operation with the

BUS_MANAGER_ID register. The arg_value should be

3F16 and data_value should contain the tester nodes

physical ID. The register is located at:



Is the rcode for the lock response packet 016?


8.4.2.3

Check

Point

If you answered “No” to IRM46, IUT failed the lock of

BUS_MANAGER_ID register. FAILURE, Stop





IRM47 Does the old_value returned in the lock response packet

equal the arg_value sent in the request packet?

Yes or No

Check

Point

If you answered “No” to IRM47 the compare and

swap operation failed. FAILURE! Stop



located at address:




Yes or No

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82


Check

Point







IRM49 Does the bus_mngr_id field (bits 26-31) contain the tester

nodes physical ID?

Yes or No

Check

Point If you answered “No” to IRM49 then the tester node is

not SBM. Stop BUS_MANAGER_ID test! If

appropriate, repeat test and force Tester to SBM.


BUS_MANAGER_ID register. The arg_value should be

3F16 and data_value should contain the tester nodes

physical ID. The register is located at:




Yes or No

Check

Point

If you answered “No” to IRM410, IUT failed the lock

of BUS_MANAGER_ID register. FAILURE, Stop






equal the tester node‘s physical ID?

Yes or No

Check

Point

If you answered “No” to IRM411, IUT incorrectly

handled the compare and swap operation. FAILURE!

Stop BUS_MANAGER_ID test!

IRM412 At S100 speed, write the BUS_MANAGER_ID CSR with

3F16 using the following address:



Is the rcode for each write response packet 616?

Yes or No

Check

Point


responded to the write of BUS_MANAGER_ID

registers. FAILURE!


located at address:




Yes or No

Check

Point







IRM414 Does the bus_mngr_id field (bits 26-31) contain the tester

node‘s physical ID?

Yes or No

Check If you answered “No” to IRM414, then the write of the

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Point BUS_MANAGER_ID register changed its value.

FAILURE!

5.2.4.5 BANDWIDTH_AVAILABLE Test Procedure

The active Isochronous Resource Manager (IRM) maintains the BANDWIDTH_AVAILABLE register. As

previous described, of all the competing IRM capable nodes, only one becomes the active IRM. This set of

tests verifies the following:

- Verify BANDWIDTH_AVAILABLE register only supports quadlet read and lock compare and

swap

- Verify the allocation/deallocation of bandwidth resource

- Verify value of maximum bandwidth after bus reset

- Verify operation if arg_value is incorrect


Reference

IRM51 Note: the IUT may automatically allocate resources after

a bus reset. When the IUT is also IRM it may be difficult

to access the BANDWIDTH_AVAILABLE register

before IUT‘s application allocates resources.

- 8.4.31. and 8.4.3.2

IRM52 Force IUT to become IRM. -


IRM54 At S100 speed, read the BANDWIDTH_AVAILABLE

CSR located at address:




Yes or No

Check

Point


of BANDWIDTH_AVAILABLE registers. FAILURE,

Stop BANDWIDTH_AVAILABLE test!




IRM55 Did IRM automatically reserve at least 23.27μsec (1388h)

for asynchronous bandwidth? The value read will be

called ―IUT Initial Value‖.

Yes or No

Check

Point

If you answered “No” to IRM55, the value obtained

didn’t include the 23.27μsec reserved for

asynchronous traffic. Failure!


BANDWIDTH_AVAILABLE. The arg_value should be

IUT Initial Value and the data_value should be the IUT

Initial Value shift right four bits. The register is located at:





8.4.3

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84


Check

Point


BANDWIDTH_AVAILABLE register. FAILURE,






equal the arg_value sent in the request packet?

Yes or No

Check

Point

If you answered “No” to IRM57, the compare and


BANDWIDTH_AVAILABLE test!






Yes or No

Check

Point







IRM59 Does the bw_remaining field (bits 19-31) contain the

data_value of the lock operation executed on line IRM58?

Yes or No

Check

Point

If you answered “No” to IRM59, IUT didn’t retain the

value written during the lock operation. FAILURE,



BANDWIDTH_AVAILABLE register. The arg_value

should be the data_value from line IRM56 and the

data_value should contain all zeros (all bandwidth

allocated). The register is located at:




Yes or No

Check

Point


of BANDWIDTH_AVAILABLE register. FAILURE,






equal the data_value from link IRM56?

Yes or No

Check

Point









Yes or No

1394 TA 2002005 Revision 2.3


Check

Point








data_value of the lock operation executed on line

IRM510?

Yes or No

Check

Point

If you answered “No” to IRM513, IUT didn’t retain

the value written during the lock operation.

FAILURE, Stop BANDWIDTH_AVAILABLE test!


BANDWIDTH_AVAILABLE register. The arg_value

should be the data_value from line IRM510 and the

data_value should contain 4915. The register is located at:




Yes or No

Check

Point









Yes or No

Check

Point









Yes or No

Check

Point








data_value of the lock operation executed on line

IRM514?

Yes or No

Check

Point



FAILURE, Stop BANDWIDTH_AVAILABLE test!

IRM518 At S100 speed, write the BANDWIDTH_AVAILABLE

CSR with all zeros using the following address:




Yes or No

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86


Check

Point


responded to the write of BUS_MANAGER_ID

registers. FAILURE!






Yes or No

Check

Point








4915?

Yes or No

Check

Point

If you answered “No” to IRM520, then the write of the

BANDWIDTH_AVAILABLE register changed its

value. FAILURE!


BANDWIDTH_AVAILABLE. The arg_value should be

all zeros and the data_value should be the IUT Initial

Value shift right four bits. The register is located at:





8.4.3

Check

Point








equal the 0000133316?

Yes or No

Check

Point

If you answered “No” to IRM522 the compare and








Yes or No

Check

Point








value of 4915 (133316)?

Yes or No

Check

Point

If you answered “No” to IRM524, IUT compare and

swap operation altered the value of the

1394 TA 2002005 Revision 2.3


BANDWIDTH_AVAILABLE register. FAILURE!

5.2.4.6 CHANNELS_AVAILABLE Test Procedure

The active Isochronous Resource Manager (IRM) maintains the CHANNELS_AVAILABLE_HI and

CHANNELS_AVAILABLE_LO register. As previous described, of all the competing IRM capable nodes,

only one becomes the active IRM. This set of tests verifies the following:

- Verify CHANNELS_AVAILABLE register only supports quadlet read and lock compare and

swap

- Verify the allocation/deallocation of channel resources

- Verify all channels are deallocated after bus reset

o IEEE-1394a-2000: ffff_fffe (channel 31 allocated for async_streams)

o IEEE-1394-1995: ffff_ffff

- Verify operation if arg_value is incorrect


Reference

IRM61 Note: the IUT may automatically allocate resources after

a bus reset. When the IUT is also IRM, it may be difficult

to access the CHANNELS_AVAILABLE registers before

IUT‘s application allocates resources.

-

IRM62 Force IUT to become IRM. -


IRM64 At S100 speed, read both the

CHANNELS_AVAILABLE_HI and LO CSRs located at

address:


Destination offset low = f000_022416/ f000_022816


Yes or No

Check

Point


of CHANNELS_AVAILABLE_HI or LO register.

FAILURE, Stop CHANNELS_AVAILABLE test!




- The values read in line IRM64 will be referred to as Initial

Value HI and LO.

-

- If not an Enhanced IRM node, skip to step IRM66.

IRM65 If Enhanced IRM node, is Channel 31 of the

CHANNELS_AVAILABLE_HI reserved?

Yes or No

Check

Point

If you answered “No” to IRM65, channel 31 wasn’t set

and it should have been. Please proceed to next

question.


CHANNELS_AVAILABLE_HI and LO registers. The

arg_value should be IUT Initial Value HI and LO and the

data_value should be aaaaaaaa16 for both lock operations.

The registers are located at:



Is the rcode for the lock response packets 016?


8.4.3

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88


Check

Point


CHANNELS_AVAILABLE_HI or LO registers.





IRM67 Does the old_value returned in the lock response packets

equal the arg_value sent in the request packets?

Yes or No

Check

Point



CHANNELS_AVAILABLE test!

IRM68 At S100 speed, read the CHANNELS_AVAILABLE_HI

and LO CSRs located at address:




Yes or No

Check

Point


of CHANNELS_AVAILABLE_HI or LO registers.





IRM69 Does the read response payloads executed on line IRM68

equal the data_value of the lock operation executed on

IRM66?

Yes or No

Check

Point

If you answered “No” to IRM69, IUT didn’t retain the

value written during the lock operations. FAILURE,

Stop CHANNELS_AVAILABLE test!


CHANNELS_AVAILABLE_HI and LO registers. The

arg_value should be the data_value from line IRM66 and

the data_value should contain the IUT Initial Value. The

register is located at:




Yes or No

Check

Point


of CHANNELS_AVAILABLE registers. FAILURE,







Yes or No

Check

Point





and LO CSR located at address:




Yes or No

1394 TA 2002005 Revision 2.3


Check

Point







IRM613 Do the values read equal the IUT Initial Value HI and

LO?

Yes or No

Check

Point




IRM614 At S100 speed, write the CHANNELS_AVAILABLE_HI

and LO CSR with all zeros using the following address:




Yes or No

Check

Point


responded to the write of CHANNELS_AVAILABLE

registers. FAILURE!


and LO CSR located at address:




Yes or No

Check

Point







IRM616 Do the values read equal the IUT Initial Value HI and

LO?

Yes or No

Check

Point

If you answered “No” to IRM616, then the write of the

CHANNELS_AVAILABLE register changed the

values. FAILURE!


CHANNELS_AVAILABLE_HI and LO. Both the

arg_value and data_value should be all zeros. The register

is located at:





8.4.3

Check

Point








equal IUT Initial Value HI and LO?

Yes or No

Check

Point



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90




and LO CSRs located at address:




Yes or No

Check

Point







IRM620 Do the payloads of each read response match those of the

IUT Initial Value HI and LO?

Yes or No

Check

Point

If you answered “No” to IRM620, IUT compare and

swap operation altered the value of the

CHANNELS_AVAILABLE registers. FAILURE!

5.2.4.7 BROADCAST_CHANNEL Test Procedure

The active Isochronous Resource Manager (IRM) maintains its BROADCAST_CHANNEL register and

may also access other nodes BROADCAST_CHANNEL register. As previous described, of all the

competing IRM capable nodes, only one becomes the active IRM. This set of tests verifies the following:

- Verify bit 0 is read only

- Verify bit 1 (valid) is read/write

- Verify only supports quadlet read and write transactions

- CHANNELS_AVAILABLE_HI channel 31 (bit 31) is 0 by default

- Verify the valid (v) bit is set to one (1) once channel 31 is allocated in

CHANNELS_AVAILABLE_HI register.

- Verify channel field (bits 26 –31) is by default 31


Reference

IRM71 Note: This test assumes you answered ―Yes‖ to IRM34. -

IRM72 Force IUT to become root. -

IRM73 At S100 speed, read the BROADCAST_CHANNEL






8.3.2.3.11

Check

Point


of BROADCAST_CHANNEL register. FAILURE,

Stop BROADCAST_CHANNEL test!




IRM74 Is the valid (v) bit set to 1 in the read response packet? Yes or No

Check

Point

If you answered “No” to IRM74, IUT has not

allocated channel 31 in the

CHANNELS_AVAILABLE_HI CSR and set the valid

bit! FAILURE! Stop BROADCAST_CHANNEL test.

IRM75 At S100 speed, read the BROADCAST_CHANNEL Yes or No

1394 TA 2002005 Revision 2.3






Check

Point







IRM76 Is the channel field (bits 26-31) in the read response

packet set to 31?

Yes or No

Check

Point

If you answered “No” to IRM76, IUT did not set

channel field to the default value! FAILURE! Stop

BROADCAST_CHANNEL test.







8.3.2.3.8

Check

Point


of CHANNELS_AVAILABLE_HI register.

FAILURE, Stop BROADCAST_CHANNEL test!

Note: Examine the rcode, if it is 4 possible but rare

condition occurred perhaps retry transaction.

IRM78 Is the channel field (bit 31) in the read response packet

set to zero (0)?

Yes or No

Check

Point

If you answered “No” to IRM78, IUT did not allocate

channel 31 even though valid bit is set. FAILURE!

Stop BROADCAST_CHANNEL test.

IRM79 At S100 speed, write the BROADCAST_CHANNEL

CSR with 3fffffc016 The CSR is located at address:



Is the rcode of the write response packet 016?

Yes or No

Check

Point

If you answered “No” to IRM79, IUT failed the write

of BROADCAST_CHANNEL register. FAILURE!










Yes or No

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92


Check

Point







IRM711 Is the value of the read response payload 8000001f16? Yes or No

Check

Point


handled the write to the BROADCAST_CHANNEL

register. FAILURE!

IRM712 At S100 speed, write the BROADCAST_CHANNEL

CSR with c000001f16 The CSR is located at address:




Yes or No

Check

Point

If you answered “No” to IRM712, IUT failed the write

of BROADCAST_CHANNEL register. FAILURE!










Yes or No

Check

Point







IRM714 Is the value of the read response payload c000001f16? Yes or No

Check

Point

If you answered “No” to IRM714 IUT incorrectly

handled the write to the BROADCAST_CHANNEL

register. FAILURE!

5.2.4.8 Gap_count Opt imizat ion Test Procedure

Before IEEE-1394b-2002 the Serial Bus Manager, or in the absence of the Serial Bus Manager the

Isochronous Resource Manager, could optimize the 1394 bus timing by referencing a table that correlated

number of hops to optimum gap_count. While this method wasn‘t perfect it was adequate. IEEE-1394b-

2002 added flexibility of media type, distances and repeater delays which make the table referred to above

invalid. However, IEEE-1394a-2000 created a Ping transaction that can be used to measure round trip time

from the originator of the Ping PHY request packet to receipt of the Ping response packet. Implementations

such as OHCI provide timing capability for primary asynchronous packets which also allow the same round

trip timing functionality. Depending on the originators location and the bus topology multiple

measurements maybe required to determine the maximum round trip delay between any two nodes on the

bus.

1394 TA 2002005 Revision 2.3


Figure 39: Gap_count short haul test topology

Figure 40: Gap_count optical test topology


Reference

IRM81 Note: This test assumes you answered ―Yes‖ to IRM34. -

IRM82 No Tester node shall be SBM capable for this test. -

IRM83 Connect IUT to Tester 1 through 3 and 8 as shown in

Figure 39 or Tester 3 and 8 as shown in Figure 40.

-

IRM84 Force IUT to become SBM and or IRM. -

IRM85 Connect Tester 4 through 7 as shown in Figure 39 or

Tester 7 as shown in Figure 40. Does IUT send a PHY

Configuration packet setting the gap_count?

Yes or No IEEE-1394-1995

4.3.4.3

Check

Point

If you answered “No” to IRM85 IUT didn’t send a

PHY Configuration packet to set gap_count.

Warning! End test.

IRM86 Did IUT set the gap to an appropriate9 value for the

topology?


Annex E.1

Check

Point

If you answered “No” to IRM86 IUT didn’t set the

gap_count to an appropriate setting. Failure!

5.2.5 Bus Manager Capable Node

Bus Manager (BM) capable nodes shall have the bmc bit in the Bus_Info_Block set to one. BM capable

nodes shall implement the following CSRs:

9 The appropriate value is 0x3F to the smallest value possible for the specified topology.

IUT

Tester3 Tester7

Tester8

Optical Connection

Tester2

IUT

Tester1 Tester3 Tester4 Tester5 Tester6 Tester7

Tester8

1394 TA 2002005 Revision 2.3

94


- Same CSRs as IRM capable nodes plus

- TOPOLOGY_MAP

- Abdicate bit within STATE_CLEAR register (IEEE-1394A-2000)

In addition a BM Capable node must participate in the BM selection process.

The active Bus Manager (BM), should be able to perform the following functions:


- Limited power management

o Set the linkoff bit in the bus_depend field of the STATE_CLEAR register to 1

o Issue a link_on packet

o Set a node‘s force root flag true (10.27)

Used to:

Make the root a Cycle Master Capable node

Select root that supports enhanced IRM functions

(BROADCAST_CHANNEL register).

5.2.5.1 SBM General ROM Support Test Procedure


Reference

BM11 At S100 speed, read one quadlet from address:



Is the bmc (bit 3) field set to 1?

Yes or No 8.3.2.5.4

Check

Point

If you answered “No” to BM11 then IUT is not a BM

contender node. Stop Bus Manager test here.

BM12 At S100 speed, write a 0 to the bmc field at the following

address:






Is the bmc (bit 1) field set to 1?

Yes or No

Check

Point

If you answered “No” to BM12, then bmc is not a read

only location. FAILURE!

5.2.5.2 Bus Manager Determinat ion Test Procedure

Determining which node will be Bus Manager (BM) employees the following process:

After each bus reset and the associated initialization completes, candidate BM nodes determine which node

is the active IRM and execute a compare and swap lock request addressed to the BUS_MANAGER_ID

CSR located in that node. Within the lock request the arg_value (compare value) is 0x3F and the

data_value (swap value) is the lock requesters physical ID.

The IRM processes the lock request and returns a lock response. If the Response Code is resp_complete

and the old_value is 0x3F or the requesting node’s physical ID, then the requesting node is the active Bus

Manager. However, if the Response Code is resp_complete and the old_value is not 0x3F or the requesting

node’s physical ID, then the requesting node is not the active BM and the old_value received contains the

physical ID of the active BM.

1394 TA 2002005 Revision 2.3


5.2.5.2.1 Stabi lity of Bus Manager

Bus Manager capable nodes are not necessarily equal. Because capabilities can vary it is important that the

best BM is selected and once selected remains the active BM. IEEE-1394 provides two provision that make

this possible.

- Incumbent BM

The incumbent BM, the BM prior to the bus reset, may start the lock request to the IRM’s

BUS_MANAGER_ID CSR immediately after bus initialization. All other BM candidate nodes

shall wait 125ms before they attempt the lock request.

- Abdication by the Bus Manager

At some point a node, presumably (determination of capability is beyond the scope of IEEE-1394)

with better BM capabilities than the current BM, may want to become BM. In this case, it may be

desirable to have the more capable node become BM. To do this:

a) The more capable node sets the BM’s abdicate bit to one. The abdicate bit is located in the

STATE_CLEAR CSR.

b) Next it initiates a bus reset (short bus reset is preferred).

c) The incumbent BM seeing its abdicate bit set to one waits 125ms before it attempts to become the

BM. The more capable node does not wait and should become the BM.

d) If the node is still not BM, it shall repeat step a), send a PHY Configuration packet forcing itself to

become root10

then execute steps b) and c).


Reference

BM21 Start with IUT not connected to the test environment -

BM22 Note: the following test procedure assumes the Tester

node is the incumbent fully capable BM and enhanced

IRM when IUT is connected to the bus.

-

BM23 Connect IUT to the test environment -

BM24 Verify the IUT waits 125ms before attempting a lock

operation on the BUS_MANAGER_ID register found in

the active IRM.

Did IUT wait 125ms before attempting a lock transaction

on the BUS_MANAGER_ID register?

Yes or No 8.4.2.5

Check

Point

If you answered “No” to BM24, then IUT did not wait

the correct amount of time. FAILURE!

BM25 Did IUT attempt to access the BUS_MANAGER_ID

register?

Yes or No

Check

Point

If you answered “No” to BM25, then IUT did not

attempt to become the Bus Manager. FAILURE! Stop

Bus Manager test!

BM26 Force the tester node to not compete to become BM but

should present itself as an enhanced IRM and root.

-

BM27 Initiate a bus reset -



the active IRM.


Yes or No 8.4.2.5

10 Being root, the node will be IRM and has the highest arbitration priority. This should allow the node to win

arbitration and execute the lock request to the BUS_MANAGER_ID CSR first. This operation should only be needed if

the incumbent BM doesn‘t implement the abdicate bit; i.e., it‘s an IEEE-1394-1995 implementation.

1394 TA 2002005 Revision 2.3

96



Check

Point



BM29 Is the IUT the active Bus Manager? Yes or No

Check

Point



Bus Manager test!

BM210 Force the tester node to not compete to become BM but

should present itself as an enhanced IRM and root.

-


BM212 Verify IUT attempts a lock operation on the

BUS_MANAGER_ID register found in the active IRM

within 125ms (after the completion of the bus initialization

process).

Did IUT attempting a lock transaction on the

BUS_MANAGER_ID register within 125ms?

Yes or No 8.4.2.5

Check

Point


execute lock transaction quickly enough. FAILURE!

BM213 Is the IUT the active Bus Manager? Yes or No

Check

Point



Bus Manager test!

BM214 Did you answer ―Yes‖ to IRM34? Yes or No

Check

Point

If you answered “No” to BM214, then IUT doesn’t

support 1394a functions. Stop Bus Manager test!

BM215 At S100 speed, write the STATE_SET CSR setting the

abdicate bit. The CSR is located at address:




Yes or No

Check

Point

If you answered “No” to BM215, IUT failed the write

of STATE_SET register. FAILURE! Stop Bus

Manager test here!




BM216 At S100 speed, read the STATE_CLEAR CSR located at

address:





8.3.2.2.1

Check

Point

If you answered “No” to BM216, IUT failed the read of

STATE_CLEAR register. FAILURE, Stop Bus

Manager test!




BM217 Is the abdicate bit set in read response payload? Yes or No

Check

Point

If you answered “No” to BM217, IUT doesn’t support

the abdicate bit. FAILURE, Stop Bus Manager test!

BM218 Note: The following test procedure assumes the Tester

node is a fully capable BM and enhanced IRM. It also

assumes the Tester will compete to become BM faster than

- IEEE-1394a-2000

8.5.4

1394 TA 2002005 Revision 2.3


125ms.




the active IRM.



Yes or No

Check

Point



BM221 Did IUT attempt to access the BUS_MANAGER_ID

register?

Yes or No

Check

Point

If you answered “No” to BM221 then IUT did not


Bus Manager test!

5.2.5.3 TOPOLOGY_MAP CSR Test Procedure

The active BM owns the active TOPOLOGY_MAP registers located at 1000h to 13FCh. The following test

procedure tests the following:

- Verify only supports read requests (perhaps read block).

- Use length field to read the data and calculate the CRC; compare that with the CRC found in the

TOPOLOGY_MAP register.

- Verify that the generation_number increments with each bus reset

- Verify that the node_count field is equal to the number of self-IDs found in the topology map

(Tested in Network Interoperability Test Suite) - Verify that the self_id_count is equal to number of self-ID packets found in the topology map

(remember wide PHY can have more then one packet represent them). (Tested in Network

Interoperability Test Suite) - Verify that the self-ID packets found in the self_id_packet fields are consistent with the Tester‘s

representation. (Tested in Network Interoperability Test Suite)


Reference




Is the rcode value in the read response 016?

Yes or No 8.3.2.4.1

Check

Point

If you answered “No” to IRM31, IUT failed the read of

TOPOLOGY_MAP register. FAILURE, Stop

Topology Map test!




BM32 Is the value of bits 0-15 greater than 2? Yes or No

Check

Point

If you answered “No” to BM32, IUT doesn’t support

the TOPOLOGY_MAP. FAILURE! Stop Topology

Map test!

BM33 Record the value of bits 0-15 in length variable. -

BM34 Record the value of bits 16-31 in CRC variable. -

BM35 At S100 speed, using read quadlet requests, read a length

number of quadlets starting at address:


-

1394 TA 2002005 Revision 2.3

98



BM36 Calculate the CRC on the data read in step BM35.

Is the calculate CRC the same is CRC?

Yes or No

Check

Point

If you answered “No” to BM36, CRC value is

incorrect. Repeat steps starting at BM33 and if the

same value is obtained the CRC value is incorrect.

FAILURE! Stop Topology Map test!

BM37 At S100 speed, using read block request(s) read a length

(use the max_ROM value to determine maximum block

size) number of quadlets starting at address:



Is the data read in this step constant with the data read in

step BM35?

Yes or No

Check

Point

If you answered “No” to BM37, IUT didn’t correct

support block access of the Topology Map. FAILURE!

BM38 At S100 speed, using write quadlet requests write a length

number of quadlets with ffffffff16 starting at address:



-

BM39 At S100 speed, using read quadlet requests read a length




-

BM310 Is the data read in this step constant with the data read in

step BM35?

Yes or No

Check

Point

If you answered “No” to BM310, IUT’s

TOPOLOGY_MAP register isn’t read only.






Yes or No 8.3.2.4.1

Check

Point


of TOPOLOGY_MAP register. FAILURE, Stop

Topology Map test!




BM312 Record the value of bits 0-31 in generation_number

variable.

-

BM313 Initiate a bus reset. -





Yes or No 8.3.2.4.1

Check

Point


of TOPOLOGY_MAP register. FAILURE, Stop

Topology Map test!




BM315 Is the value read in step BM314 greater than the value in Yes or No

1394 TA 2002005 Revision 2.3


the generation_number?

BM316 Repeat steps BM312 – BM315 10 times. -

Check

Point

If you answered “No” to BM315 more than once (roll

over case), IUT incorrectly implemented the

generation_number. FAILURE! Stop Topology Map

test!





Yes or No 8.3.2.4.1

Check

Point

If you answered “No” to IRM31, IUT failed the read of

TOPOLOGY_MAP register. FAILURE, Stop

Topology Map test!




BM318 Record the value of bits 0-15 in length variable. -

BM319 Record the value of bits 16-31 in CRC variable. -

BM320 At S100 speed using read quadlet requests, read a length




-

BM321 Calculate the CRC on the data read in step BM317.

Is the calculate CRC the same is CRC?

Yes or No

Check

Point

If you answered “No” to BM321, CRC value is

incorrect. Repeat steps starting at BM317 and if the

same value is obtained the CRC value is incorrect.


5.2.5.4 Other Supported CSRs


o BUS_MANAGER_ID – see IRM section

o BANDWIDTH_AVAILABLE – see IRM section

o CHANNELS_AVAILABLE – see IRM section

o BROADCAST_CHANNEL – see IRM section

5.2.5.5 Bus Manager Responsibil it ies Test Procedure

The BM has several management functions that it may perform. Of them the following are required:

- Bus manager must insure that all nodes SPLIT_TIMEOUT registers are set to the same value

- Bus manager shall select and activate a cycle master

o It shall examine the Bus_Info_Block of the root node to determine if it is cycle master

capable

o If the root node does not have cycle master capabilities, the bus manager shall select a

node on the serial bus that has cycle master capabilities and force that node to become

root.

o If the root node is cycle master capable, the bus manager shall set the force_root flag of

the root node and set the cmstr bit in the STATE_CLEAR register.

- Bus manager must perform power management as follows:

o The total power requirement of the bus shall be calculated for the pwr fields in the self-ID

packets

1394 TA 2002005 Revision 2.3

100


o The total power available on the bus shall be calculated from the self-ID packets

o If the power requirements exceed the power available, an SB_EVENT.indiation with a

parameter that indicates Insufficient Cable Power shall be provided to the application at

the bus manager node

o If the power requirements are less than or equal to the power available, link-on packets

shall be transmitted to all nodes whose self-ID packet indicated an inactive link layer.

Optionally the bus manager can perform the following functions:



Reference

BM51 Note: The following test procedure assumes the Tester

node will allow the IUT to become BM.

-

BM52 Set the Tester node‘s SPLIT_TIMEOUT registers to a

value that is different from IUT‘s

- IEEE-1394a-2000

8.3.2.2.6

BM53 Initial a bus reset -

BM54 Is IUT the BM? Yes or No

Check

Point

If you answered “No” to BM54, IUT is not the bus

manager. FAILURE! Stop testing this section here!

BM55 Read IUT‘s SPLIT_TIMEOUT register -

BM56 Read the Tester‘s SPLIT_TIMEOUT register -

BM57 Are the IUT‘s and Tester‘s SPLIT_TIMEOUT register

values consistent?


8.3.2.2.6

Check

Point

If you answered “No” to BM57, IUT failed to make the

SPLIT_TIMEOUT value for all node consistent.

FAILURE

BM58 The following configuration is assume for this test:

Bus Analyzer---Tester---<IUT

-

BM59 Note: The following test procedure assumes Bus Analyzer

node is connected to an established topology with its

force_root flag true. Bus Analyzer node presents itself as

not being BMC, IRMC, or CMC. Tester node presents

itself as being CMC. (IUT is not connected at this time)

-

BM510 Connect IUT to the test environment -

BM511 Is IUT the BM? Yes or No

Check

Point

If you answered “No” to BM511, IUT is not the bus

manager. FAILURE! Stop testing this section here!

BM512 Did IUT force either itself or Tester to become root? Yes or No 8.4.2.6

Check

Point

If you answered “No” to BM512, IUT didn’t force a

CMC node to become the root node. FAILURE! Stop

testing this section here!

BM513 Did IUT set the root nodes cmstr bit in the

STATE_CLEAR register?

Yes or No

Check

Point

If you answered “No” to BM513, IUT didn’t set the

cmstr bit. FAILURE! Stop testing this section here!

1394 TA 2002005 Revision 2.3


Annexes

Annex A: Cable Power Tester Example Circuit (informative)

External power:

+/- 8 to 10VDC

C3

0 . 0 1 u F

+ 5 . 0 0 Vre f

Company: Quantum Paramet rics LLC. All rig hts reserved 200 2.

Designer: Daniel Stewart

U1

L M 4 0 4 0 -5 . 0 / SOT 2 3

21

R4

4 . 9 9 K

+

C2 4

1 0 0 u F / 2 0 V

Construct C1 (506uf) and C2 (619uf) with

descrete values to within 3uF.

D3

1 N4 0 0 1

< Do c > A

Ca b l e Po we r T e s te r - Po we r & Re fe re n c e

C

1 5T h u rs d a y , Au g u s t 2 6 , 2 0 0 4

T i tl e

Si z e Do c u m e n t Nu m b e r Re v

Da t e : Sh e e t o f

16.2mJ / 19.8mJ

R1 2 4

4 . 9 9 K

SW 1

Sl id e Swi tc h DPST

+ C2 0

2 2 0 u F / 2 5 V

Energy In-Rush Test Jig

VSS

SW 2L o a d s e le c t

1 2 3

Ca b l e GND

R2

4 . 8 5 o h m

+ C2

4 7 0 u F / 2 0 V

D2

1 N4 0 0 1

D1

POW ER ON

R3 0 o h m

Construct R1 and R2 with descrete

values to within 0.01 ohm

R1 2 5

2 . 7 4 K

VSS

NOTES:

All resistors: In ohms 1%, 1/8W unless otherwise

noted.

All capacitors: In Farad, 10% 16V unless otherwise

noted.

All IC Vcc pins to be bypassed with 0.01uF cap to GND.

All IC Vss pins to be bypassed with 0.01uF cap to GND.

All LED's: 1.8V, 2mA.

-5 .0 0 Vre f

+ C2 3

3 3 u F / 2 0 V

Power Swi tch

SW 1

L o a d Ap p ly

U2

L M 4 0 4 0 -5 . 0 / SOT 2 32

1

Normally closed

+ C2 2

n o t i n s ta l le d

C2 1

0 . 0 1 u F

F 1

1 / 2 A

Tip: -9VD C

Center: + 9VDC

R1

5 . 9 3 o h m

ON / OFF

+ C4

2 2 0 u F / 2 5 V

VCC

+

C2 5

4 7 u F / 2 0 V

VCC

+ C1

4 7 0 u F / 2 0 V

J 1

St e re o Ph o n e J a c k w/ s wi tc h

12345

As Re q u i re d

0 . 0 1 u F

F 2

1 / 2 A

Ca b l e PW R

Bypass caps (see notes)

Normally open

As Re q u ie d .

0 . 0 1 u F

1394 TA 2002005 Revision 2.3

102


D3

D2

D1

ac

XBP BP

Vss

-IN

+IN

u A V m

Kohm

dC

nc

C Mohm

GND

dF

BAT

hold1

hold2

RH

RL

Vdd

U5

2 V DPM (9 v p o we r)

1 2 3 4 5 6 7 8 9 10 11 12 1314151617181920212223242526

D P M O f f s e t

a d j u s t m e n t

RP1

1 M

12 3 4 5 6 7 8 9 10

SW 2

Sl id e Swi tc h 6 P3 T

1

232 2

2 3

2 4

5

76

42 1

8

1 6

1 51 41 3

2 0

1 91 81 7

9

1 01 11 2

VCC

Current Direction

Vr ip p l e

VCC

R6

2 . 7 4 K

R1 4

8 2 . 0 K

R1 61 M

D7

Si n k in g

D P M F u n c t i o n

S e l e c t o r

< Do c > A

Ca b l e Po we r T e s te r - DP M , Ri p p le s e n s e , Cu rre n t Di re c ti o n

C

2 5T h u rs d a y , Au g u s t 2 6 , 2 0 0 4

T i tl e



Vr ip p l e

R2 3

2 . 1 0 K

-

+

U3

L M 1 1 1

2

37

564 1

8

Ca b l e PW R

Vi

V o l t S e l e c t o r

R9

1 0 0

VCC

Ripple Detector(Peak to Peak)

R2 0

1 0 0 K

D4

So u rc in g

SW 3

Sl id e Swi tc h 4 P2 T

1

231 0

1 1

1 2

4

56

9

78

x 1

VCC

Ve / 1 0

V O L T S

VSS

VCC

W A T T S

Vp / 1 0

R2 2

1 . 0 0 M

R7

1 0 0

VR1

1 K

A M P S

+ C72 . 2 u F

R1 9

1 . 0 0 M

R1 8

2 . 1 0 K

-

+

U9

L M 1 1 1

2

37

564 1

8

V o l t a g e D C

VCC

C6

0 . 1 u F

VSS VR2

1 0 K

R i p p l e

VSS

Digital Panel Meter-

+

U4

L M 1 1 1

2

37

564 1

8

VSS

R1 7

9 . 5 3 K

R5

1 5 0 K

R8

4 9 . 9 K

VSS

D5

1 N9 1 4

R1 3 9 . 0 9 K

R1 0

2 . 7 4 K

U8

I NA1 2 8

23

4

6

7

518

-VIN+ VI N

V-

VO

V+

REFRGRG

C o m p a n y : Q u a n t u m P a r a m e t r i c s L L C . A l l r i g h t s r e s e r v e d 2 0 0 2 .

D e s i g n e r : D a n i e l S t e w a r t

Vi

+ C52 . 2 u F

VCC

VSS

R1 1

1 5 0 K

R1 51 M

D6

1 N9 1 4

D P M G a i n

a d j u s t m e n t

R2 1

n o t i n s ta l le d

R1 2 7 . 5 0 K

-

+

U6

L F 3 5 6 B

3

26

7 14 5

-

+

U7

L M 1 1 1

2

37

564 1

8

1394 TA 2002005 Revision 2.3


VR3

5 0 KVp / 1 0 0

8 5 . 4 K h z

Vp / 1 0

-Vp /1 0 0 + o f fs e t

C1 7

0 . 0 0 1 u F

U1 2

M N3 2 0 9

37

82

6

5

14

I NOUT 1

OUT 2CP1

CP2

Vdd

GN

DV

gg

VSS

V1 4 / 1 5

Vg n d

R3 6

1 0 . 0 K

R4 7

3 9 . 2 K

C1 5

1 0 0 p F

3 m S A n a l o g d e l a y

B a n d w i d t h : D C t o 1 2 k H z

R4 9

5 . 6 2 K

-

+

U1 0 A

L F 3 4 7

3

21

411

R4 4

5 . 6 2 K

-

+

U1 1 A

L F 3 4 7

3

21

411

R4 3

5 . 6 2 K

+

C1 6

0 . 3 3 u F

Vp / 1 0

C1 8

0 . 0 1 u F

R4 6

3 9 . 2 K

VCC

Energy InRush Detection

R2 8

1 0 K

R2 4

1 0 . 0 K

C1 3

1 2 0 0 p F

-

+

U1 1 B

L F 3 4 7

5

67

411

R3 8

1 . 1 0 K

R3 9

3 9 . 2 K

R5 3

1 0 0 K

R3 7

1 0 . 0 K

-

+

U1 1 C

L F 3 4 7

1 0

98

411

R3 2

3 9 . 2 K

R3 4

3 3 . 2 K

R4 8

3 3 . 2 K

R5 6

1 . 0 M

-

+

U1 0 B

L F 3 4 7

5

67

411

E n e r g y I n t e g r a t o r

( - 1 0 0 v o l t s / s e c

p e r w a t t )

Vg n d

-Vp /1 0 (d e la y e d )

R3 5

1 4 0 K

C1 4

1 5 0 0 Pf

-

+

U1 0 C

L F 3 4 7

1 0

98

411

R5 1

5 . 6 2 K

R5 5

1 0 . 0 K

R5 2

1 0 . 0 K

C1 0

1 5 0 0 Pf

U1 5

L M 5 5 5 /SO

3

4

8

5

26

7OUT

RST

VCC

CV

T RGT HR

DSCHG

L o w P a s s F i l t e r

-

+

U1 3

L F 3 5 6 B3

26

7 14 5

< Do c > A

Ca b l e Po we r T e s te r - En e rg y In Ru s h De t e c ti o n

C

3 5T h u rs d a y , Au g u s t 2 6 , 2 0 0 4

T i tl e



C9

1 2 0 0 p F

R5 0

1 0 0 K

VCC

C1 1

1 0 0 p F

L o w P a s s F i l t e r

VCC

C o m p a n y : Q u a n t u m P a r a m e t r i c s L L C . A l l r i g h t s r e s e r v e d 2 0 0 2 .

D e s i g n e r : D a n i e l S t e w a r t

Vp / 1 0 0 + o ff s e t (d e l a y e d )

R2 6

3 9 . 2 K

R2 5

1 0 . 0 K

R2 9

3 3 . 2 K

R4 2

1 0 0 K

VSS

VR4

1 0 K

R3 1

4 3 . 2 K

U1 4 A

4 0 1 3 / SO

5

3

12

1 4

6

7

4

D

CL K

QQ

VDD

S

GND

R

-Vm J / 1 0

R3 0

1 0 . 0 K

R4 5

4 3 . 2 K

R5 4

1 0 . 0 K

R3 3

3 9 . 2 K

-

+

U1 0 D

L F 3 4 7

1 2

1 31 4

411

Vp / 1 0 0 + o ff s e t

R4 1

1 0 0 K

C8

1 0 0 0 p F

VSS

R4 0

1 0 . 0 K

R2 7

1 0 0 K

C1 2

1 0 0 0 p F

1394 TA 2002005 Revision 2.3

104


VCC

Power /Current/EnergyDetectors

VCC

-

+

U2 8

L M 1 1 1

2

37

564 1

8

R6 9

2 0 . 0 K

-

+

U2 4

L M 1 1 1

2

37

564 1

8

VCC

R6 7

1 . 0 0 K

R7 2

2 0 . 0 K

R9 3

2 0 . 0 K

U1 7 B

4 0 1 3 / SO

9

1 1

1 31 2

1 4

8

7

1 0

D

CL K

QQ

VDD

S

GND

R

0.8V

VCC

R6 4

2 . 7 4 K

R7 3

2 . 0 5 K

D1 0

Ex c e e d s 3 3 Vo u t

-5 .0 0 Vre f

Ve / 1 0

Be l o w7 .5 VI n

R8 3

2 . 7 4 K

R8 2

6 . 4 9 K

-

+

U2 0

L M 1 1 1

2

37

564 1

8

Ex c e e d s 1 . 5 As o u rc e

Ex c e e d s 1 V ri p p le Ou t

3.3V

VCC

VCC

VCC

VCC

VCC

VCC

VSS

(18mJ)

4.0V

VCC

VCC

Vi

< Do c > A

Ca b l e Po we r T e s te r - T ri p I n d ic a to rs

C

4 5T h u rs d a y , Au g u s t 2 6 , 2 0 0 4

T i tl e



VSS

-Vm J / 1 0

R7 9

2 . 9 4 K

R8 6

2 . 7 4 K

R6 1

2 . 7 4 K

U2 1 B

4 0 1 3 / SO

9

1 1

1 31 2

1 4

8

7

1 0

D

CL K

QQ

VDD

S

GND

R

D1 2

Be l o w8 Vo u t

R5 9

2 0 . 0 K

R8 1

2 0 . 0 K

-

+

U2 2

L M 1 1 1

2

37

564 1

8

R5 7

1 0 . 0 K

-

+

U1 6 A

L M 3 3 9 /SO

7

61

312

Test Dete ctors

Vr ip p l e

-

+

U2 5 B

L M 3 3 9 /SO

5

42

312

Ex c e e d s 1 W s i n k

VCC

+ 5 . 0 0 Vre f

VCC

Ex c e e d s 3 3 Vo u t

Voltage Detectors

R7 8

2 0 . 0 K

R6 2

2 0 . 0 K

D8

Ex c e e d s 4 0 Vin

U1 4 B

4 0 1 3 / SO

9

1 1

1 31 2

1 4

8

7

1 0

D

CL K

QQ

VDD

S

GND

R

R5 8

2 . 7 4 K

D1 1


VCC

VCC

VCC

VCC

VCC

VCC

Company: Quantum Paramet rics LLC. All ri ghts reserved 200 2.


VCC

VSS

R7 6

5 4 9

R6 5

2 0 . 0 K

-

+

U1 8

L M 1 1 1

2

37

564 1

8

R6 3

6 . 9 8 K

-1 .8 VEx c e e d s 1 8 m J I n ru s h

D1 6

Ex c e e d s 1 V ri p p le

R9 5

2 0 . 0 K

-

+

U2 5 A

L M 3 3 9 /SO

7

61

312

R7 4

2 . 7 4 K

R1 2 3

2 0 . 0 K

R6 8

2 . 7 4 K

R8 9

2 0 . 0 K

SW 4

M o m e n t a ry Swi tc h (n o rm a l l y o p e n )

SW 8

M o m e n t a ry Swi tc h (n o rm a l l y o p e n )

Reset Det ectors

D1 3


R9 1

2 0 . 0 K

R9 6

1 5 . 0 K

D1 7

Ex c e e d s 1 0 W s i n k

U1 9 A

4 0 1 3 / SO

5

3

12

1 4

6

7

4

D

CL K

QQ

VDD

S

GND

R

U2 1 A

4 0 1 3 / SO

5

3

12

1 4

6

7

4

D

CL K

QQ

VDD

S

GND

R

R7 5

2 0 . 0 K

U1 9 B

4 0 1 3 / SO

9

1 1

1 31 2

1 4

8

7

1 0

D

CL K

QQ

VDD

S

GND

R

1.0V

Vp / 1 0

VCC

VCC

VCC

VCC

VCC

VCC

VSS

0.6V

Ex c e e d s 1 0 W s i n k

R9 2

2 . 7 4 K

VCC

VCC

VSS

U2 6 B

4 0 1 3 / SO

9

1 1

1 31 2

1 4

8

7

1 0

D

CL K

QQ

VDD

S

GND

R

U1 7 A

4 0 1 3 / SO

5

3

12

1 4

6

7

4

D

CL K

QQ

VDD

S

GND

R


0.3V

+ 5 . 0 0 Vre f

R9 4

2 0 . 0 K

-

+

U1 6 B

L M 3 3 9 /SO

5

42

312

R7 0

2 4 . 9 K

R8 5

4 . 0 2 K

R9 0

3 4 . 8 K

U2 3 A

4 0 1 3 / SO

5

3

12

1 4

6

7

4

D

CL K

QQ

VDD

S

GND

R

U2 3 B

4 0 1 3 / SO

9

1 1

1 31 2

1 4

8

7

1 0

D

CL K

QQ

VDD

S

GND

R

VCC

0.1V

I s So u rc i n g

VCC

R8 0

2 . 7 4 K

R6 6

3 1 . 6 K

R8 4

2 0 . 0 K U2 6 A

4 0 1 3 / SO

5

3

12

1 4

6

7

4

D

CL K

QQ

VDD

S

GND

R

VCC

VCC

VCCVCC

VCC

R8 8

2 0 . 0 K

R7 1

2 . 7 4 K

-

+

U2 7

L M 1 1 1

2

37

564 1

8

R9 7

2 . 0 0 K

R8 7

1 . 0 0 K

R9 93 4 0 K

-

+

U1 6 C

L M 3 3 9 /SO

9

81 4

312

1.5V

VCC


D1 5


VCC

VSS

Vi

Be l o w8 Vo u t

0.1V

D1 8

Ex c e e d s 1 . 5 As o u rc e

D9

Ex c e e d s 1 8 m J I n ru s h

VCC

D1 4

Be l o w7 .5 VI n0.75V

VCC

VCCR6 0

1 8 . 2 K

R7 7

2 . 7 4 K

-

+

U1 6 D

L M 3 3 9 /SO

1 1

1 01 3

312

- 5 .0 0 Vre f

I s Sin k i n g

VCC

I s Sin k i n g

VCC

VSS

R9 81 K

-

+

U2 9

L M 1 1 1

2

37

564 1

8

VCCEx c e e d s 4 0 Vin

1394 TA 2002005 Revision 2.3


VSS

Current

VSS

CN5

123456

7

8

VPVG

T PB-T PB+T PA-T PA+

SH7

SH8

Vp / 1 0

VCC

Voltage / Current / Power Sensing

U3 0

I NA1 2 8

23

4

6

7

518

-VIN+ VI N

V-

VO

V+

REFRGRG

Press Bot h for 45W or 2.0A

Ca b l e GND

R1 1 0 1 0 . 0 K

CN1

123456

7

8

VPVG


SH7

SH8

R1 2 1 2 0 . 0 K

R1 0 2

0 . 0 1 o h m , 1 % ,1 W

SW 7

Sl id e Swi tc h SPDT

1

23

-

+

U3 1 A

L F 3 4 7

3

21

411 R1 1 2

3 0 . 1 K

R1 1 8 4 9 9

From

DUT

External Cable power source .

R1 1 42 8 . 0 K

R1 2 0 2 0 . 0 K

R1 1 9

9 . 5 3 K

CN8

861234

1 3

1 2

1 01 1

95

7

VPVGT PB-T PB+T PA-T PA+

SHo u t 1 3

SHo u t 1 2

SHi n 1 0SHi n 1 1T PBre tT PAre t

SC

R1 1 3 1 2 . 4 K

Power

R1 0 7 2 0 . 0 K

R1 0 1 1 0 0 K

R1 1 1

8 2 . 0 K

x1

To

DUT

Ca b l e PW R

< Do c > A

Ca b l e Po we r T e s te r - 1 3 9 4 V, I , P s e n s e & Ac t iv e lo a d

C

5 5T h u rs d a y , Au g u s t 2 6 , 2 0 0 4

T i tl e



R1 1 5

No t i n s ta l le d

-

+

U3 1 B

L F 3 4 7

5

67

411

R1 1 7 5 1 1

R1 0 6 2 0 . 0 K

VCC

Ca b l e PW R

To

DUT

VCC

C1 9

0 . 0 1 u F

+ 5 . 0 0 Vre f

VSS

CN3

123456

7

8

VPVG


SH7

SH8

VSS

Q1I RF 7 4 0

CN6

123456

7

8


SH7

SH8

30 Watts or 1.33 Amps

VSS

SW 5

Pu s h Bu t to n 2 PST

VCC

Connect t o DUT with multipl e

cables if attempting to Loa d

DUT to > 15 Watts.

R1 1 6 1 0 . 0 K

Ca b l e GND

Active Load

U3 3

AD6 3 3 / SO

578124

63

WX1X2Y1Y2Z

+ VCC-VCC

15 Watts or 0.66 Amps

J 3

Ba n a n a J a c k (Re d )1

Load Mode

R1 0 8

7 . 5 0 K

From

DUT

R1 0 3 4 9 . 9 K

U3 2

I NA1 2 8

23

4

6

7

518

-VIN+ VI N

V-

VO

V+

REFRGRG

x2.25

Ve / 1 0VR5

1 K

R1 0 9 4 4 . 2 K

From

DUT

Vi

Mount wit h suitable

heat sink to disipate

45W.

R1 0 01 5 0 K

CN2

123456

7

8


SH7

SH8

Vi

To

DUT

CN7

861234

1 3

1 2

1 01 195

7

VPVG


SHo u t 1 3

SHo u t 1 2

SHi n 1 0SHi n 1 1T PBre tT PAre t

SC

x100

SW 6

Pu s h Bu t to n 2 PSTR1 0 5 5 1 1

Company: Quantum Parametri cs LLC. All rights reserved 2002.


VSS

R1 0 4 0 o h m

J 2

Ba n a n a J a c k (Bl a c k )1

x1

VCC

-

+

U1 1 D

L F 3 4 7

1 2

1 31 4

411

R1 2 29 . 0 9 K

Adjust fo r Ve/10 =

10.0% of CablePower

voltage.

CN4

123456

7

8


SH7

SH8

VCC

Vp / 1 0

VCC

Base 1394 Test Suite Definition with Extensions for 1394b...

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