barrel_shifter.vhd Sun Nov 01 23:56:12 2015

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1 ----------------------------------------------------------------------------------2 -- Company: 3 -- Engineer: 4 -- 5 -- Create Date: 13:10:40 10/13/2015 6 -- Design Name: 7 -- Module Name: barrel_shifter - Behavioral 8 -- Project Name: 9 -- Target Devices:

10 -- Tool versions: 11 -- Description: 12 --13 -- Dependencies: 14 --15 -- Revision: 16 -- Revision 0.01 - File Created17 -- Additional Comments: 18 --19 ----------------------------------------------------------------------------------20 library IEEE;21 use IEEE.STD_LOGIC_1164.ALL;22 23 -- Uncomment the following library declaration if using24 -- arithmetic functions with Signed or Unsigned values25 --use IEEE.NUMERIC_STD.ALL;26 27 -- Uncomment the following library declaration if instantiating28 -- any Xilinx primitives in this code.29 --library UNISIM;30 --use UNISIM.VComponents.all;31 32 entity barrel_shifter is33 Port ( d_in : in STD_LOGIC_VECTOR (7 downto 0);34 d_out : out STD_LOGIC_VECTOR (7 downto 0);35 reset, load : in STD_LOGIC;36 clk : in STD_LOGIC;37 shift_by : in STD_LOGIC_VECTOR (2 downto 0);38 shift_r_l : in STD_LOGIC);39 end barrel_shifter;40 41 architecture Behavioral of barrel_shifter is42 43 begin44 process (clk,reset,shift_by,shift_r_l)45 46 variable x: std_logic_vector(7 downto 0):="00000000";47 48 begin49 50 if(reset = '1') then51 d_out

barrel_shifter.vhd Sun Nov 01 23:56:12 2015

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59 case shift_by is60 when "000"=> d_out x := x(6 downto 0) & x(7) ;62 d_out x := x(5 downto 0) & x(7 downto 6) ;64 d_out x := x(4 downto 0) & x(7 downto 5) ;66 d_out x := x(3 downto 0) & x(7 downto 4) ;68 d_out x := x(2 downto 0) & x(7 downto 3) ;70 d_out x := x(1 downto 0) & x(7 downto 2) ;72 d_out x := x(0) & x(7 downto 1) ;74 d_out null;76 end case;77 78 when '1'=>79 case shift_by is80 when "000"=> d_out x := x(0) & x(7 downto 1) ;82 d_out x := x(1 downto 0) & x(7 downto 2) ;84 d_out x := x(2 downto 0) & x(7 downto 3) ;86 d_out x := x(3 downto 0) & x(7 downto 4) ;88 d_out x := x(4 downto 0) & x(7 downto 5) ;90 d_out x := x(5 downto 0) & x(7 downto 6) ;92 d_out x := x(6 downto 0) & x(7) ;94 d_out null;96 end case;97 98 when others => null;99 end case;

100 end if;101 end if;102 end process;103 104 end Behavioral;105 106