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The University of Texas at AustinFoil # 1
The University of Texas at AustinEE 382M-8 VLSI-2 Page 1
EE-382M-8
VLSI–II
Early Design Planning:
Back End
Mark McDermott
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Backend EDP Flow
• The project activit ies wil l include:
– Determining the standard cell and custom library elements needed
to completely do the design with APR tools.
– Detailed floor-plan of the block level components.
– A reasonably detailed top-level floorplan using the cluster abstracts.
– Approximate clock routing at the top-level
– Approximate Power-GND routing at the top level
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Standard Cell Library Effort
• Will be using a very minimal standard cell library for the project:~80+ cells
– Basic logic gates and buffers
– 1 set-reset flip-flop
• “ CMOS65_SubVt.lib” fi le was derived using a scaled 65nm .lib
file
– Need to validate the scaled numbers with HSPICE simulations.
– Need to validate power spreadsheet numbers using HSPICE:• S-D leakage currents
• Intrinsic power
– Need to validate area spreadsheet numbers
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Block Floorplanning Effort
• Objectives:
– Minimize area
– Determine best shape of the block
– Minimize total wire length
• Each team will do a detailed floorplan of their respective blocks.
The output will be a spreadsheet analysis showing the
contribution from each of the following:
– Power grid – Clocking
– Signal Routing
– Datapath area
– Random logic area
– White space
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Integration Effort
• The integration team will be responsible for: – Doing a floor plan of the top level of the chip
– Characterizing the top-level routing delays and determining theassertions and constraints for each cluster. They will be working
with each cluster to optimize the constraints. – Designing the clock routing structure:
– Determining the clock generation implementation (block diagrams)
– Determining the clock regeneration circuitry (block diagrams)
– Determining the reset logic. – Designing the power grid.
– Determining the power estimation for the global clock and signalrouting.
– Generating the power budget for each cluster. – Generating the area budget for each cluster.
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The University of Texas at AustinFoil # 7 The University of Texas at AustinEE 382M-8 VLSI-2 Page 7
Layout Implementation Options
SPARC-T1
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The University of Texas at AustinFoil # 8 The University of Texas at AustinEE 382M-8 VLSI-2 Page 8
Layout Density & Die Size = Performance
• Higher density layout leads to
smaller block sizes
• Smaller block sizes lead toshorter wires
• Shorter wires can lead to higher
frequency
• Shorter wires can also lead to
higher IPC by requiring fewer
transmission pipe stages
Layout #1
Layout #2
A B’
A
C
CB
A C
Schematic
Floorplan
B’
The layout of Block B affects the
timing of the path from A to C
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Layout Implementation Options
• Synthesis – Random Logic Macro (RLM) – Cell layout comes from a shared cell library
– Automated cell selection and placement
– Automated routing between cells
• Structured Custom (SC/SDP)
– Cell layout comes from a shared cell library
– Manual cell selection and placement
– Automated routing between cells
• Custom Design (CD)
– Cell layout is unique for each application
– Manual cell selection and placement
– Manual routing between cells
Increasing
Design Effort
(And Density)
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Layout Implementation Options
CD SC RLM
ARTL Coding M M M
Logic Minimization M M A
Cell Placement M M A
Device Sizing M A A
Layout M A A
A = Automatic
M = Manual
CD SC RLM
Timing Best Better WorstDensity Best Better Worst
Design Time Worst Better Best
• RLM saves time incircuit design andlayout
• SC saves time inlayout.
• RLM and SDP makerevisions easier.
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Datapath and Block Floorplanning Procedure
• Step 1 - Identify feedthrus for RLM or SC/DP block
• Step 2 - Look for opportunities for track sharing
• Step 3 - Define the bitpitch of the block
• Step 4 - Review the metal plan within the cell• Step 5 - Review and plan the clock routing and placement
• Step 6 - Plan the critical cell placement locations
• Step 7 - Estimate the area of the cells and the block
• Step 8 - Review the power grid
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Feed-through or Over-the-cell (OTC) Routes
• Metal tracks routed over RLM, Datapath or custom block
• The block is neither the driver or a receiver of the signals
• Feedthrus use up metal tracks which impacts the internal
signals of the block• Carefully review datapath connectivity to account for them
Bypass
ALU 0
ALU 1
ALU 2
Sources Results
Receiver
Driver
Feedthrus
for ALU0
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Datapath and Block Floorplanning Procedure
• Step 1 - Identify feedthrus
• Step 2 - Look for opportunities for track sharing
• Step 3 - Define the bitpitch of the block
• Step 4 - Review the metal plan within the cell• Step 5 - Review and plan the clock routing and placement
• Step 6 - Plan the critical cell placement locations
• Step 7 - Estimate the area of the cells and the block
• Step 8 - Review the power grid
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Step 2: Track Sharing
• Minimizes the number of unique tracks in layout byopportunistically sharing tracks where possible
• Often allows for the smallest possible bitpitch
• Allows for metal layers to be more efficiently utilized
• Can help improve performance by shortening distances
• Should always be explored to improve layout efficiency and
performance
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Step 2: Track Sharing
Bypass$
ALU 0
ALU 1
ALU 2
Sources Results
First, check outside your
block to see if there
are any candidates
for track sharing
Receiver
Driver
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Step 2: Track Sharing
Next, check inside your
block to see if there
are any candidates
for track sharing
LRBL RRBL
IE_BYC_DATA IE_RF_DATA
Metal 2Metal 4
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Step 2: Track Sharing Example
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Step 2: Track Sharing Example
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Datapath and Block Floorplanning Procedure
• Step 1 - Identify feedthrus
• Step 2 - Look for opportunities for track sharing
• Step 3 - Define the bitpitch of the block
• Step 4 - Review the metal plan within the cell• Step 5 - Review and plan the clock routing and placement
• Step 6 - Plan the critical cell placement locations
• Step 7 - Estimate the area of the cells and the block
• Step 8 - Review the power grid
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The University of Texas at AustinFoil # 21 The University of Texas at AustinEE 382M-8 VLSI-2 Page 21
Bit Pitch Defining Width of Chip
AMD K5
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Step 3: Define the Bitpitch
• Fixed cell width chosen toallow easy assembly
• Most often determined by
metal usage within the
datapath
• Integration efficiency would
prefer one bitpitch per
project• Architectures lend
themselves to more unique
bit pitches
Bitpitch A
A
A
A
A
Vdd
Sig0
Sig1
Sig2
Sig3
Sig4
Sig5
Vss
Vdd
Sig0
Sig1
Sig2
Sig3
Sig4 Sig5
Vss
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Step 3: Define the Bitpitch
Insure all blocks in a datapath stack follow the same bitpitch
B i t p i t c h # 2 Y µ
B y p a s s C a c h e
I n t e g e r R e g i s t e r
F i l e
A
L U 0
A
L U 1
A r i t h F l a g s
A G E N
- L D / S T A
S h i f t e r
W B
M u x
B i t
O p s
S y s t e
m U o p s
B i t p i t c h
# 1 X µ
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Bit Pitch Example: 3:2 Adder Bit Cell
Bitpitch
7.56u
M1
M4
M3 & M1
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Bit Pitch Example: 4 Bit Cells stacked
Bitpitch
7.56u BIT - 0
BIT - 1
BIT - 2
BIT - 4
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Bit Pitch Example: Tiled Datapath
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Bit Pitch Example: Swizzle
Don’t mix and match bit pitches to avoid swizzle channels
As buses get wider and the number of tracks per
bit gets higher the cost of swizzle channels grows
Swizzle
Channel
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Step 3: Define the Bitpitch
• Wider bit pitches allow more upper level metal usage
• Narrower bit pitches allow shorter routes for orthogonal signals
• Balancing these conflicting objectives can be difficult
• Understand your local constraints and be aware of the tradeoffs
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Datapath and Block Floorplanning Procedure
• Step 1 - Identify feedthrus• Step 2 - Look for opportunities for track sharing
• Step 3 - Define the bitpitch of the block
• Step 4 - Review the metal plan within the cell• Step 5 - Review and plan the clock routing and placement
• Step 6 - Plan the critical cell placement locations
• Step 7 - Estimate the area of the cells and the block
• Step 8 - Review the power grid
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Metal Planning
• Metal layer, width, spacing and shielding are negotiable – “ Negotiable” means you have to plead your case to the integration
leaders
• All of these impose a physical constraint for layout
• For your first attempt at convergence
– M1,M2 : Local routing – M3,M4, M5, M6 : Data and control
– M7,M8 : Power, Ground, Clock, Reset, etc
– Assume all nets are routed in M1&M2 within your block
– Assume your only shielding is on clocks and reset
– Assume the routes are minimum
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Metal Flow Planning
Avoid bi-directional dataflow
BAD GOOD
Data
Cntl
Data
Cntl
Data
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Shielding
• Intentionally routing signals to control the effective line-to-linecapacitance seen during switching.
• Requires designers to constrain the physical assembly done by
routing tools or physical design specialists (PDSs).
• Falls into one of three categories:
– Physical shielding - signals are routed next to a power rail
– Logical shielding - signals are routed by logically related signals
– Temporal shielding - signals are routed by temporally dist inct
signals
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Miller Coupling Factor
A
B
C
A
B
C
A
B
C
A
B
C
A
B
C
MCF = 1.5 One against, one quietMCF = 2.0 Both against
MCF = 0.5 One with, one quietMCF = 1.0 Both quiet MCF = 0.0 Both with
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No Shielding
• Signals are routed next to any neighboring signals• Neighbors can slow down (max delay) or speed up (min delay)
signal transitions through line-to-line coupling
• Variation can create design problems
• Most signals will not be shielded
Sig A Sig B Sig C
No ShieldMax MCF 2.0 Min MCF 0.0
A
B
C
A
B
C
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Physical Shielding
• Signals are routed next to at least one power rail• Helps both min delay and max delay
• Can be expensive in terms of metal usage
• Typically limited to most critical nets and clocks
Vss Sig A Sig B Vss Sig A Vss
Half Shield Full Shield
Max MCF 1.5
Min MCF 0.5
Max MCF 1.0
Min MCF 1.0
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Logical Shielding
• Signals are routed next to mutually exclusive neighbors• Also helps min delay and max delay
• Comparable results as physical shielding but lesser cost
• Encouraged in mux structures and arrays
Sel A Sel B Sel C
A
B
C
Sel A
Sel B
Sel C
Sel A
Sel B
Sel C
Max MCF 1.5
Min MCF 1.0
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Temporal Shielding
• Signals are routed next to signals that limit aggressors• Can help max delay or min delay or both
• Lesser cost than physical shielding, but more design effort
• Encouraged wherever possible but tricky
A
B
C
A
B
C
Max MCF 1.0
Min MCF 0.0
Ck
Ck
Ck
Sig A Sig B Sig C
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Datapath and Block Floorplanning Procedure
• Step 1 - Identify feedthrus• Step 2 - Look for opportunities for track sharing
• Step 3 - Define the bitpitch of the block
• Step 4 - Review the metal plan within the cell• Step 5 - Review and plan the clock routing and placement
• Step 6 - Plan the critical cell placement locations
• Step 7 - Estimate the area of the cells and the block
• Step 8 - Review the power grid
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Variations of Clock Tree distribution networks
Tapered H-Tree
Target: Metallization and Gate topology uniformity
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Clock Routing
• Watch out for the clock, it’s your most critical net• Make sure the physical design treats it accordingly
• Help reduce clock power by eliminating unnecessary load
• Make sure the clock has enough via coverage• Leave room for decoupling capacitors and upsizing
• Don’t forget to account for clock routing overhead (full shield) in
your metal planning
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Clock Routing
BAD GOOD
UNNECESSARY
LOAD
Avoid unnecessary clock load to save active power
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Power/Clock Grid
• Clock grid is interleaved between VDD and VSS on metal6
Port1 Input Data Latch
LCB
LCB
Port0 Input Data Latch LCB
LCB
Port0 Read/Write CktLCB
Port0 Output LatchLCB
LCB
Port1 Output LatchLCBPort1 Read/Write Ckt
LCB
LCB
LCB
LCB
Bitcell
Array
Port1 Input Data Latch
LCB
LCB
Port0 Input Data LatchLCB
LCB
Port0 Read/Write Ckt LCB
Bitcell
Array
P or t 0 D e c
o d er
LCB
LCB
Port0 Output Latch LCB
LCBPort1 Output LatchPort1 Read/Write Ckt
LCB
LCB
LCB
LCB
LCB
LCB
LCB
Port0 Read/Write Ckt
P or t 1 D e c
o d er
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Clock Routing
Make sure there are enough vias to get power through
the clock network
INSUFFICIENT
VIA COVERAGE
SUFFICIENT
VIA COVERAGE
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Clock Routing
Remember to count clocks as ~5-7 tracks in your
wire planning!
Vdd Clock Vss
Be careful with gated clocks. Fine grain
clock gating tends to drastically increase
the number of unique clocks, significantly
increasing the metal usage.
No tools catch this before layout
1x 2x 1 x
1.5x 1.5x
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Datapath and Block Floorplanning Procedure
• Step 1 - Identify feedthrus• Step 2 - Look for opportunities for track sharing
• Step 3 - Define the bitpitch of the block
• Step 4 - Review the metal plan within the cell• Step 5 - Review and plan the clock routing and placement
• Step 6 - Plan the critical cell placement locations
• Step 7 - Estimate the area of the cells and the block
• Step 8 - Review the power grid
C ll Pl t
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Cell Placement
• Start with the critical path! – Place cells to limit the wire load on the crit ical path
– Move less critical blocks out of the way
• Place clock generators to limit clock wire load
– Again, place most critical clock LCBs first if area is tight
– Ideally there should be minimal side loads
• Consider track sharing opportunit ies when placing cells
– Cell placement can enable or disable track sharing
– Optimum placement generally follows data flow
C ll Pl t
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Cell Placement
LCB
Short
critical
path
No side
load
C ll Pl t d R ti
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Cell Placement and Routing
D t th d Bl k Fl l i P d
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Datapath and Block Floorplanning Procedure
• Step 1 - Identify feedthrus• Step 2 - Look for opportunities for track sharing
• Step 3 - Define the bitpitch of the block
• Step 4 - Review the metal plan within the cell• Step 5 - Review and plan the clock routing and placement
• Step 6 - Plan the critical cell placement locations
• Step 7 - Estimate the area of the cells and the block
• Step 8 - Review the power grid
A E ti ti
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Area Estimation
• All modules have an area budget in the floorplan
• That budget is only an educated guess
• Some guesses are high, and some are low
• You will need to enhance the quality of these estimates by more
accurately estimating the area of your modules
• While doing this you will reduce the amount of late surprises in
the design and also reduce post-layout effort by converging withaccurate parasitics
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Di Si E ti ti
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Die Size Estimation
Datapath and Block Floorplanning Proced re
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Datapath and Block Floorplanning Procedure
• Step 1 - Identify feedthrus• Step 2 - Look for opportunities for track sharing
• Step 3 - Define the bitpitch of the block
• Step 4 - Review the metal plan within the cell• Step 5 - Review and plan the clock routing and placement
• Step 6 - Plan the critical cell placement locations
• Step 7 - Estimate the area of the cells and the block
• Step 8 - Review the power grid
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Power Grid
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Power Grid
Think of the grid as a straw
between the C4 and the devices.
Too many devices sucking through
the same straw or too narrow astraw can cause devices to starve
and the supply to dip or crater!
SAMPLE P /G d GRID
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SAMPLE Power/Ground GRID
Shielding takes up significant routing resources. Global M6 routes over the array should have minimal coupling noise
to array bitlines.
* Where is minimum critical dimension for width/space
S i g
S i g
S i g
S i g
VSS VDD VSS
S i g
48
S i g
V s s
V s s
V s s
V s s
(Full Shielding, MCF = 1.0)
4
Power Grid
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Power Grid
SCHEMATIC
VIEW
CELL LAYOUT
VIEW
RELATIVE CELL
PLACEMENTA
Bit 31
Bit 0
A
A
OUT
Power Grid
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Power Grid
A
SCHEMATIC
VIEW
CELL LAYOUT
VIEW
RELATIVE CELL
PLACEMENTA
Bit 31
Bit 0
A
When large, arrayed drivers pull
on the same rail, supply bounce
can occur degrading performance
and causing supply offset noise
OUT
Out
Current
Vdd
Vss
Power Grid
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Power Grid
• Be very careful arraying large drivers• Follow the % power guidelines for the power grid
• Try to keep temporal relationships between arrayed drivers
• Consider the physical impact on the grid by your design• Be prepared to make the grid more robust to compensate for
marginal grids
Summary
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Summary
• Early design planning and layout can have a signif icant impacton processor design
– Die size, profi t & power are impacted by layout density
– Schedule is impacted by implementation choices
• Floorplanning also signif icantly impacts circuit performance
– Shielding can help timing and noise sensit ive circuits
– Carefully f loorplanning critical paths can help reduce wire loads
– Reducing clock routing can reduce clock skew and clock power
Backup
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Backup
Wire and Resistance Calculator
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Wire and Resistance Calculator
ALPHA 21364
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ALPHA 21364
PPC 603
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PPC 603