QUANTIZATION NOISE SUPPRESSION IN FRACTIONAL-N

PLLs UTILIZING GLITCH-FREE PHASE SWITCHING

MULTI-MODULUS FREQUENCY DIVIDER

By Syed Azeem Hussain(11k31D5716)

In this project , a novel circuit technique, glitch-free phase switching multi-

modulus frequency divider (PS-MMFD) to suppress the QN in a fractional-N

PLL, is proposed.

In addition, the PS-MMFD could operate at a higher frequency since its internal

operating frequency is not doubled.

INTRODUCTION

SOFTWARE REQUIREMENTS:

MODELSIM 6.4C

XILINX 13.2

HARDWARE REQUIREMENT:

FPGA

SPARTAN 3

HARDWARE AND SOFTWARE

REQUIREMENTS

A wide continuous frequency division range is achieved in the proposed PS-

MMFD by using division ratio extension logic. A fractional- PLL utilizing the

proposed glitch-free PS-MMFD.

The PS-MMFD could operate at a higher frequency since its internal operating

frequency is not doubled.

SCOPE OF THE PROJECT

Unconditional Glitch-Free Phase Switching

Divide-By-0.5/1/1.5/2 Cell

Divide-By-/4/4.5 Cell

Divide-By-2/3 Cell

Proposed Glitch-Free PS-MMFD

MODULES NAME

 A PS is required, the output switches to the next state. Compared with the

waveform of no PS occurrence, the rising edges are moved backward by half

of the input cycle as the solid arrows.

The PS occurs at time, it operates properly. However, if the PS occurs a little

earlier at , an unwanted narrow pulse is generated.

Although the rising edges of the output are moved backward as normal, an

additional rising edge would be counted because of the unwanted pulse

(glitch).

The phase information will be corrupted and the function of the overall

frequency divider would be failed.

UNCONDITIONAL GLITCH-FREE PHASE SWITCHING

It is composed of a divide- by-2 quadrature phase generator, a phase

selector and a digital controller CTRL.

The divide-by-2 in /0.5/1/1.5/2 cell works at full speed (fin), and generates

four Grey-coded outputs whose rising edges (or phases) are separated by 90 .

At any instance, only one of the divide-by-2 outputs is connected to the

subsequent /2/3 chain through a 2-bit MUX. The MUX is controlled by the

2-bit word, fsm,<1:0>. , given by the control circuit block (CTRL).

In order to achieve the required four division ratios (/0.5/1/1.5/2), the CTRL

logic for glitch-free PS has to be carefully designed.

In order to obtain the continuous division ratio stepped by 0.5, the phase

switching module should be able to conduct 0-3 times of nearest-reversed-

state PS in an output cycle to realize the divide-by-/0.5/1/1.5/2.

Divide-by-0.5/1/1.5/2 Cell

1/1.5 cell

A divide-by-4/4.5 (/4/4.5) topology is Compared with conventional

divide-by-4/5 (/4/5) prescaler, the /4/4.5 divider cell is composed of

four D-flip-flops (DFFs), two multiplexers (MUXs) and two D-

latches which are all synchronized at the highest input frequency,

among which D-latch1, D-latch2, and MUX2 form a double-edge-

triggered flip-flop (DTFF), and each DFF is composed of a positive

D-latch and a negative D-latch.

When mod is high, the DTFF is enabled, and generates a signal which

lags half input cycle of selected DFF output. The signal feedbacks to

DFFs input and a half input cycle is swallowed due to its delay.

Divide-by-/4/4.5 Cell

4/4.5 cell

The PS-MMFD is mainly composed of a /0.5/1/1.5/2 cell and a /2/3

chain.

The key principle of /2/3 cell is to swallow one additional input cycle

when the input control and the feedback signal are valid.

The input frequencies are stepped down through the divider chain, so

the power consumption can be scaled down progressively.

Divide-by-2/3 cell

Divide 2/3 cell

The frequency division ratio, , is controlled by the 10-bit division ratio control input <9:0> . With the division range extension logic, the division ratio of the proposed DREL circuit can be expressed as follows

 

 

DIVISION RATIO EXTENSION LOGIC

It is mainly composed of a divide-by-0.5/1/1.5/2 (/0.5/1/1.5/2) cell, several divide-by-2/3

(/2/3) cells and the division range extension logic circuit.

Divide-by-0.5/1/1.5/2 Cell The operating principle of the divide-by-0.5/1/1.5/2

(/0.5/1/1.5/2) cell extends the basic glitch-free phase switching technique proposed.

It is composed of a divide- by-2 quadrature phase generator, a phase selector and a digital

controller CTRL. The divide-by-2 in /0.5/1/1.5/2 cell works at full speed (f in), and

generates four Grey-coded outputs whose rising edges (or phases) are separated by 90 .

At any instance, only one of the divide-by-2 outputs is connected to the subsequent /2/3

chain through a 2-bit MUX. The MUX is controlled by the 2-bit word, fsm(1:0), given by the

control circuit block (CTRL).

Proposed Glitch-Free PS-MMFD

A 700-kHz bandwidth fractional synthesizer with spurs

compensation and linearization techniques for WCDMA applications, E.

Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo

A ΣΔ fractional-N frequency synthesizer targeting WCDMA receiver

specifications is presented. Through spurs compensation and linearization

techniques, the PLL bandwidth is significantly extended with only a slight increase

in the integrated phase noise. In a 0.18-μm standard digital CMOS technology a

fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has

an area of 3.4 mm2 PADs included, and it consumes 28 mW. With a 3-dB closed-

loop bandwidth

LITERATURE SURVEY

of 700 kHz, the settling time is only 7 μs. The integrated phase noise plus

spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc

for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered)

fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer

could be used also for TX direct modulation over a broad band. The choice of such

a large bandwidth, however, still limits the spur performance. A slightly smaller

bandwidth would fulfill WCDMA requirements. This has been shown in a second

prototype, using the same architecture but employing an external loop filter and

VCO for greater flexibility and ease of testing.

CONT,…

A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with

LMS-based DAC gain calibration, M. Gupta and B. S. Song.

 

A 1.8GHz wideband fractional-N synthesizer achieves the phase

noise of an integer-N PLL using a noise-cancellation DAC calibrated with

an adaptive LMS spur correlation technique. It exhibits in-band and

integrated phase noises of -98dBc/Hz and 0.8deg, respectively. The chip in

0.18mum CMOS occupies 2mm2, and consumes 29mW at 1.8V.

A wide-bandwidth 2.4 GHz ISM band fractional-N PLL with

adaptive phase noise cancellation, A. Swaminathan, K. J. Wang, and I.

Galton.

 

A 2.4GHz ISM-band PLL with a 730kHz bandwidth, a 12MHz

reference, an on-chip loop filter, and worst-case phase noise of -101

dBc/Hz and -124dBc/Hz at 100kHz and 3MHz offsets, respectively, is

enabled by an adaptive phase-noise cancellation technique with 35mus

settling time. The 0.18mum CMOS IC measures 2.2times2.2mm2, and its

core circuitry draws 20.9mA from a 1.8V supply.

A fractional-N synthesizer with customized noise shaping for

WCDMA/ HSDPA applications, X. Yu, Y. Sun,W. Rhee, H. K. Ahn, B.

H. Park, and Z. Wang.

  This paper describes a quantization noise reduction method in

Delta Sigma fractional-N synthesizer design based on a semidigital

approach. By employing a phase shifting technique, a low power hybrid

finite impulse response (FIR) filtering is realized which is suitable for RF

applications. A prototype fractional-N synthesizer is implemented in 180

nm CMOS for WCDMA/HSDPA applications. Experimental results show

that the proposed method can effectively suppress out-of-band phase noise

to meet the phase noise mask requirements in various RF applications.

A noise filtering technique for fractional-N frequency synthesizers, C. C. Hung

and S. I. Liu

 

A noise filtering technique for fractional-N frequency synthesizers

(FNFSs) is presented. The noise filter is based on an integer-N (N = 1) phase-

locked loop that is placed in a feedback path of an FNFS. By adopting the noise

filter, out-of-band quantization noise of a high-order delta-sigma modulator is

suppressed. In addition, folded noise due to nonlinearity of a phase/frequency

detector (PFD) and a charge pump is improved by reducing phase errors at PFDs.

An FNFS using the noise filter is fabricated in 90-nm complementary metal-

oxide-semiconductor technology. Its die area is 950 by 950 μm, and its power

consumption is 30 mW for a supply voltage of 1 V. The frequency resolution of

this FNFS is less than 1 Hz.

More robust

Can operate at higher input frequency

Consumes less power

ADVANTAGES

Wireless Communication Systems

PLL Design

APPLICATIONS

PROPOSED GLITCH-FREE PS-MMFD FIRST BLOCK

PROPOSED GLITCH-FREE PS-MMFD SECOND BLOCK

DIVIDE-BY-2/3 CELL

UNCONDITIONAL GLITCH-FREE PHASE SWITCHING

PHASE DIVIDER

FSM

PHASEDETECTORBYFSM

 TOPMODULE

103

104

105

106

107

108

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

eq(1) w/ QN supp

eq(1) w/o QN supp

Required PN MaskPN w/ QN supp

PN w/o QN supp

MATLAB SNAPSHOT

A novel multi-modulus frequency divider architecture utilizing

glitch-free phase switching is proposed to achieve half-stepped division

ratios and thus QN suppression in fractional- PLLs. Theoretical analysis

and circuit implementations with practical timing issues discussions for the

proposed PS-MMFD are presented in details. The proposed PS-MMFD is

unconditionally glitch-free and achieves 6-dB QN suppression thanks to its

half-step division. The proposed PS-MMFD is able to operate at higher

input frequency and consume less current, compared with other state-of-

the-art frequency dividers (usually based on double-edge-triggering

technique) used for QN Suppression.

CONCLUSION

[1] G. C. Gillette, “Digiphase synthesizer,” in Proc. 23rd Annu. IEEE Freq. Control

Symp., 1969, pp. 201–210.

[2] N. B. Braymer, “Frequency synthesizer,” U.S. Patent 3,555,446, Jan. 12, 1971.

[3] S. Pamarti, L. Jansson, and I. Galton, “A wideband 2.4-GHz delta-sigma

fractional-NPLL with 1-Mb/s in-loop modulation,” IEEE J. Solid-State Circuits,

vol. 39, no. 1, pp. 49–62, Jan. 2004.

[4] E. Temporiti, G. Albasini, I. Bietti, R. Castello, and M. Colombo, “A 700-kHz

bandwidth fractional synthesizer with spurs compensation and linearization

techniques for WCDMA applications,” IEEE J. Solid-State Circuits, vol. 39, no. 9,

pp. 1446–1454, Sep. 2004.

REFERENCE

[5] M. Gupta and B. S. Song, “A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2842–2851, Dec. 2006.

 

[6] A. Swaminathan, K. J. Wang, and I. Galton, “A wide-bandwidth 2.4 GHz ISM band fractional-N PLL with adaptive phase noise cancellation,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2639–2650,Dec. 2007.

 

[7] X. Yu, Y. Sun,W. Rhee, H. K. Ahn, B. H. Park, and Z. Wang, “A fractional-N synthesizer with customized noise shaping for WCDMA/ HSDPA applications,” IEEE J. Solid-State Circuits, vol. 44, no. 8, pp. 2193–2201, Aug. 2009.

 

[8] C. C. Hung and S. I. Liu, “A noise filtering technique for fractional-N frequency synthesizers,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, pp. 139–143, Mar. 2011.

CONT,…