Autumn 2012C.-S. Shieh, EC, KUAS, Taiwan1 The 8051 Family Microcontroller Chin-Shiuh Shieh csshieh...
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Transcript of Autumn 2012C.-S. Shieh, EC, KUAS, Taiwan1 The 8051 Family Microcontroller Chin-Shiuh Shieh csshieh...
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 1
The 8051 Family Microcontroller
Chin-Shiuh Shiehhttp://bit.kuas.edu.tw/~csshieh
Department of Electronic EngineeringNational Kaohsiung University of Applied Sciences, Taiwan
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 2
Microcontrollers
• Microprocessors, such as 8086 family, have only CCU and ALU in them. External RAM, ROM, and I/O are required.
• Microcontrollers, such as 8051 family, encompass CCU, ALU, RAM, ROM, and I/O in a single chip, also called single-chip.
• Microcontrollers have limited computational power, but their low-cost make them prevalent in consumer products and small-scale control systems.
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 3
Microcontrollers (cont)
• We adopt 8051 family microcontroller in our class for its general structure and manageable system complexity.
• A large number of manufactures offer different variants of 8051 family microcontroller.
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 4
ATMEL AT89C51
• AT89C51 / AT89S51 is a popular member of the 8051 family microcontroller from ATMEL.
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 5
Features
• 8-bit CPU optimized for control applications
• 128 bytes of on-chip Data RAM, 4K bytes of on-chip Program Memory (Flash Memory/ROM)
• 64K Program Memory address space, 64K Data Memory address space
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 6
Features (cont)
• 32 bidirectional and individually addressable I/O lines
• Two 16-bit timer/counters
• Full duplex programmable UART
• 6-source/5-vector interrupt structure with two priority levels
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 8
Pin Configurations (cont)
• Vcc, GND: supply voltage (5V), ground
• XTAL1, XTAL2: crystal connections for system clock
• RST: reset input
• EA: External Access, EA=5V to enable internal ROM.
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 10
Pin Configurations (cont)
• P0.0~P0.7: Port 0, bidirectional bit-addressable with open drain
• P1.0~P1.7: Port 1, bidirectional bit-addressable with internal pull-ups
• P2.0~P2.7: Port 2, bidirectional bit-addressable with internal pull-ups
• P3.0~P3.7: Port 3, bidirectional bit-addressable with internal pull-ups
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 12
Pin Configurations (cont)
• MOV P2,#0Ah ;Copy 0A16 to P2
• MOV P2,#08 ;Copy 08 to P2
• MOV P2,#00110100b;Copy 3416 to P2
• SETB P2.0 ;Set P2.0 to “1”• CLR P2.1 ;Clear P2.1 to “0”• MOV A,P1 ;Copy P1 to A• JB P3.2,LOOP ;Jump to LOOP if P3.1 is “1”
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 13
Pin Configurations (cont)
• P0 is open-drain– SETBP0.0;P0.0 = high impedance – CLR P0.1;P0.1 = 0V
• P1, P2, and P3 have internal pull-ups– SETBP1.0;P1.0 = 5V– CLR P1.1;P1.1 = 0V
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 14
• "MOV P2,A" will turn on LEDs on P2 whose corresponding bits in A is "0". Notice that I/O port source current is limited.
• If an I/O port is used for input, it's output latch must set to "1". For example, "MOV P1,#0FFh", then "MOV A,P1" will read P1 status into A.
• MOV P1,#0FFh• MOV A,P1
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 15
• P0 is open-drain. Pull-up resistor is required. "SETB P0.0" will turn on the relay and "CLR P0.0" will turn it off.
• For button applications, de-bounce circuitry and code is required (5RC=10mS~20mS).
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 16
ORG 0000hLOOP:
SETB P2.0LCALL DELAYCLR P2.0LCALL DELAYLJMP LOOP
DELAY:MOV R0,#0FFh
L1: MOV R1,#0FFhL2: DJNZ R1,L2 ; Decrease and jump if not zero
DJNZ R0,L1RETEND
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 19
Pin Configurations (cont)
• Alternative Functions of Port 3
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 20
Pin Configurations (cont)
• PSEN: Program Store Enable, read strobe for external program memory
• ALE: Address Latch Enable, for multiplexing AD0~AD7
• A8~A15(P2.0~P2.7): high-byte address bus for external addressing
• AD0~AD7(P0.0~P0.7): multiplexed low-byte address bus and data bus for external addressing
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 21
Memory Organization
• Separation of program addressing space and data addressing space.
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 24
Internal Data Memory
• MOV 12h,#05h• MOV A,3Ch• MOV 0E0h,3Ch
• MOV A,R0
• MOV 20h,#05h• SETB 03h• MOV A,20h; A==0D
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 28
Special Function Register Map (cont)
• MOV P2,#55h == MOV 0A0h,#55h• SETB P1.0• CLR P1.0
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 29
Special Function Register Map (cont)
• MOV SBUF,A = MOV 99h,0E0h • MOV 99h,A
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 30
Special Function Registers
• A, (ACC): Accumulator – MOV A,#02h– ADD A,#03h
• B: B Register – MUL AB
• MOV A,#03h• MOV R0,#02h• MUL AR0
– DIV AB• SP: Stack Pointer • DPTR(DPH,DPL): Data Pointer
– MOV DPTR,#4000h– MOVX A,@DPTR
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 31
Special Function Registers (cont)
• P0: Port 0
• P1: Port 1
• P2: Port 2
• P3: Port 3
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 32
Special Function Registers (cont)
• TH0: Timer/Counter 0 High Byte
• TL0: Timer/Counter 0 Low Byte
• TH1: Timer/Counter 1 High Byte
• TL1: Timer/Counter 1 Low Byte
• SBUF: Serial Data Buffer – MOV SBUF,A
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 33
Special Function Registers (cont)
• PSW: Program Status Word • PCON: Power Control Register • IE: Interrupt Enable Register • IP: Interrupt Priority Register • TCON: Timer/Counter Control Register • TMOD: Timer/Counter Mode Control
Register • SCON: Serial Port Control Register
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 38
PCON: Power Control Register (cont)
• SETB SMOD ; Incorrect• MOV A,PCON• ORL A,#10000000b• MOV PCON,A
• CLR GF0 ; Incorrect• MOV A,PCON• ANL A,#11111011b• MOV PCON,A
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 39
IE: Interrupt Enable Register
; Enable External Interrupt 0 with high prioritySETB EX0SETB EASETB PX0
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 44
TMOD: Timer/Counter Mode Control Register (cont)
TH1 TL1
FD FD
FF• 8-bit Auto-reload mode
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 47
PC: Program Counter
• PC: Program Counter – 16-bit register– Instruction fetching– Auto increase
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 52
Addressing Mode
• Immediate: MOV A,#20h
• Register: MOV A,R0
• Direct: MOV A,30h
• Indirect: MOV A,@R0
• External Data Indirect: MOVX A,@DPTR
• Code Indirect: MOVC A,@A+DPTR
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 53
• MOV A,#00h
• ADD A,00h
• ADD A,01h
• ADD A,02h
• …
• ADD A,09h
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 54
• int x[10];• int sum;
• sum=0;• sum=sum+x[0];• sum=sum+x[1];• sum=sum+x[2];• …• sum=sum+x[9];
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 55
• int x[10];
• int sum;
• for(i=0;i<10;i++)– sum=sum+x[i];
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 56
• MOV A,#00h
• MOV R0,#09h
• LOOP:– ADD A,@R0– DJNZR0,LOOP
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 57
• int x[10],sum;
• sum=sum+x[0];
• sum=sum+x[1];
• sum=sum+x[2];
• …
• sum=sum+x[9];
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 59
Instruction Set
• ASEM51 v1.3– Assembler Directives
• ORG• EQU
• Emulator 8051 V1.0 or JSIM-51
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 60
• JB bit, rel
• JNB bit, rel
• JC rel
• JNC rel
• JZ rel ; Jump if A==0
• JNZ rel
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 61
• ADD B,R0
• ANL A,#00001111b
• MOV A,PCON
• ANL A,#01111111b
• MOV PCON,A
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 63
• MOV A,00h
• ADD A,04h
• MOV 08h,A
• MOV A,01h
• ADDC A,05h
• MOV 09h,A
Autumn 2012 C.-S. Shieh, EC, KUAS, Taiwan 64
• MOV R0,#10
• LOOP:
• …
• …
• …
• DEC R0
• CJNE R0,#00, LOOP