ATCA LLP CARRIER BLOCK DIAGRAMS

LAST UPDATE 09/05/2007

Master / Slave Structure

TCLK

SLOT A (n)

SWITCHES

MASTER/SLAVE

CARD_PRESENT

TCLK_PRESENT

TRIGGERCLOCKSYNCs

And DATAMANAGERS

SLOT B (n+1) MASTER/SLAVE

CARD_PRESENT

TCLK_PRESENT

TRIGGERCLOCKSYNCs

And DATAMANAGERS

DATAPATH

CLOCK AND SYNCS

DATAPATH

CLOCK AND SYNCS

200Mhz Clock and Clock SYNC distribution

TCLK

GTS

CORE

SEGMENT

SEGMENT

PLL

SWITCH

GTS_CLOCK

VIRTEX4 FX100

MAIN FPGA

SMBINSP

VIRTEX4 LX25DATA DISTRIBUTON

MGT CLOCKSYSTEM

CLOCK_ SYNC

CLOCK_ SYNC

200MHz

FANOUT

SWITCH

MASTER

100MHz

SWITCH

SEGMENT

SEGMENT

SEGMENT

SEGMENT

PLL

SWITCH

GTS_CLOCK

VIRTEX4 FX100

MAIN FPGA

SMBINSP

VIRTEX4 LX25DATA DISTRIBUTON

MGT CLOCKSYSTEM

CLOCK_ SYNC

CLOCK_ SYNC

200MHz

FANOUT

SWITCH

SLAVE

100MHz

SWITCH

PPC_CLOCK

PPC_CLOCK

100MHz200MHz

100MHz200MHz

$07 – D0

$07 – D1

$07 – D2

$08 – D1

$07 – D0

$07 – D1

$07 – D2

$08 – D1

PPC_CLOCK

PPC_CLOCK

GTS ADCs CLOCK SYNC distribution

TCLK

GTS

CORE

SEGMENT

SEGMENT

FANOUT

SYNC_RTN

MASTER

SLAVE

SEGMENT

SEGMENT

SEGMENT

SEGMENT

FANOUT

GTS_SYNC

GTS_SYNC

100MHz clock with missed periods as SYNC event

SWITCH

SWITCH

SYNC_AUX

SYNC_RTN

SYNC_AUX

Serializers SYNC signal distribution

TCLK

GTS

CORE

SEGMENT

SEGMENT

FANOUT

MASTER

SLAVE

SEGMENT

TRIGGERFPGA

MAINFPGA

SWITCH

SEGMENT

SEGMENT

SEGMENT

FANOUT

TRIGGERFPGA

MAINFPGA

SWITCH

10MHz clock signal (the patterns must be equal at any rising edge)

Bcast & Msg Handler Serialized

SE

RIA

LIZ

ER

S

8

1

8

FROM REMOTE (TCLK)

GT

S

ME

ZZ

AN

INE

MAIN FPGA

Msg_str0Msg_str1

B_cast_data (7 downto 0)

B_cast_str0

B_cast_str1

LLP Status (7 downto 0)

GTS Status (7 downto 0)

Msg_data (7 downto 0)SE

G/C

OR

E

ME

ZZ

AN

INE

Msg_str0Msg_str1

LLP Status (7 downto 0)

Msg_data (7 downto 0)

8

8

8

8

8

FROM REMOTE (TCLK)

TO REMOTE (TCLK)

FANOUT TO MAIN FPGA, LOCALS MEZZANINES, AND REMOTE MEZZANINES (TCLK)

Con

cent

rato

r

LX25FPGA 2

x6

LX25FPGA 2

x4

Trig_req (1 downto 0)

Trig_val (1 downto 0)

Lt_data (7 downto 0)

Tv_data (7 downto 0)

Lt_Strobe

Tv_Strobe

TRIGGER Handlerserialized

Trig_Rej (1 downto 0) 8

FANOUT TO OTHERS DEST8

8

CO

RE

ME

ZZ

AN

INE

Local_Trigger (1 downto 0)

MAIN FPGA

LX25

GT

S

ME

ZZ

AN

INE

FROM REMOTE (TCLK)

Trig_req (1 downto 0)

x4TCLK

Trig_val (1 downto 0)

Lt_data (7 downto 0)

Tv_data (7 downto 0)

Lt_Strobe

Tv_Strobe

Trig_Rej (1 downto 0)

SE

Rs

/ D

ES

ER

s 8

1

GT

S

ME

ZZ

AN

INE

cm

c #

1

Trig_req (1 downto 0)

B_cast_data (7 downto 0)

B_cast_str0

B_cast_str1

GTS Status (7 downto 0)

8

8

8

8

8

10pairs (20 lines)

44 lines 44 lines 44 lines

8

8

8

8

8

44 lines

TC

LK

266 / 448 ~50% of LX25_FF668

Alignement BUS (3 lines)

CMC #2 CMC #3 CMC #4 FX100

TRIGGER & BCAST Handler (parallel)

Using 1 16 bit port :128 words/event 256 bytes/event6 channels 1536bytes16bit bus @ 100MHz Need 7.68µs (20µs avaible @ 50KHz)

SerializerSerializer

Data_A (15 downto 0)

Empty_AData_Ready_AData_Request_A

Deserializer

8 pairs ; 16 I/O

1Mx18DPRAM

20bit

Data readout engine

Data_A (15 downto 0)

Empty_A

Data_Ready_AData_Request_A

X4 Mezzanines

18bit

SerializerSerializer

20bit

18bit

1536*4 = 6144 byte/Event16bit bus @ 200MHzNeed 15.36µs (20µs avaible @ 50KHz

Max 325 Events stored6.5msec@50KHz

Data Rate Required 307.2 Mb/sec @50KHz

Data Readout Protocol

Peak Bandwidth

[Mb/sec]

Peak Event Rate

[KHz]

Fast Ethernet [100Mbit/sec]

11 1.8

1G Ethernet [1.25 Gbit/sec]

94 15.3

PCI Express

[2.5 Gbit/sec]225 36.6

MGT Clocking Layout

RocketIO101M

UX

RocketIO102M

UX

RocketIO103M

UX

RocketIO105M

UX

MGTclkM34/N34

MGTclkAP28/AP29

RocketIO106M

UX

RocketIO109M

UX

RocketIO110M

UX

RocketIO112M

UX

RocketIO113M

UX

MGTclkAP3/AP4

MGTclkJ1/K1

RocketIO114M

UX

100250MHzPCI Express

JITTERATTENUATOR

200MHzGTS Clock

(***) User SFP could be used as 1GEnet or PCIExpressDAQ without FABRIC

ATCA FABRIC CH15

AB

AB

AB

AB

AB

AB

AB

AB

AB

AB

100MHzGTS Clock

OPTICALSFP

LOCAL100MHz

PHASE LOCKED

ATCA FABRIC CHxx

ATCA FABRIC CH13

ATCA FABRIC CH14

PCI Express SFP

ATCA FABRIC CH02

ATCA FABRIC CH01

ATCA FABRIC CH04

ATCA FABRIC CH03

ATCA FABRIC CH06

ATCA FABRIC CH05

ATCA FABRIC CH12

ATCA FABRIC CH11

ATCA FABRIC CH10

ATCA FABRIC CH09

ATCA FABRIC CH08

ATCA FABRIC CH07

FPGA0 TempMAX1617A

Address $18

FPGA1 TempMAX1617A

Address $19

FPGA2 TempMAX1617A

Address $4C

CMC1Address $50

CMC2Address $51

CMC3Address $52

CMC4Address $53

Temp SensMAX6626

Address $48

Temp SensMAX6626

Address $49

Temp SensMAX6626

Address $4ASFP Lanes

I2C Multiplexer

MAIN FPGA(FX100)

SFP Clock

Temp SensMAX6626

Address $4B

FPGA1 SwLX25

Address $60

FPGA2 TriggerLX25

Address $61

I2C Multiplexer

DC-DCATC210

Address ?

I2C bus layout

Fast Ethernet

ATCA Zone1

IPMIIPMI Address

IPMI A

IPMI B

uProcassor

JTAG Connector (Front Panel)

MANUALSW

Slow control layout (JTAG Management)

MAIN FPGA(FX100)

JTAG SWITCH

Fast Ethernet

ATCA Zone1

IPMIIPMI Address

IPMI A

IPMI B

I2C Multiplexer

CONF[1..0]

SEL PROGRAM [1..0]

TCK

TMS

TDO

INIT

TDI

X7 (4 Mezzanines + 3 FPGAs)

RMT JTAG

TCLK Port Layout

ATCA Power Supply (maximum)

Fusing

-48V

DC

HS ENABLE

DC to DCConverter

DC to DCConverter

DC to DCConverter

DC to DCConverter

P3V3-5A 16.5W MEZZANINE 1

MEZZANINE 2

MEZZANINE 3

MEZZANINE 4

MAIN BOARDP3V3-7A 23W

P5V0/P2V5Linear Reg

M48/P12DC DC

P12/P3V3DC DC

MAIN BOARDP2V5-7A 17.5WP12/P2V5DC DC

FPGAs COREP1V2-9A 11WP12/P1V2DC DC

FPGA MGTP1V2-5A 6WP5V0/P1V2DC DC

P5V0/P2V5Linear Reg

P2V5-1.0A

P2V5-0.05A

P5V0/P1V8Linear Reg

P1V8-0.5A PROMS

VCCAUXFpga 1

VCCAUX MGT

P5V0/P2V5Linear Reg

P2V5-1.0A VCCAUXFpga 2

P2V5/P1V5Linear Reg

P1V5-2.5AVTTTXs

P2V5/P1V5Linear Reg

P1V5-0.2AVTTRXs

MGT BUFFERS P1V8-4.2A 7.5WP5V0/P1V8

DC DC

P12V-14.6A 181W

P3V3-5A 16.5W

P3V3-5A 16.5W

P3V3-5A 16.5W

M48V-4.2A 200W

DC-DC Efficency assumed at least 90%

DC-DC ARTESYN

P3V3_BOOT

DC-DC NATIONAL

P12/P5V0DC DC

P5V0-8.6A 47.8W

LINEAR REGULATORS

P5V0/P1V5Linear Reg

P3V3-0.2APLL_VCC

P2V5/P1V8Linear Reg

P1V8-0.8ADPRAM_VCC

P5V0/P3V3Linear Reg

P1V8-0.4A ZARLINK_VCC

P2V5-4.8A 15.8WP5V0/P3V0DC DC

8.3W

P3V3-0.1A

18.2W

18.2W

18.2W

18.2W

6.6W

10.8W

25.3W

19.3W

17.4W

2.0A (10W)

52.6W

DC-DC POWER ONE

SWITCH MICREL

P2V5-2A 5W

P1V8A

VCCB

P1V25A

P2V5/P1V8Linear Reg

P0V8-0.8ADPRAM_VREF

P5V0/P3V3Linear Reg

P3V3-0.6A SFP Power SupplyP3V3_SFP_LANESP3V3_SFP_CLOCK

IC95

VREF_DPRAM

IC53

IC57

P1V8_DPRAM

P3V3_ZLKP1V8_ZLK

IC2

IC99

P3V3_CMC1

IC100

P3V3_CMC2

IC108

P3V3_CMC3

IC110

P3V3_CMC4

P3V3A

IC49

IC78

P12V

IC51

IC24

P1V2

IC92

P2V5

IC94

P3V3

IC16

IC15

IC10

P5V

IC59

VTTTX_TILE1VTTTX_TILE2

IC58

VTTRX

IC48

IC54

P2V5A

P2V5/P1V8Linear Reg

P0V8-0.8A

P1V8_VCCO

IC86

P2V5/P1V8Linear Reg P2V5A_SW

IC26

P2V5_AUX_FPGA0

IC45

IC42

P2V5_AUX_FPGA2

IC106IC5IC6

P1V8_FLASH0P1V8_FLASH1P1V8_FLASH2

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

Case 1 : PCIExpress

1Mx36DPRAM

PREPROCESSING

ADCs

TCLK Bus

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

Case 2 : 1G Ethernet switch

GEthernetSwitch

EB FARM

PREPROCESSING

ADCs

TCLK Bus

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

1Mx36DPRAM

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

PCIExpress

Case 3 : PCIExpress (full mesh)