ATC v. 5 - Institute of Transportation Engineers --...

A Recommended Standard of the Joint Committee on the ATC Ballot Copy for Joint Adoption by AASHTO, ITE, and NEMA

ATC v. 5.0

Advanced Transportation Controller (ATC) Standard

October 28, 2003

This is a draft document that is distributed for review and ballot purposes only. You may reproduce and distribute this document within your organization, but only for the purposes of and only to the extent necessary to facilitate review and ballot to AASHTO, ITE, or NEMA. Please ensure that all copies reproduced or distributed bear this legend. This document contains recommended information that is subject to approval.

Published by American Association of State Highway and Transportation Officials (AASHTO) 444 North Capitol St. NW, Suite 249 Washington, DC 20001 Institute of Transportation Engineers (ITE) 1099 14th St. NW, Suite 300 West Washington, DC 20005-3438 National Electrical Manufacturers Association (NEMA) 1300 N. 17th St., Suite 1847 Rosslyn, VA 222209-3801 © Copyright 2003 AASHTO/ITE/NEMA. All rights reserved.

Joint NEMA, AASHTO, and ITE Copyright and

Advanced Transportation Controller (ATC)

NOTICE

These materials are delivered "AS IS" without any warranties as to their use or performance. AASHTO/ITE/NEMA AND THEIR SUPPLIERS DO NOT WARRANT THE PERFORMANCE OR RESULTS YOU MAY OBTAIN BY USING THESE MATERIALS. AASHTO/ITE/NEMA AND THEIR SUPPLIERS MAKE NO WARRANTIES, EXPRESSED OR IMPLIED, AS TO NONINFRINGEMENTOF THIRD PARTY RIGHTS, MERCHANTABILITY, OR FITNESS FOR ANYPARTICULAR PURPOSE. IN NO EVENT WILL AASHTO, ITE, OR NEMA OR THEIR SUPPLIERS BE LIABLE TO YOU OR ANY THIRD PART FOR ANY CLAIM OR FOR ANY CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES, INCLUDING ANY LOST PROFITS OR LOST SAVINGS, ARISING FROM YOUR REPRODUCTION OR USE OF THESE MATERIALS. EVEN IF AN AASHTO, ITE, OR NEMA REPRESENTATIVE HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Some states or jurisdictions do not allow the exclusion or limitation of incidental, consequential, or special damages, or exclusion of implied warranties, so the above limitations may not apply to you. Use of these materials do not constitute an endorsement or affiliation by or between AASHTO, ITE, or NEMA and you, your company, or your products and services. If you are not willing to accept the foregoing restrictions, you should immediately return these materials. ATC is a trademark of NEMA/AASHTO/ITE.

DRAFT ATC Controller Standard

TABLE OF CONTENTS

ATC Controller – Expedited Standards Development Page i Rev. 5 Ballot Draft

TABLE OF CONTENTS 1

2

1 FORWARD......................................................... 1-1 3

2 INTRODUCTION................................................ 2-1 4

2.1 SCOPE ..................................................................2-1 5

2.2 KEY ELEMENTS OF THE ATC CONTROLLER 6

STANDARD ............................................................2-3 7

2.2.1 Form/Fit/Function .............................................. 2-3 8

2.2.2 Engine Board ..................................................... 2-3 9

2.2.3 Communications and User Interfaces ............. 2-4 10

2.2.4 Parallel and Serial I/O ........................................ 2-4 11

2.2.5 Software Interface.............................................. 2-4 12

2.3 REFERENCES.........................................................2-5 13

2.3.1 Normative References....................................... 2-5 14

2.3.2 NTCIP Standards ............................................... 2-6 15

3 CONCEPT OF OPERATIONS ........................... 3-1 16

3.1 PROBLEM STATEMENT...........................................3-1 17

3.2 HISTORICAL BACKGROUND....................................3-2 18

3.2.1 NEMA .................................................................. 3-2 19

3.2.2 The Model 170 Specification............................. 3-3 20

3.2.3 The ATC 2070 Standard .................................... 3-4 21

3.3 FUNCTIONAL NEEDS ..............................................3-4 22

3.4 OPERATIONAL ENVIRONMENT ................................3-6 23

3.5 REPRESENTATIVE USAGE ......................................3-7 24


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3.5.1 Manage/Configure Controller 1 Applications ..................................................... 3-10 2

3.5.2 Manage External Devices................................ 3-12 3

3.5.3 Facilitate Ease of Maintenance & Future 4 Hardware and Software Updates.................... 3-12 5

3.6 SECURITY............................................................3-13 6

3.7 MODES OF OPERATION ........................................3-14 7

4 FUNCTIONAL REQUIREMENTS...................... 4-1 8

4.1 MANAGE/CONFIGURE CONTROLLER 9

APPLICATIONS.......................................................4-1 10

4.1.1 Install and Update Applications 11 Software.............................................................. 4-1 12

4.1.2 Installing and Upgrading the Operating 13 System Software................................................ 4-2 14

4.1.3 Maintain Clock/Calendar Function and 15 Synchronize with Reliable External 16 Sources As Needed ........................................... 4-2 17

4.1.4 Configure and Verifying Parameter(s) ............. 4-2 18

4.1.5 Uploading/Downloading Data Block(s)............ 4-3 19

4.1.6 Monitoring and Verifying Present 20 Application Status ............................................. 4-3 21

4.1.7 Allowing Operator Control of 22 Application(s)..................................................... 4-4 23

4.1.8 Facilitate the Long Term Retention of 24 Data ..................................................................... 4-4 25

4.2 MANAGE EXTERNAL DEVICES ................................4-4 26

4.2.1 Monitor the Status of External Field 27 Devices ............................................................... 4-4 28


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ATC Controller – Expedited Standards Development Page iii Rev. 5 Ballot Draft

4.3 FACILITATE EASE OF MAINTENANCE & 1

FUTURE HARDWARE OR SOFTWARE UPDATES........4-5 2

4.3.1 Provide Support for a Standardized API.......... 4-5 3

4.3.2 Provide a Platform that Allows for 4 Hardware Upgrades........................................... 4-6 5

5 ENGINE BOARD DETAILS ............................... 5-1 6

5.1 GENERAL INFORMATION.........................................5-1 7

5.1.1 Engine Board ..................................................... 5-1 8

5.1.2 Host Module ....................................................... 5-2 9

5.2 MECHANICAL AND PHYSICAL..................................5-2 10

5.2.1 Board Dimensions and Mechanical 11 Requirements..................................................... 5-2 12

5.2.2 Connector Pinout and Signal Names............... 5-4 13

5.2.3 Environmental Requirements........................... 5-6 14

5.3 ON-BOARD RESOURCES........................................5-6 15

5.3.1 Central Processing Unit .................................... 5-6 16

5.3.2 Startup Considerations ..................................... 5-6 17

5.3.3 Memory ............................................................... 5-6 18

5.3.4 Real-Time Clock (RTC) ...................................... 5-7 19

5.3.5 ATC Controller API Support ............................. 5-7 20

5.4 ELECTRICAL INTERFACE ........................................5-8 21

5.4.1 Power .................................................................. 5-8 22

5.4.2 Synchronization............................................... 5-10 23

5.4.3 Serial Interface Ports....................................... 5-10 24

5.4.4 Programming/Test Port................................... 5-14 25

5.4.5 Miscellaneous .................................................. 5-15 26


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ATC Controller – Expedited Standards Development Page iv Rev. 5 Ballot Draft

6 COMMUNICATION INTERFACE DETAILS...... 6-1 1

6.1 GENERAL DESCRIPTION.........................................6-1 2

6.1.1 Interchangeability Control Guidance............... 6-2 3

6.1.2 Serial Port Identification ................................... 6-3 4

6.2 MECHANICAL DESCRIPTION....................................6-3 5

6.2.1 Mechanical Outline Dimensions....................... 6-3 6

6.2.2 ATC Communications Connector 7 Mechanical Pin Assignments ........................... 6-4 8

6.2.3 Mechanical Field Connections ......................... 6-5 9

6.3 OPERATIONAL DESCRIPTION..................................6-9 10

6.3.1 Interface to ATC ................................................. 6-9 11

6.3.2 Modulation and Demodulation ....................... 6-10 12

6.4 COMMUNICATIONS INTERFACE VERSIONS.............6-18 13

7 PHYSICAL AND USER INTERFACE 14

DETAILS............................................................ 7-1 15

7.1 USER INTERFACE GENERAL DESCRIPTION..............7-1 16

7.1.1 Minimum User Interface .................................... 7-1 17

7.1.2 Optional User Interfaces ................................... 7-2 18

7.1.3 User Interface Pin Connections ....................... 7-2 19

7.1.4 User Interface Operation................................... 7-3 20

7.1.5 User Interface Power Requirements ................ 7-9 21

7.2 POWER SUPPLY GENERAL DESCRIPTION..............7-10 22

7.2.1 "ON/OFF" Power Switch ................................. 7-10 23

7.2.2 LED DC Power Indicators ............................... 7-10 24

7.2.3 Service Voltage Fuse....................................... 7-10 25

7.2.4 +5 VDC Standby Power ................................... 7-10 26


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ATC Controller – Expedited Standards Development Page v Rev. 5 Ballot Draft

7.2.5 Monitor Circuitry.............................................. 7-11 1

7.2.6 External Power Supply Requirements........... 7-12 2

7.3 MECHANICAL AND PHYSICAL GENERAL 3

DESCRIPTION.......................................................7-13 4

7.3.1 Chassis ............................................................. 7-14 5

8 PARALLEL AND SERIAL I/O DETAILS........... 8-1 6

8.1 GENERAL INFORMATION.........................................8-1 7

8.1.1 Parallel Input / Output Overview ...................... 8-1 8

8.1.2 Serial I/O Overview ............................................ 8-1 9

8.2 PARALLEL INPUT / OUTPUT (PI/O)..........................8-2 10

8.2.1 Parallel Connection to Model 332 11 Cabinets.............................................................. 8-2 12

8.2.2 Parallel Connection to NEMA TS-1 or 13 TS-2 Type 2 Cabinets ...................................... 8-19 14

8.2.3 Connection to NEMA TS-2 Type 1 15 Cabinets............................................................ 8-21 16

8.3 SERIAL INPUT / OUTPUT.......................................8-22 17

8.4 ISOLATION REQUIREMENTS ..................................8-24 18

8.4.1 Engine Board Isolation.................................... 8-25 19

8.4.2 Parallel I/O Isolation ........................................ 8-25 20

8.4.3 Serial I/O Isolation ........................................... 8-25 21

9 ENVIRONMENTAL AND TEST 22

PROCEDURES.................................................. 9-1 23

9.1 GENERAL ..............................................................9-1 24

9.2 INSPECTION ...........................................................9-2 25

9.3 TESTING CERTIFICATION ........................................9-3 26


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ATC Controller – Expedited Standards Development Page vi Rev. 5 Ballot Draft

9.4 DEFINITIONS OF DESIGN ACCEPTANCE 1

TESTING (DAT) AND PRODUCTION TESTING. ..........9-3 2

9.5 ENVIRONMENTAL AND OPERATING 3

REQUIREMENTS .....................................................9-3 4

9.5.1 Voltage and Frequency ..................................... 9-3 5

9.5.2 Transients, Power Service ................................ 9-3 6

9.5.3 Nondestructive Transient Immunity 7 (DAT) ................................................................... 9-4 8

9.5.4 Temperature and Humidity ............................... 9-5 9

9.6 TEST FACILITIES ....................................................9-5 10

9.7 TEST PROCEDURE: TRANSIENTS, 11

TEMPERATURE, VOLTAGE, AND HUMIDITY ..............9-6 12

9.7.1 Test A: (DAT) Placement in 13 Environmental Chamber and Check-Out 14 of Hook-Up ......................................................... 9-6 15

9.7.2 Test B: (DAT) Temperature Cycling and 16 Applied Transient Tests (Power 17 Service)............................................................... 9-6 18

9.7.3 Test C:(DAT and Production Testing) 19 Low-Temperature Low-Voltage Tests.............. 9-9 20

9.7.4 Test D:(DAT and Production Testing) 21 Low-Temperature High-Voltage Tests ........... 9-10 22

9.7.5 Test E: (DAT and Production Testing) 23 High-Temperature High-Voltage Tests .......... 9-10 24

9.7.6 Test F: (DAT and Production Testing) 25 High-Temperature Low-Voltage Tests ........... 9-11 26

9.7.7 Test G: Test Termination (All tests) .............. 9-11 27

9.7.8 Test H: Appraisal of Equipment under 28 Test ................................................................... 9-12 29

9.8 VIBRATION TEST (DAT) .......................................9-13 30


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ATC Controller – Expedited Standards Development Page vii Rev. 5 Ballot Draft

9.8.1 Purpose of Test................................................ 9-13 1

9.8.2 Test Equipment Requirements....................... 9-13 2

9.8.3 Resonance [Mechanical Resonant 3 Frequency] Search (DAT)................................ 9-13 4

9.8.4 Endurance Test (DAT) ..................................... 9-14 5

9.8.5 Disposition of Equipment under Test ............ 9-14 6

9.9 SHOCK (IMPACT) TEST (DAT/PRODUCTION) .........9-14 7

9.9.1 Purpose of Test................................................ 9-14 8

9.9.2 Test Equipment Requirements....................... 9-15 9

9.9.3 Test Procedure (DAT/Production) .................. 9-17 10

9.9.4 Disposition of Test Unit .................................. 9-17 11

9.10 POWER INTERRUPTION TEST PROCEDURES 12

(DAT) 9-17 13

9.10.1 Short Power Interruption ................................ 9-18 14

9.10.2 Voltage Variation ............................................. 9-18 15

9.10.3 Rapid Power Interruption................................ 9-18 16

10 PERFORMANCE AND MATERIAL 17

REQUIREMENTS............................................ 10-1 18

10.1 GENERAL ............................................................10-1 19

10.1.1 Furnished Equipment...................................... 10-1 20

10.1.2 Edges ................................................................ 10-1 21

10.1.3 Hardware .......................................................... 10-1 22

10.1.4 Electrical Isolation ........................................... 10-1 23

10.1.5 Component Sources........................................ 10-1 24

10.1.6 Capacitors ........................................................ 10-2 25

10.1.7 Resistors .......................................................... 10-2 26

10.1.8 Semiconductors............................................... 10-3 27


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ATC Controller – Expedited Standards Development Page viii Rev. 5 Ballot Draft

10.1.9 Transformers and Inductors........................... 10-3 1

10.1.10 Fuses............................................................ 10-3 2

10.1.11 Switches....................................................... 10-3 3

10.1.12 Wiring, Cabling, and Harnesses ................ 10-4 4

10.1.13 Indicators and Character Displays ............ 10-4 5

10.1.14 Connectors .................................................. 10-5 6

10.1.15 PCB Design.................................................. 10-6 7

10.1.16 Tolerances ................................................... 10-6 8

11 QUALITY CONTROL....................................... 11-1 9

11.1 COMPONENTS......................................................11-1 10

11.1.1 Subassembly, Unit Or Module........................ 11-1 11

11.1.2 Predelivery Repair ........................................... 11-1 12

11.1.3 Manufacturers’ Quality Control Testing 13 Certification...................................................... 11-1 14

12 GLOSSARY ..................................................... 12-1 15

12.1 PHYSICAL UNITS..................................................12-1 16

12.2 MODIFIERS ..........................................................12-1 17

12.3 ACRONYMS AND DEFINITIONS ..............................12-2 18

19

LIST OF TABLES AND FIGURES 20 21 Figure 2-1: Component Parts of the ATC Controller and 22

their Connections. .................................................... 2-2 23

Figure 3-1: API in the ATC Architecture..................................... 3-5 24

Figure 3-2: View of a Typical ATC System Environment.......... 3-7 25

Table 3-1: Anticipated ATC Applications ................................. 3-8 26


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ATC Controller – Expedited Standards Development Page ix Rev. 5 Ballot Draft

Figure 3-3: Main Maintenance/ Support Diagram...................... 3-9 1

Figure 3-4: Manage/ Configure Applications’ Sub-feature 2 Areas........................................................................ 3-10 3

Figure 3-5: Manage External Devices’ Sub-feature Areas...... 3-12 4

Figure 3-6: Facilitate Ease of Maintenance & Future 5 Hardware and Software Updates’ Sub-feature 6 Areas........................................................................ 3-13 7

Figure 5-1: Engine Board Top View............................................ 5-3 8

Figure 5-2: Engine Board/Host Module Stackup (not to 9 scale) ......................................................................... 5-4 10

Table 5-1 Connector Pinout and Signal Names.......................... 5-4 11

Table 5-1: Connector Pinout and Signal Names 12 (Continued)................................................................ 5-5 13

Figure 5-3: Power Failure And Recovery (not to scale)............ 5-9 14

Figure 6-1: Standard Specification & Option Choices.............. 6-2 15

Figure 6-2: Mechanical Dimensions ........................................... 6-3 16

Figure 6-3: Master Mode 1 and Remote Mode 1...................... 6-20 17

Table 7-1: Configuration Command Codes.............................. 7-9 18

Figure 7-1: Relationship of Service Voltage and 19 LINESYNC................................................................ 7-12 20

Figure 7-2: Maximum Basic Dimensions ................................. 7-15 21

Figure 8-1: C1S and C11S Pin Configuration: Refer to 22 ATC 2070 Standard................................................. 8-19 23

Figure 8-2: Connector Diagram ............................................... 8-21 24

Figure 8-3: Details of Ethernet Hub Connections, Typical 25 Use 8-23 26

Figure 8-4:Isolation Boundaries................................................. 8-26 27

Figure 9-1: Test Profile ................................................................ 9-9 28

Figure 9-2: Shock Test Fixture.................................................. 9-16 29


FORWARD

ATC Controller – Expedited Standards Development Page 1-1 Rev. 5 Ballot Draft

1 FORWARD 1 2 The purpose of this document is to define the function calls that are supported by the 3 ATC Application Programming Interface. 4 5 The effort to develop standards for the ATC began with the Federal Highway 6 Administration gathering together a group of users interested in furthering the 7 development of open architecture hardware and software to meet the future needs of 8 Intelligent Transportation Systems. The ATC users group gained the support of the 9 Institute of Transportation Engineers to continue their work in developing standards for 10 the ATC. The American Association of State Highway and Transportation Officials 11 (AASHTO) and the National Electrical Manufacturer’s Association joined with ITE to 12 create a joint effort 13 14 In March 1999, a formal agreement was reached among NEMA, ITE and AASHTO to 15 jointly develop, approve and maintain the ATC standards. Under the guidance of a Joint 16 AASHTO/ITE/NEMA Committee on the ATC, a Working Group was created in order to 17 develop a standard for the Advanced Transportation Controller. The first official meeting 18 of this working group was in November 2002. 19 20 In preparation of this Standards Publication, input of users and other interested parties 21 was sought and evaluated. Inquiries, comments and proposed or recommended 22 revisions should be submitted to: 23 24

Standards Development Engineer 25 Institute of Transportation Engineers 26 1099 14th Street, NW, Suite 300 West 27 Washington, DC 20005-3438 28 29 voice:202-289-0222 30 fax:202-289-7722 31


FORWARD


2 INTRODUCTION 1

2.1 Scope 2 With the growth of Intelligent Transportation Systems, transportation management 3 increasingly relies on electronically controlled devices deployed in the field and the 4 controllers that coordinate and relay data from those devices. This standard describes a 5 family of advanced, ruggedized, field communications and process controllers that are 6 configurable for a variety of traffic management applications. Typically, they provide 7 communication, control, and data gathering from and to 8 9

• Central control computers when appropriate 10

• Other controllers when appropriately configured 11

• Control units for devices deployed in the field, typically in the vicinity of and linked 12 to the controller. 13

14 Essentially, an ATC is a special function computer that must be able to operate remotely 15 in a largely unattended mode in the harsh environment of field deployments throughout 16 the United States. 17 18 The goal of this standard is to provide an open architecture design for the next 19 generation of transportation controller applications. These controllers are modular in 20 design and intended to be compatible with or inclusive of existing (present day) traffic 21 controller capabilities. First, the design specified in this standard is based on the 22 concentration of computing power in a single component (the Engine Board) that, is 23 interchangeable with Engine Boards designed by other manufacturers. Second, the 24 standard provides for required and optional features, all of which are based on open 25 standard, common protocol communication standards. Third, the standard is responsive 26 to the functional requirements identified in Section 4 below. Finally, design 27 specifications are given where needed to ensure plug-in compatibility between modular 28 components of any ATC. 29 30 Figure 2-1 provides details of the component parts of the ATC and their connections. 31 32


FORWARD


SP

I IN

TER

FAC

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1 Figure 2-1: Component Parts of the ATC Controller and their Connections. 2


FORWARD


1

2.2 Key Elements Of The ATC Controller Standard 2

2.2.1 Form/Fit/Function 3 4 The ATC provides for easy hardware upgrades to adapt to newer processors, operating 5 systems, and increased memory size and speed. It does this by requiring that the 6 Engine Board (CPU module) conform to a designated specific physical form and pin-out 7 interface. Pins designated as “Reserved” allow for future enhancements to the Engine 8 Board and are not to be used for any purpose. They shall be no-connects on both 9 Engine Board and Host modules. 10 11 While the ATC packaging is ultimately left open to allow manufacturers to be responsive 12 to special needs, this standard describes packaging and interfaces that allow the ATC 13 Controller to be deployed in industry standard cabinet configurations. 14 15 The overall ATC physical design allows for either rack mount or shelf mount cabinet 16 configurations. 17 18

• Controller units shall be capable of being mounted in rack cabinet including, but 19 not limited to, cabinets adhering to the new ITS Cabinet standard and the Model 20 332 cabinet specifications. 21

• If used in standard NEMA TS1 or TS2 cabinet, or the ITS Cabinet (standard 22 concurrently in design), or the Model 332 cabinet, or similar configurations, the 23 controller unit shall be shelf mounted. 24

25 Note that many of the design choices in this standard reflect the basic requirement that 26 the ATC provide backward interface compatibility with existing NEMA TS1, TS2, 27 Caltrans Model 170, NYDOT Model 179, and ATC 2070 controllers and NEMA Model 28 332 and ITS cabinets. 29 30

2.2.2 Engine Board 31 32 All computational functions are concentrated on an Engine Board within the ATC that 33 meets designated minimum requirements on: 34 35

• CPU and RAM memory 36

• FLASH memory storage 37

• Operating System Software 38

• Serial ports 39

• Ethernet interface 40

• Standardized (form, fit and function) pin out interface 41


FORWARD


• Clock/calendar maintenance 1

2

2.2.3 Communications and User Interfaces 3 4 The internal plug-in Communications Interface module is optional. If supplied, it must 5 adhere to the form, fit and electrical interface specifications of the ATC 2070 standard. 6 This standard, however, requires that a slot be made available so that this option can be 7 exercised when needed. 8 9 Section 7 of this standard defines the required front panel interfaces of the ATC and 10 defines the allowable optional interfaces. In this standard user interfaces not specified 11 here as minimum or optional are considered non-compliant. 12 13

2.2.4 Parallel and Serial I/O 14 15 The ATC provides industry-standard communication interfaces for asynchronous and 16 synchronous serial communications. 17

18 This standard also requires a minimum of one synchronous serial port to interface to ITS 19 Cabinet or TS2 Type 1 Cabinet. Optional interface modules defined in this standard 20 include: 21 22

• Serial to parallel interface module for connection to NEMA TS1 or TS2 type 2 23 cabinet 24

• Serial to parallel interface module for connection to Model 332 cabinet 25

26

2.2.5 Software Interface 27 28 The ATC supports the following classes of functions through a standardized API 29 (defined in a separate standard): 30 31

• Serial communications 32

• Field cabinet I/O 33

• FLASH memory file management 34

• Applications task control 35

• Time & date management functions 36

• User interface support 37


FORWARD


2.3 References 1

2.3.1 Normative References 2 3 This standard assumes and is consistent with known versions of ITS cabinet 4 (http://www.ite.org/standards/atc/ITS_Cabinet.pdf) standard (presently in progress). 5 6 ATC Standard for the Type 2070 Controller 7

http://www.ite.org/standards/atc/ATC_2070Standard.pdf 8 9 ATC API Specification 10

http://www.ite.org/standards/atc/atcapi.doc 11 12 NEMA TS2-2002 Traffic Controller Assemblies with NTCIP Requirements (pending 13 NEMA approval) 14 15 USB Specifications 16

17 Universal Serial Bus Specification. Revision 1.1, September 23, 1998. 18 Copyright © 1998, Compaq Computer Corporation, Intel Corporation, Microsoft 19 Corporation, NEC Corporation. All Rights Reserved. 20 21

http://www.usb.org/developers/docs/usbspec.zip 22 23 USB Mass Storage Overview 1.1 24 25

http://www.usb.org/developers/devclass_docs/usbmassover_11.pdf 26 27 USB Mass Storage Bulk Only 1.0 28 29

http://www.usb.org/developers/devclass_docs/usbmassbulk_10.pdf 30 31 USB Mass Storage Control/Bulk/Interrupt (CBI) Specification 1.0 32 33

http://www.usb.org/developers/devclass_docs/usbmass-cbi10.pdf 34 35 36 37 USB Mass Storage UFI Command Specification 1.0 38 39

http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf 40 41

Ethernet 802.3 Specifications 42 43

IEEE 802.3-2002 Specification 44 45 http://standards.ieee.org/getieee802/download/802.3-2002.pdf 46

47


FORWARD


2.3.2 NTCIP Standards 1 2 Where appropriate, this standard supports all relevant requirements of the NTCIP 3 standards for communication between ITS devices. 4 5

6


CONCEPT OF OPERATIONS


3 CONCEPT OF OPERATIONS 1 2 This standard describes a general, field-located computing device that must be capable 3 of executing applications software from various developers. Generally accepted 4 systems engineering practices begin from user needs. This section identifies the 5 presently known user requirements for an ATC and begins to identify the associated 6 functions. Because these users needs and applications are expected to expand in 7 unknown ways in the future, the standard explicitly recognizes that the details of 8 particular future applications use are not completely known at this writing. It is important 9 nonetheless that the support and usage needs of the most commonly known and 10 anticipated applications be defined. 11 12 As indicated above, it is the intent of this standard to describe a general-purpose 13 computing device. As such, the ATC can be seen as analogous to a Personal Computer 14 (PC). A difference between this standard and the PC is that a device meeting this 15 standard must be able to withstand the harsh environment of a field-located device with 16 no special cabinet or environmental conditioning beyond that specified separately in the 17 ITS cabinet standard. Another difference is that the ATC must be able to operate 18 remotely in a largely unattended mode. Similar to the PC, the ATC Controller must 19 adhere to a set of programming conventions and interfaces standards such that the 20 applications software that runs in the device can be developed independently of the 21 hardware and provided in a way that is consistent with the separately developed ATC 22 API standard. 23 24 The ATC Controller must also have a high degree of reliability, be easily maintained and 25 yet must be designed in a cost-effective manner. 26

3.1 Problem Statement 27 28 One of the largest component costs of today’s Intelligent Transportation Systems is 29 associated with the development, testing, deployment and maintenance of applications 30 software. As the current trend continues towards distributing more of the intelligence of 31 ITS out closer to the field, there is an increasing demand for more and more capable 32 field deployable devices. This hardware must run more sophisticated applications 33 software and operate in modern networking environments. The ATC Controller is 34 intended to address these needs. 35 36 The ATC Controller is intended as a next generation, “Open Systems” controller [in 37 which hardware interfaces are generically defined, standardized, and adopted by 38 multiple manufacturers] which follows the “Open Systems” lineage of the ATC 2070 and 39 California Model 170 and New York Model 179 controllers. “Open Systems” in this 40 context refers to the concept of separation of hardware from software by standardizing 41 the interface between the two. This allows software to be developed independent of the 42 hardware. “Open Systems” help protect an agency’s investment by guarding against 43 premature obsolescence due to a manufacturer’s discontinuance of a particular line of 44




equipment or the manufacturer’s ceasing of business operations altogether. 1 Additionally, “Open Systems” typically increase equipment procurement competition; 2 resulting in reduced procurement costs. Deployment, integration, and maintenance costs 3 are also generally reduced because of the commonality and interchangeability of units 4 between various manufacturers reducing spare inventories and technician training costs. 5 6 Another important need for “Open Systems” controllers has to do with the occasional 7 need for custom, specially built, applications. Sometimes the demand for a particular 8 application or custom feature is too small, from an industry-wide standpoint, to be of 9 much interest as a product for manufacturers. Nonetheless, a particular problem or 10 research need may require some unique functionality. With “Open Systems”, software is 11 written to satisfy a specified set of requirements without special support or permissions 12 from the hardware manufacturer. 13 14

3.2 Historical Background 15 16 Many of the design choices in this standard are based on historical trends. This history 17 is included to provide a framework for the decisions represented in this standard. It is 18 also recognized that many legacy systems are presently deployed and that any new 19 technology, such as that specified here, must be capable of interfacing accurately and 20 readily within existing networks of deployed equipment. Therefore, it is appropriate to 21 document the known characteristics of elements of the deployed network. 22 23 In the early 1970’s two concurrent traffic controller standards efforts were initiated in 24 North America. These were the Model 170 standard and the NEMA standard. A brief 25 history of these two standards efforts and the later ATC 2070 standard are presented in 26 the subsections below. 27 28

3.2.1 NEMA 29 The NEMA standard(s) stemmed from a group of manufacturers who joined the NEMA 30 (National Electrical Manufacturers Association) and assembled a core of experienced 31 traffic and electronic engineers to define the first NEMA traffic signal controller. The 32 controller development consisted of an interchangeable electronic device with standard 33 connectors. The NEMA standard further defined traffic terminology and minimum traffic 34 signal control software functionality. Various user agencies that included State, City and 35 County Government Officials were included in this initial definition of the standard. 36 37 The initial standard included the standardization of connectors and connections for three 38 MS style connectors. The inputs and outputs were defined and standardized with 39 respect to electrical levels as well as function. 40 41 The development process ultimately yielded a document labeled the “TS-1” Traffic 42 Controller Assemblies - Standard in 1983. The NEMA standard also defined peripheral 43 devices used in the controller industry and eventual defined the cabinet. The NEMA 44




process requires that every six years the standard is updated and re-ratified. The 1 standard did not cover communications between devices, nor did the standard provide 2 for interchangeability of software functions. 3 4 During subsequent years the demand for communications to provide data transfers 5 between local controllers and central control or on-street master systems increased 6 rapidly. The original TS-1 standard had not defined communication and subsequently a 7 non-standard fourth connector evolved that did not allow interchangeability. The TS-1 8 1989 revision defined/standardized actuated intersection control, provided standards for 9 all cabinet components and added test procedures, and improved interchangeability 10 between manufacturers equipment. 11 12 Over the years, further definitions were recommended to define a safer cabinet to 13 controller interface. This new recommendation included a full SDLC communication 14 protocol to allow the traffic controller and the conflict monitor to communicate between 15 each device and check the intended output with what was actually being displayed by 16 the cabinet. 17 18 This effort generated the most recent "TS-2" standard in 1992 later updated in 1998 and 19 scheduled to be updated in 2004. The standard outlines an expandable and 20 interchangeable traffic controller, cabinets and peripherals. The TS2 standard replaced 21 individual Parallel I/O lines with time slots in a high speed serial data stream, reducing 22 the amount of cabinet wiring and allowing easier addition of new features. The standard 23 however, did not accommodate interchangeable software among the various 24 manufacturers. Features found in one software package were not available in another's 25 package. Also the front panel displays and the information displayed were all different 26 and non standard. The ATC standard addresses both the interchangeability of software, 27 the standardization of displays and the reliance upon a single operating system 28 29

3.2.2 The Model 170 Specification 30 31 The Model 170 specification was developed by Caltrans and New York State DOT to 32 address needs for an “Open Systems” controller for transportation applications. Unlike 33 the NEMA standard, the Model 170 defined controller hardware but not software 34 functionality. The Model 170 approach allows software from any source to be loaded and 35 executed on the controller. The Model 170 obtains its hardware / software 36 independence by requiring, by part number specification, the use of specific integrated 37 circuit chips (for CPU and Serial Communications functions). In addition, a memory map 38 was defined so that software developers would know precisely where to address input 39 and output functions regardless of who manufactured the hardware unit. 40 41 While the Model 170’s architecture has been enormously successful and achieves the 42 desired independence of the hardware and software, the Model 170 relied heavily on the 43 specific Motorola CPU and serial communications chips (or suitable substitutes). 44 Unfortunately, these chips have been designated for phased-out obsolescence. The 45 issue is further compounded by the relatively poor computational performance of the 46




Model 170, compared to today’s controller systems. The applications software written 1 for the Model 170 CU is written in assembly language which makes it difficult to move to 2 a different CPU. Also, the Model 170, without a dedicated CPU for communications, 3 cannot handle the performance demands of today’s modern packet based high speed 4 communications networks. Few options currently exist for those agencies heavily 5 invested in Model 170 software/hardware to preserve their investments in Model 170 6 applications software. 7 8

3.2.3 The ATC 2070 Standard 9 10 The ATC 2070 is a current generation “Open Systems” controller system and is 11 recognized explicitly within this standard. It was originally developed by Caltrans and 12 City of Los Angeles to address some of the shortfalls associated with the Model 170 as 13 discussed above. Its designers tried to mitigate some of the potential parts obsolesce 14 issues which plague the Model 170. Instead of relying on the efficiency of assembly 15 language programming, the ATC 2070 CU includes the necessary resources to execute 16 programs written in high level programming languages such as ANSI C or C++. Such 17 high-level language programs are more easily written and debugged, and are capable of 18 being ported to other hardware platforms as necessary. The ATC 2070 also specifies the 19 use of an O/S(OS-9 to separate the hardware from the application software). By 20 specifying an O/S, the explicit mapping of User Memory and Field I/O, as was done with 21 the Model 170, is no longer necessary. The O/S and associated standardized support 22 functions take care of many of the basic execution management and scheduling tasks 23 required by application software programs. The O/S further extends the 24 hardware/software independence through I/O and memory resource sharing capabilities. 25 These capabilities allow multiple independent applications to be run simultaneously on a 26 single controller unit in a multi-tasking mode. This was not the case with a Model 170. 27 28 The ATC 2070 standard also provides for greater subcomponent interchangeability and 29 modularity than the Model 170. ATC 2070 component modules are defined through 30 specification such that they are interchangeable among different manufacturers. 31 With the Model 170 only the Modem/Communication and Memory modules are 32 interchangeable among controllers produced by different manufacturers. 33 34 However, the ATC 2070 requires that a specific CPU chip and a specific commercial 35 O/S be used. Unfortunately, the embedded hardware and O/S market place is not as 36 large as is the PC marketplace. As a result, longevity concerns are surfacing for the 37 ATC 2070 related to the its particular O/S and CPU selections. Many users are 38 concerned that additional retrofit and software porting costs would be required should 39 either this O/S and/or the CPU become unavailable. 40 41

3.3 Functional Needs 42 43




The ATC Controller standard is particularly interested in addressing the longevity 1 concerns surrounding the ATC 2070. In particular, with the accelerated pace of 2 microprocessor technology advancement and quicker obsolescence cycles, it is 3 desirable not to specify any particular CPU chip set or particular O/S as is done by other 4 standards. To decrease the reliance on a particular technology, a standardized API is 5 required which provides a consistent software platform for all ATC Controllers today and 6 in the future. 7 8 A separate but coordinated standards effort is defining a standardized API for ATC 9 controller use. The API will include both general operating system functionality and 10 specific functions designed for ATC interfaces and applications. The API standard is 11 expected to specify a source code level interface defined by high-level language function 12 descriptions and header information. ATC manufacturers will provide an a library that 13 supports the API Standard and is compatible with their ATC hardware. Developers can 14 port their software to various ATC controllers by compiling and linking their application 15 with the appropriate API library for the target controller as shown in Figure 3.1. The ATC 16 Controller incorporates by reference this API standard. 17 18 19 20

21 Figure 3-1: API in the ATC Architecture 22

23 An additional need for the ATC is improved network communication interface support. 24 Advanced communication capabilities are becoming increasingly important for ITS field 25 controllers. ITS data communications networks are deploying NTCIP and Internet 26 Protocol (IP) based data communications networks. Peer-to-peer networking 27 capabilities are also increasingly required for advanced control algorithm 28

APPLICATION SOFTWARE

ATC FROM

VENDOR 1

ATC FROM

VENDOR 2

ATC FROM

VENDOR 3

ATC FROM

VENDOR 4

COMPILING AND LINKING USING THE API STANDARD AND LIBRARIES




implementations. For such networks, Ethernet is the connection interface of choice at 1 field controllers. 2 3 Cost-effective design (or improved affordability) is also a goal, particularly for fixed and 4 predefined ITS applications where subcomponent interchangeability is not as important 5 and may be traded off for simplicity of design, smaller size, and/or reduced deployment 6 costs. This standard aims to provide enough flexibility in form factor and packaging to 7 allow manufacturers to offer complete families of designs all of which are application 8 software compatible and meet a minimum set of ATC design standards. As is the case 9 with Personal Computers, many different hardware configurations and designs are 10 envisioned all which would share basic applications software and external interface 11 compatibilities. 12 13 Finally, a further need exists for controller units meeting the standard to be able to cost 14 effectively take advantage of future CPU, serial communications, driver, and memory 15 chip improvements without necessitating the replacement of other controller 16 components. Towards this end, a standardized subcomponent interface is required that 17 defines the form, fit, and function of a circuit board with CPU, serial communications, 18 driver and memory components (referred hereafter as the Engine Board). For further 19 protection against obsolescence, this standard requires that Engine Boards be 20 interchangeable between various manufacturers’ controller units. 21 22

3.4 Operational Environment 23 24 Typically, an operator interfaces to an ATC through one of three mechanisms: 25 26

Remote computer – this type of operation configures and manages ITS 27 applications from a computer located at a traffic management location, such as a 28 Transportation Management Center (TMC) or from a field located computer such 29 as a traffic signal field master controller. 30 31 Local computer – this type of operation performs the same functions as a central 32 computer does, but uses a portable interface device (e.g., laptop, PDA, etc.) 33 connected directly to a port of the ATC. 34 35 Locally – this type of operation uses the front panel or portable interface devices 36 (e.g., keyboard, displays, switches) at the ATC to perform the functions of 37 configuring and managing the ITS applications. 38

39 The connection between the central computer and the ATC runs over a communications 40 network. This can be either hard-wired (cables) or wireless. The network interface at 41 the ATC can be either a serial communications port or Ethernet port. Figure 3-2 depicts 42 the physical architecture of the key components related to a typical ATC based system 43 run from a central location. 44 45 46




1

Local Computer

Central Computer Communications betweenCentral Computer and SignController ( C overed by NTCIP)

Direct Communications betweenSign Controller and Maintenance

Laptop( May be NTCIP)

Local:Roadside cabinet housing the ATC, power distribution, and field I/O interfaces

ATC

2 3

Figure 3-2: View of a Typical ATC System Environment 4 5 The ATC is enclosed in a field-located cabinet. The ATC connects to other cabinet-6 located input/output devices (i.e. load switches, detector sensors, etc.) through serial 7 and or parallel connections. Cabinet input/output devices, in turn, connect to field-8 located elements (i.e. signal head, dynamic message sign, sensors, etc.). 9 10 In practice, there are additional components in a field-located cabinet which support the 11 system including power distribution equipment, monitoring devices, and terminal 12 facilities. The exact device interfaces and cabinet configuration depends on the 13 particular ITS application and type of equipment being deployed. 14 15 As a minimum, the ATC must provide the necessary interfaces to support the ITS 16 Cabinet standard. Additionally, the ATC should provide optional interface support for 17 common legacy cabinets including Model 332, NEMA TS1, and NEMA TS2 types. 18 19

3.5 Representative Usage 20 21 As previously indicated, the functionality of a deployed ATC will depend on the 22 applications software loaded into it. Typical ITS applications to be hosted on the ATC 23 are listed in Table 3-1. 24 25

Traffic Signal Highway Rail Intersections Traffic Surveillance Speed Monitoring Lane Use Signals Incident Management Communications Highway Advisory Radio




Field Masters Freeway Lane Control Ramp Meter High Occupancy Vehicle Systems Variable/Dynamic Message Signs Access Control General ITS beacons Roadway Weather Information

Systems CCTV Cameras Irrigation Control

Table 3-1: Anticipated ATC Applications 1 2 Due to its general-purpose nature, an ATC may be used for future ITS applications that 3 are currently anticipated. These expanded functions may, over time, expand the 4 operational user needs for an ATC. Nonetheless, a number of basic operational usage 5 scenarios can be discerned from present day applications. 6 7 This section identifies and describes some of the most common “use cases” to be 8 supported by the ATC and its applications software. Figure 3-3 provides a top-level view 9 of the operational features offered by a typical ITS application using an ATC. The 10 definition of each feature is provided after the presentation of the diagram. The features 11 in this diagram are subdivided into more detailed features in the text below. For these 12 “use cases”, a more detailed “use case” feature diagram is presented along with 13 corresponding definitions. Section 4 then uses these definitions to organize and define 14 the various functional requirements of an ATC. 15




1 2 3

4

5 6

Figure 3-3: Main Maintenance/ Support Diagram 7 8 The generalized operational features of an ATC can be categorized into three major 9 areas: 10 11

• Manage/Configure Applications 12 • Manage External Devices 13 • Facilitate ease of maintenance & future hardware and software updates 14 15

The Maintenance and Support function includes features for maintenance and 16 update/enhancement of the controller unit’s hardware and/or software. 17

Facilitate ease of maintenance & future hardware and software

updates

Manage/Configure Applications

Local Operator / Remote Computer External Device

Manage External Devices




3.5.1 Manage/Configure Controller Applications 1 2 The various sub-features for managing and configuring software applications are shown 3 in the following figure. The subsequent sections detail these sub-features 4 5

6 Figure 3-4: Manage/ Configure Applications’ Sub-feature Areas 7

8

3.5.1.1 Install/Update Applications Software Quickly and Efficiently 9 This feature allows the local operator or a remote computer to install or update the 10 application software resident on the ATC. 11 12

Manage Clock / Calendar Function and Synchronize with Reliable External Source

Configure and Verify Parameter(s) for Particular Local Applications Upload/Download Data Block(s) as needed to transfer files and accommodate bulk transfers of new application databases

Monitor and Verify Present Application Status

Allow Operator Control of Application (start/stop/run time/etc.)

Facilitate the Long Term Storage of Data for Logging and other Data Storage Applications

Install/Upgrade Operating System Software Quickly and Efficiently

Install/Update Application Software Quickly and Efficiently

Local Operator / Remote Computer




3.5.1.2 Install/Upgrade O/S Quickly and Efficiently 1 This feature allows the local operator to install or update the O/S resident on the ATC. 2 Local upgrade capability is required while remote upgrade capability is considered an 3 optional feature. 4 5

3.5.1.3 Manage Clock / Calendar Function and Synchronize with 6 Reliable External Source 7

This feature is responsible for management of a real-time clock calendar function within 8 the ATC. It allows the operator or a remote computer to interrogate and/or update the 9 current time and date information kept by the ATC. It is responsible for synchronizing 10 the ATC O/S clock to an AC power source or other suitable locally available reference to 11 adjust for internal ATC clock drift. 12 13

3.5.1.4 Configure and Verify Parameters for Particular Local 14 Applications 15

This feature allows the operator or a remote computer to manage and update the 16 currently operational applications data stored in the ATC. 17 18

3.5.1.5 Upload/Download Data Block(s) as needed to Transfer Files 19 and Accommodate Bulk Transfers of new Application Databases 20

This feature allows an operator to remotely or locally download or upload complete data 21 blocks or data files from another computer device. It supports the operator’s ability to do 22 bulk transfers of complete application databases to and from the ATC. 23 24

3.5.1.6 Monitor and Verify Present Applications Status 25 This feature allows an operator to remotely or locally view real-time reports of current 26 applications status. The feature, depending on the application, would allow the operator 27 to view status indicators such as operating modes, failure status, event logs, operation 28 algorithm outputs, input and output states, timer countdowns, etc. 29 30

3.5.1.7 Allow Operator Control Application Execution 31 (start/stop/run time/etc.) 32

This feature allows the operator to manage the starting, stopping, and scheduling of one 33 or more applications on the ATC. 34 35

3.5.1.8 Facilitate the Long Term Storage of Data for Logging and 36 other Data Storage Applications 37

This feature facilitates the long-term storage of data for logging and other data storage 38 applications 39




1

3.5.2 Manage External Devices 2 3 The various sub-features for “managing external devices” are shown in the following 4 figure. The subsequent sections detail these sub-features. 5 6

Figure 3-5: Manage External Devices’ Sub-feature Areas 7 8

3.5.2.1 Manage/Control a Variety of External Field Devices 9 This feature addresses the need for external devices to be controlled remotely (through 10 a local controller using commands from a central computer), locally (from a laptop 11 computer connected to the controller), or from an unattended controller. 12 13

3.5.2.2 Monitor the Output and Status of a Variety of External Field 14 Devices 15

This feature provides the capability for the controller to monitor device output and status 16 and to use that status for local control configuration, failure diagnosis, logging and/or 17 reporting to a local operator or remote computer. 18 19

3.5.3 Facilitate Ease of Maintenance & Future Hardware and 20 Software Updates 21

The various sub-features for “facilitating ease of maintenance & future hardware and 22 software” are shown in the following figure. The subsequent sections detail these sub-23 features. 24 25

Manage/Control a Variety of External Field Devices

Monitor the Status of a Variety of External Devices

Local Operator / Remote Computer

External Device




1 2

Figure 3-6: Facilitate Ease of Maintenance & Future Hardware and 3 Software Updates’ Sub-feature Areas 4

5

3.5.3.1 Maintain/Update Controller Hardware 6 This feature addresses the need for controller unit hardware to be maintained and 7 updated as technology changes and additional functional and performance capabilities 8 are needed. 9 10

3.5.3.2 Maintain/Update Controller Software 11 This feature addresses the need for controller applications software to easily be 12 maintained, updated, or ported between different manufacturers’ hardware units. 13 14

3.5.3.3 Support Diagnostics 15 This feature addresses the need for the controller to support self diagnostic software. 16 17

3.6 Security 18 19 The standard does not explicitly address security issues. However, network 20 communication interfaces have been defined with provisions for data security in mind. If 21

Engineer/Technician

Maintain/Update Controller Hardware

Maintain/Update Controller Software

Support Diagnostics




individual applications require it, security should be addressed either through the 1 software hosted by the ATC or by physically protecting access to the ATC and its 2 interfaces. These are outside the scope of this particular standard. 3 4

3.7 Modes of Operation 5 6 The features identified above were developed with the following three modes of 7 operation in mind: standalone, direct, and distributed. Each of these is discussed below. 8 9 The “standalone” control mode assumes that the ATC is operating in the field without 10 remote monitoring by a central computer or master controller. In this mode, application 11 software is loaded into non-volatile controller memory and used to control and/or monitor 12 externally connected devices such as gates, signals, beacons, signs, etc. Device control 13 is based on locally stored schedule, predefined control algorithms or manual operation 14 by a person present at the controller. Device monitoring might include processing of 15 remote sensor inputs and/or monitoring the results of the controller’s control actions. 16 Under this mode, no communications is assumed to exist between the ATC and central 17 computer or remote master. Local operator interactions take place through the ATC 18 front panel interface, laptop computer, or similar portable device. 19 20 The “direct” control mode assumes that a remote control center or master device 21 controls the external device(s) via commands to the ATC. In this mode, commands are 22 sent from control center/master to the ATC via communications network to affect the 23 operation of local device(s) connected to the ATC. 24 25 The “distributed” control mode is a combination of the first two. Here the local ATC 26 applications software exercises normal control but the operation is managed and 27 synchronized through a communication network connection with a central computer or 28 master. Local control operations may frequently be overridden remotely to meet current 29 needs and situations. 30 31


FUNCTIONAL REQUIRMENTS


4 FUNCTIONAL REQUIREMENTS 1 2 This section defines the Functional Requirements to be supported by the ATC. These 3 functions fall into three major categories: 4 5

• Manage/Configure Controller Applications 6 • Manage External Devices 7 • Facilitate Ease of Maintenance & Future Hardware or Software Updates 8

9 The ATC is fundamentally defined as a general-purpose field computing device 10 supporting many different possible software applications. Therefore the particular 11 functional and sub-functional requirements applicable to any particular ATC 12 implementation cannot be fully defined here and are left to each end-users’ discretion so 13 long as the basic functions described here are supported by the particular ATC. 14 15

4.1 Manage/Configure Controller Applications 16 17

4.1.1 Install and Update Applications Software 18 19 The ATC shall provide hardware to support the installation and update of applications 20 software. If performed locally, this requirement shall be satisfied by the following 21 hardware: 22 23

• Front panel connected dedicated Serial port for interfacing with laptop computer, 24 PDA or similar locally connected device with software for performing this function 25

• Front panel connected dedicated Ethernet port for interfacing with laptop 26 computer, PDA or similar locally connected device with software for performing 27 this function 28

• Front panel portable memory device interface and a minimal front panel user 29 interface for initiating bulk data transfers to and from a portable memory device – 30 satisfied by following requirements: 31

♦ USB port with support for portable memory device and API mechanism for 32 portable memory device file access 33

♦ Front panel display and keyboard or a serial interface for connection to 34 connected Laptop computer or PDA device to serve as an operator interface 35 for initialing file transfers to and from a portable memory device when such a 36 device is connected to USB port per above requirement 37

38 39

If performed remotely, this requirement shall be satisfied by the following hardware: 40




1 • Separate Ethernet port for possible use to communicate with a remote computer 2

device having the necessary software for performing this function. 3

• Separate Serial port for possible use to communicate with a remote computer 4 device having the necessary software for performing this function. 5

6

4.1.2 Installing and Upgrading the Operating System Software 7 8 The ATC shall provide hardware to support the installation and upgrade of drivers, APIs, 9 utilities, etc. This requirement shall be satisfied by the same local (preferred) and 10 remote (in this case, optional) requirements given in Section 4.1.1. 11 12

4.1.3 Maintain Clock/Calendar Function and Synchronize with 13 Reliable External Sources As Needed 14

15 The ATC shall provide hardware to support a reliable clock/calendar function: 16 17

• This Controller shall include resident clock/calendar device to support to the 18 maintenance and backup of current time and date by the controller unit in the 19 absence of service power. 20

♦ Clock/calendar device shall maintain time/date for a minimum of 30 days 21 without AC power applied to the controller. 22

♦ Clock/calendar device drift shall be less than ± 1 minute per 30 days at 25 C. 23

• Applications software executing in the controller shall be able to set time and 24 date on the resident clock/calendar device to the nearest 1/10 sec via the API. 25

• When AC power is applied to the unit, a clock pulse derived from AC power 26 source shall be monitored by the O/S for use in correcting current time for long 27 term drift. 28

• When service power is present, current time/date information should be 29 maintained by the O/S and easily accessed by the application software utilizing 30 the API. 31

• Power transients and short term power outages shall not introduce clock drift. 32

33

4.1.4 Configure and Verifying Parameter(s) 34 35 The ATC shall provide hardware to support the configuration and verification of 36 parameters for particular local applications. 37 38




If performed locally, this requirement shall be satisfied by the following hardware: 1 2

• Front panel display and keyboard(s) to support operator configuring/verifying of 3 application parameter(s) and/or 4

• Serial communication port for locally connected laptop, PDA or similar device 5 with software to support operator configuring/verifying application parameter(s) 6 from this device and/or 7

8 If performed remotely, this requirement shall be satisfied by the following hardware: 9 10

• Serial communications port or 11

• Ethernet port 12

This hardware is understood to be matched with applications support and/or proposed 13 API functions supporting NTCIP transfers through remote system interface. 14 15

4.1.5 Uploading/Downloading Data Block(s) 16 17 The ATC shall provide hardware to support file transfers and bulk transfers of new 18 application databases. 19 20 If performed locally, this requirement shall be satisfied by the following hardware: 21 22

• the Communication port for interface to locally connected laptop, 23 • PDA or similar device with necessary software to support operator 24

configuring/verifying application parameter(s) from this device 25 26 If performed remotely, this requirement shall be satisfied by: 27 28

• Communications port (no provisions for operator data entry), and 29

• presence of applications support and/or proposed API functions supporting 30 NTCIP transfers through that port 31

32

4.1.6 Monitoring and Verifying Present Application Status 33 34 The ATC shall provide hardware to monitor system health overall as well as internal 35 parameters related to particular application such as operating modes, event logs, device 36 failures, algorithm results, etc. 37 38 If performed locally, this requirement shall be satisfied by the following hardware: 39 40

• Communication ports for interface to locally connected laptop, 41




• PDA or similar device with necessary software to support operator monitor and 1 verifying of present applications status from this device 2

3 If performed remotely, this requirement shall be satisfied by the following hardware: 4 5

• Requirements listed above, and 6

• presence of applications support and/or proposed API functions supporting 7 NTCIP transfers through those ports. 8

9

4.1.7 Allowing Operator Control of Application(s) 10 11 The ATC shall provide hardware to support the operator control of start/stop/run times of 12 all applications. 13 14 If performed locally, this requirement shall be satisfied by: 15 16

Communication ports for interface to locally connected laptop, 17 18 PDA or similar device with necessary software to support operator to control 19 application control (start/stop/run time/etc.) 20 21 API allowing controller resident operator interface software to control other 22 applications tasks (start/stop/run time/etc.) [to be verified by API group] 23

24 Remote performance of this function is not supported. 25

26

4.1.8 Facilitate the Long Term Retention of Data 27 28 The ATC shall provide hardware to facilitate long term data logging and other local data 29 storage applications via: 30 31

• SRAM memory for applications to store data 32

• API supported FLASH memory file management system 33

34

4.2 Manage External Devices 35 36

4.2.1 Monitor the Status of External Field Devices 37 38




The ATC shall provide hardware to monitor the status of a variety of external field 1 devices. This standard describes required interfaces to provide standardized 2 communication with external devices via industry-standard asynchronous and 3 synchronous serial communications connections. 4 5 In support of this requirement, this standard call for a minimum of four (4) otherwise 6 undedicated general-purpose serial communications ports for possible interface to 7 external field devices: 8 9

• Each port shall support asynchronous or synchronous communications 10

• Each port shall support a range of baud rates 11

• Ports shall be configurable to various electrical interface standards 12

13 The standard also provides details of packaging and interfaces that allow this controller 14 to be deployed in industry standard cabinets configuration including: NEMA TS2 Types 1 15 and 2, ITS and Model 332 cabinets. The ATC must provide backward interface 16 compatibility with existing NEMA, Models 170, 179, and ATC 2070 controllers. 17 18 One dedicated synchronous serial port to directly interface to (select one as appropriate) 19

• an ITS or 20 • NEMA TS2 Type 1 cabinet or 21 • interface via a parallel I/O module or 22 • to a NEMA TS2 Type 2 or Model 332 cabinet. 23

24

4.3 Facilitate Ease of Maintenance & Future Hardware or 25

Software Updates 26 27

4.3.1 Provide Support for a Standardized API 28 29 The ATC hardware described here supports and implicitly assumes the co-design of an 30 appropriate API (standard for the API is under development separately from this 31 standard) to support the indicated functions and to facilitate the porting of applications 32 software between different CPU and operating systems combinations. It is implicitly 33 understood throughout this standard that the associated API will support, at a minimum, 34 the following classes of functions: 35 36

• Serial communications 37

• Field cabinet I/O 38

• FLASH memory file management 39

• Portable memory devices, as needed 40




• Applications task control 1

• Time & date management functions 2

• User interface support 3

4

4.3.2 Provide a Platform that Allows for Hardware Upgrades 5 6 This ATC standard is intended to provide a general design that readily adapts to newer 7 processors, O/Ss, and increased memory size and speed. In order to maintain an 8 upgrade path for previously deployed ATC 2070 controller units, the engine board form, 9 fit and complement of serial ports of this standard are defined such that older ATC 2070 10 units can benefit from upgrades to technology defined by this standard. While the ATC 11 packaging is ultimately left open to allow manufacturers to be responsive to special 12 needs, this standard describes packaging and interfaces that allow the ATC Controller to 13 be deployed in industry standard cabinet configurations. 14

4.3.2.1 Standardize Controller Packaging 15 16 The overall ATC physical design shall allow for either rack mount or shelf mount cabinet 17 configurations. 18 19

• Controller units shall be capable of being mounted in rack cabinet including, but 20 not limited to, cabinets adhering to the new ITS Cabinet standard and the Model 21 332 cabinet specifications. 22

• If used in standard NEMA TS1 or TS2 cabinet, or the ITS Cabinet (standard 23 concurrently in design), or the Model 332 cabinet, or similar configurations, the 24 controller unit shall be shelf mounted. 25

4.3.2.2 Standardize Engine Board Contents: 26 27 A key design goal of this ATC standard is that it provide for easy hardware upgrades to 28 adapt to newer processors, operating systems, and increased memory size and speed. 29 It does this by requiring that all computational functions be concentrated on an Engine 30 Board within the ATC. To maintain interoperability, the Engine Board (CPU module) 31 shall conform to a designated specific physical form and pin-out interface. Pins 32 designated as “Reserved” allow for future enhancements to the Engine Board and are 33 not to be used for any purpose. They shall be no-connects on both Engine Board and 34 Host modules. Section 5 of this standard designates minimum Engine Board 35 requirements on: 36 37

• CPU and RAM memory 38

• FLASH memory storage 39

• Operating System Software 40




• serial ports 1

• Ethernet interfaces 2

• Standardized (form, fit and function) pin out interface 3

• Real-time clock 4

4.3.2.3 Optional Communication Interface 5 6

The ATC standard includes an optional a plug-in internal Communication Interface 7 module(s) with a standardized interface (form, fit, and function) established such that the 8 Communication Boards of various manufacturers shall operate properly when installed 9 within an another manufacturer’s unit. 10

11 12


ENGINE BOARD DETAILS


5 ENGINE BOARD DETAILS 1

5.1 General Information 2

5.1.1 Engine Board 3 4 The Engine Board is the heart of an ATC. The CPU, all memory devices, serial interface 5 devices and processor housekeeping circuits shall be located on the Engine Board, 6 which shall be interchangeable between manufacturers. The plug-in form factor and 7 standardized connectorization of the Engine Board allow it to fit onto the Host Module 8 of any manufacturer’s controller to suit any particular application. 9 10 The Engine Board is designed as a modular unit with the following features and 11 characteristics: 12 13

• permits uniqueness of overall ATC hardware design while maintaining software 14 compatibility and portability 15

• provides a cost-effective migration path for future capability expansion 16

• provides for interchangeability and innovation between manufacturers 17

• facilitates customization of an ATC for particular applications 18

19 The Engine Board dramatically simplifies future updates of the processor, operating 20 system, memory and other core elements of the ATC. 21 22 These specifications for the Engine Board require a minimum level of real-time 23 processing capability. Suitable software shall also be specified in order to determine 24 whether a proposed Engine Board meets the minimum requirements. Manufacturers are 25 free to add additional capabilities to their Engine Board designs so long as said 26 functionality does not conflict with this specification in any way. 27 28 Guidance: There has been much discussion and debate regarding the approach 29 taken in this document regarding the Engine Board, in particular the obvious ties 30 to the ATC-2070. The consensus of the Project Team from the beginning has been 31 that this work should represent an evolution of that design, rather than a 32 revolutionary new design, and should build upon and enhance the strengths of 33 that design while addressing the shortcomings which prevent the ATC-2070 from 34 adequately meeting current and future requirements as outlined in this document. 35 36 The following concepts were the fundamental basis upon which the functional and 37 design requirements specified herein for the Engine Board have been established: 38 39

• Build on the CPU platform already specified by the ATC-2070. 40




• Encapsulate the CPU-specific elements (CPU, support hardware, and O/S) into a 1 modular form which will provide a reliable migration path for future performance 2 and obsolescence upgrades. 3

• Update existing features of the CPU functionality to make better use of current 4 technology. 5

• Selectively add new features, which may now be available through 6 advancements in technology, only where said features are necessary in order to 7 meet designated functional requirements. 8

• Reference the upcoming ATC API for much of the detailed operational 9 requirements. 10

11

5.1.2 Host Module 12 13 The Host Module shall provide the mechanical and electrical interface to the Engine 14 Board and is responsible for providing sufficient power and interface paths as required 15 by this specification. With the exception of the requirements detailed in this standard, 16 manufacturers are free to construct virtually any type and form of Host Module to meet 17 any specific market need. 18 19

5.2 Mechanical and Physical 20

5.2.1 Board Dimensions and Mechanical Requirements 21 22 The maximum horizontal dimensions of the Engine Board shall be 5.00” L x 4.00” W. 23 The nominal thickness of the PCB material shall be 0.062". 24 25 The Engine Board shall have two interface connectors and four standoff holes, which 26 shall be located as illustrated in Figure 5-1. Each connector shall have fifty pins, 27 numbered 1-50, beginning with pin number 1 as the upper left-hand pin on each 28 connector and with pin numbers increasing left-to-right and top-to-bottom. Pin 1 of each 29 connector shall be clearly marked with the number "1" either in the top layer foil or 30 silkscreen. Standoff holes shall be 0.125" +0.010"/-0" in diameter. A 0.250" keep out 31 area for circuit traces and components, concentric with each standoff hole, must be 32 observed. 4-40 hex threaded standoffs and appropriate length 4-40 mating screws are 33 required to be installed between the Engine Board and the Host Module. The 34 assembled distance between the Engine Board and the Host Module, which includes the 35 standoff height and any necessary washers or shims, shall be 0.650" +0.010"/-0" as 36 shown in Figure 5-2. Any additional hardware necessary to meet the environmental and 37 test requirements of Section 9, such as lock- or split-ring washers, shall also be 38 provided. 39 40 A vertical stackup diagram, showing the Engine Board and its relationship to the Host 41 Module, is shown in Figure 5-2. Components may be placed on either side of the PCB. 42 Component height, with the exception of the interface connectors, shall not exceed 43




0.100” on the bottom (connector side) of the PCB and shall not exceed 0.680" on the 1 top side of the PCB. 2 3 4

Figure 5-1: Engine Board Top View 5 6




1 2 3 4 5 6 7 8 9 10 11 12

Figure 5-2: Engine Board/Host Module Stackup (not to scale) 13

5.2.2 Connector Pinout and Signal Names 14 15 The Engine Board shall have two connectors, designated P1 and P2, which are mounted 16 on the bottom of the PCB. These connectors shall be dual-row, DIN 41612 pin headers 17 with the following specifications: 18 19

distance post-to-post, same row: 0.100" nominal 20 distance post-to-post, between rows: 0.100" nominal 21 representative connector: Hirose PCN10-50P-2.54DSA 22 (or equivalent) 23 Host Module mating connector: Hirose PCN10C-50S-2.54DSA 24 (or equivalent) 25

26 Table 5-1 lists the connector pinouts and signal names. All name designations are from 27 the perspective of the Engine Board (for example, TXD means data transmitted by the 28 Engine Board). 29 30

Table 5-1 Connector Pinout and Signal Names 31 32

Connector P1 Connector P2 1 VPRIMARY 1 VSTANDBY_5 2 VPRIMARY 2 RESERVED 3 VPRIMARY 3 RESERVED 4 VPRIMARY 4 RESERVED 5 GROUND 5 SP2_TXD 6 GROUND 6 SP2_RXD 7 GROUND 7 SP2_RTS 8 GROUND 8 SP2_CTS 9 SP1_TXD 9 SP2_CD

10 SP1_RXD 10 SP2_TXC_INT 11 SP1_RTS 11 SP2_TXC_EXT 12 SP1_CTS 12 SP2_RXC_EXT

Host Module

Engine Board

components allowed

pin/socket connectors

printed circuit boards

0.062" 0.000"

0.612" 0.512"

0.774" 0.712"

1.454"




Connector P1 Connector P2 13 SP1_CD 13 SP5_TXD 14 SP1_TXC_INT 14 SP5_RXD 15 SP1_TXC_EXT 15 SP5_TXC_INT 16 SP1_RXC_EXT 16 SP5_RXC_EXT 17 SP3_TXD 17 RESERVED 18 SP3_RXD 18 RESERVED 19 SP3_RTS 19 USB_DPLUS 20 SP3_CTS 20 USB_DMINUS 21 SP3_CD 21 SP8_TXD 22 SP3_TXC_INT 22 SP8_RXD 23 SP3_TXC_EXT 23 SP8_RTS 24 SP3_RXC_EXT 24 SP8_CTS 25 SP4_TXD 25 SP8_CD 26 SP4_RXD 26 SP8_TXC_INT 27 SP6_TXD 27 SP8_RXC_EXT 28 SP6_RXD 28 CPU_RESET 29 CPU_ACTIVE 29 LINESYNC 30 ENET1_TX_POS 30 POWERDOWN 31 ENET1_TX_NEG 31 POWERUP 32 ENET1_RX_POS 32 SPI_MOSI 33 ENET1_RX_NEG 33 SPI_MISO 34 RESERVED 34 SPI_CLK 35 RESERVED 35 SPI_SEL_1 36 RESERVED 36 SPI_SEL_2 37 RESERVED 37 SPI_SEL_3 38 RESERVED 38 SPI_SEL_4 39 ENET2_TX_POS 39 DKEY_PRESENT 40 ENET2_TX_NEG 40 PROG_TEST 41 ENET2_RX_POS 41 PROG_TEST 42 ENET2_RX_NEG 42 PROG_TEST 43 RESERVED 43 PROG_TEST 44 RESERVED 44 PROG_TEST 45 RESERVED 45 PROG_TEST 46 RESERVED 46 PROG_TEST 47 RESERVED 47 PROG_TEST 48 RESERVED 48 PROG_TEST 49 RESERVED 49 PROG_TEST 50 RESERVED 50 PROG_TEST

1 Table 5-1: Connector Pinout and Signal Names (Continued) 2

3




5.2.3 Environmental Requirements 1 2 Engine boards shall meet all environmental requirements specified in Section 9, 3 ENVIRONMENTAL AND TEST PROCEDURES. All thermal management on the 4 Engine Board must be by convection means only. Testing shall be performed with the 5 Engine Board mounted to a Host Module. The Engine Board shall be mounted using 6 the same construction and retention devices used in the manufacturer's normal 7 production. 8 9

5.3 On-Board Resources 10 11

5.3.1 Central Processing Unit 12 13 The Engine Board shall incorporate a CPU and support circuitry that shall have a 14 minimum computational capability of 80 MIPS calculated using the Dhrystone v2.1 15 benchmark at 25°C. 16 17 Guidance: This benchmark is intended only to specify a minimum level of 18 performance for the CPU. It is understood that this benchmark alone does not 19 completely characterize the overall performance of the ATC in a typical 20 application. 21 22

5.3.2 Startup Considerations 23 24 The Engine Board low-level hardware and O/S software initialization shall be completed 25 and application software shall be capable of exercising control of all ATC unit hardware 26 within a maximum of 4.5 seconds from the rise of both the POWERUP and 27 POWERDOWN signals to the HIGH state (see Figure 5-3). In order that the startup time 28 requirement may be verified, an application program shall be provided by the 29 manufacturer, as an independently-loaded software module, which will activate the 30 CPU_ACTIVE signal. 31 32 The Engine Board shall provide circuitry to prevent writing to the SRAM area and to 33 keep the processor in a RESET state any time that VPRIMARY is less than the 34 minimum-specified operating voltage regardless of the state of the POWERUP or 35 POWERDOWN signals. 36 37

5.3.3 Memory 38 39 FLASH Memory 40 41




The Engine Board shall provide FLASH for the storage of O/S software and user 1 application programs. A minimum of 6MB of FLASH shall be provided exclusively for 2 application program storage. FLASH devices shall use a segmented architecture 3 allowing erasing, writing and reading of individual segments. Access to this memory 4 shall be accomplished with wait states totaling no more than 100 ns and a data bus 5 width of no less than 16 bits. 6 7 Application software shall be capable of reading from and writing to the FLASH without 8 the FLASH being corrupted by the power fail conditions specified in Section 5.4.1. 9 10 Dynamic RAM (DRAM) 11 12 The Engine Board shall contain a minimum of 16MB of DRAM or equivalent volatile 13 memory for application and O/S program execution. This memory shall be organized in 14 the native word length of the CPU for maximum performance and shall operate with zero 15 wait states. 16 17 Static RAM (SRAM) 18 19 The Engine Board shall contain a minimum of 1MB of SRAM memory for non-volatile 20 parameter storage. Access to this memory shall be accomplished with wait states 21 totaling no more than 100 ns and a data bus width of no less than eight bits. In the 22 absence of primary Engine Board power VPRIMARY the SRAM shall be supported and 23 maintained by the standby power source VSTANDBY_5. 24 25

5.3.4 Real-Time Clock (RTC) 26 27 A software-settable, hardware RTC shall be provided. The clock shall track, as a 28 minimum, seconds, minutes, hours, day of month, month and year. The RTC must 29 provide one-second accuracy within 0.1 second resolution. This accuracy and resolution 30 may be provided entirely by the RTC hardware or may be supported by OS or API 31 software as needed. In the absence of primary Engine Board power VPRIMARY the 32 RTC shall operate from the standby power source VSTANDBY_5 and shall maintain an 33 accuracy of ± 0.005% per 30 days at 25°C. 34 35 Guidance: It is understood that the controller's RTC and internal software clock 36 will need to be periodically resynchronized with an external source, either via 37 system communications or by a local WWV or GPS receiver. 38 39

5.3.5 ATC Controller API Support 40 41 The ATC API provides for a standardized API in support of all hardware features and 42 functionality of the Engine Board as well as other controller components and modules. 43 All Engine Board components, including but not limited to the processor, all memory 44




components and support circuitry, must be capable of providing the required functionality 1 in its entirety as defined by the ATC API. 2 3

5.4 Electrical Interface 4 5

5.4.1 Power 6 7 Operating Voltages and Currents 8 9 Primary power shall be applied to the Engine Board between the VPRIMARY and 10 GROUND interface pins. The Engine Board shall be capable of operation from any 11 supply voltage ranging from +4.8VDC to +5.2VDC on the VPRIMARY supply. The 12 power requirement shall not exceed 10.0 W from the VPRIMARY supply. Any additional 13 voltages required for normal operation by the Engine Board shall be derived from the 14 VPRIMARY supply by circuitry located on the Engine Board. 15 16 The Engine Board does not provide standby power in support of the SRAM or RTC. In 17 the absence of primary Engine Board power, VPRIMARY, these components shall be 18 supported and maintained by the standby power source VSTANDBY_5 provided by the 19 Host Module. That is, standby power shall be provided only from the Host and not from 20 any source located on the Engine Board itself. VSTANDBY_5 shall provide standby 21 power to the Engine Board over the voltage range of VPRIMARY down to 2.0 VDC. 22 VSTANDBY_5 is allowed to fall below 2.0 VDC, but in that case it will not be considered 23 to be providing standby power. The maximum average current draw from 24 VSTANDBY_5 shall be 8.0 µA over the standby voltage range of 4.5 VDC to 2.0 VDC. 25 Alternatively, a maximum instantaneous current draw of 4.0 µA measured at the SRAM 26 or RTC devices, at a voltage of 2.5 VDC and at 25˚ C, shall be considered equivalent to 27 the maximum average current draw requirement stated above. 28 29 PCB Layout Considerations 30 31 Independent power and ground planes shall be provided for each power source and 32 GROUND. No other signal traces may appear on any power or ground plane. 33 34 Power Interruption and Restoration 35 36 The Engine Board must properly interpret and respond to power control signals provided 37 by the Host Module, specifically the POWERUP and POWERDOWN signals. A diagram 38 of these signals and their states under various operational conditions is shown in Figure 39 5-3. 40 41




1 Figure 5-3: Power Failure And Recovery (not to scale) 2

normal controller operation

external controller

power failing

external controller

power restored prior to

reset

external controller

power failing

no external

controllerpower (reset)

external power

restored

normal controlleroperation

POWERUP signal

POWERDOWN signal




1 The Engine Board shall provide circuitry to prevent writing to the SRAM area and to 2 keep the processor in a RESET state any time that VPRIMARY is less than the 3 minimum-specified operating voltage regardless of the state of the POWERUP and 4 POWERDOWN signals. 5 6 POWERUP 7 8 POWERUP is a logic-level input signal to the Engine Board. This input signal is 9 normally in the HIGH state following a controller cold start and during normal operation. 10 A HIGH-to-LOW transition, while the POWERDOWN signal is also in the LOW state, 11 indicates to the Engine Board that all software execution is to be halted and that a cold 12 restart is to be performed once controller power has been restored (POWERUP and 13 POWERDOWN are both HIGH). This condition is considered a long power outage. A 14 HIGH-to-LOW transition while the POWERDOWN signal is in the HIGH state should be 15 ignored. 16 17 POWERDOWN 18 19 POWERDOWN is a logic-level input signal to the Engine Board. This input signal is 20 normally in the HIGH state following a controller cold start and during normal operation. 21 A HIGH-to-LOW transition indicates to the Engine Board that AC power to the ATC has 22 been lost. This signal serves as an advance warning of an impending power failure, and 23 can be used to trigger data storage or other pre-shutdown activities. Should the 24 POWERDOWN signal transition from LOW-to-HIGH with the POWERUP signal in the 25 HIGH state, the application software shall continue operating normally without a restart. 26 This condition is considered a short power outage. 27 28

5.4.2 Synchronization 29 30 LINESYNC 31 32 The LINESYNC signal is an input to the Engine Board and provides a 50% duty cycle 33 square-wave at 60Hz. This signal is at logic-level between VPRIMARY and GROUND, 34 and is used to provide a periodic interrupt to the CPU for use as a O/S clock reference. 35

5.4.3 Serial Interface Ports 36 37 Serial Communications Interface Ports 38 39 The Engine Board shall provide seven serial communications ports. These ports are 40 described below. Each port shall be capable of operating at a completely independent 41 bit rate from all other ports. All interface pins shall operate at logic-levels. Input pins are 42 indicated by (I), output pins by (O). 43 44




1 2 Serial Port 1 (SP1) 3

4 Principal Usage: general-purpose 5 Operating Modes: ASYNC / SYNC / HDLC / SDLC 6 Asynchronous Rates (bps): 1200 / 2400 / 4800 / 9600 / 19.2k / 38.4k / 57.6k 7

/ 115.2k 8 Synchronous Rates (bps): 19.2k / 38.4k / 57.6k / 76.8k / 153.6k 9 Interface Pins: SP1_TXD: Transmit Data (O) 10 SP1_RXD: Receive Data (I) 11 SP1_RTS: Request To Send (O) 12 SP1_CTS: Clear To Send (I) 13 SP1_CD: Carrier Detect (I) 14 SP1_TXC_INT: Transmit Clock Internal (O) 15 SP1_TXC_EXT: Transmit Clock External (I) 16 SP1_RXC_EXT: Receive Clock External (I) 17 18

Serial Port 2 (SP2) 19 20 Principal Usage: general-purpose 21 Operating Modes: ASYNC / SYNC / HDLC / SDLC 22 Asynchronous Rates (bps): 1200 / 2400 / 4800 / 9600 / 19.2k / 38.4k / 57.6k 23

/ 115.2k 24 Synchronous Rates (bps): 19.2k / 38.4k / 57.6k / 76.8k / 153.6k 25 Interface Pins: SP2_TXD: Transmit Data (O) 26 SP2_RXD: Receive Data (I) 27 SP2_RTS: Request To Send (O) 28 SP2_CTS: Clear To Send (I) 29 SP2_CD: Carrier Detect (I) 30 SP2_TXC_INT: Transmit Clock Internal (O) 31 SP2_TXC_EXT: Transmit Clock External (I) 32 SP2_RXC_EXT: Receive Clock External (I) 33

Serial Port 3 (SP3) 34 35 Principal Usage: in-cabinet devices 36 Operating Modes: ASYNC / SYNC / HDLC / SDLC 37 Asynchronous Rates (bps): 1200 / 2400 / 4800 / 9600 / 19.2k / 38.4k / 57.6k 38

/ 115.2k 39 Synchronous Rates (bps): 153.6k / 614.4k 40 Interface Pins: SP3_TXD: Transmit Data (O) 41 SP3_RXD: Receive Data (I) 42 SP3_RTS: Request To Send (O) 43 SP3_CTS: Clear To Send (I) 44 SP3_CD: Carrier Detect (I) 45 SP3_TXC_INT: Transmit Clock Internal (O) 46 SP3_TXC_EXT: Transmit Clock External (I) 47




SP3_RXC_EXT: Receive Clock External (I) 1 2

Serial Port 4 (SP4) 3 4 Principal Usage: external user-interface (console) 5 Operating Modes: ASYNC 6 Asynchronous Rates (bps): 1200 / 2400 / 4800 / 9600 / 19.2k / 38.4k / 57.6k 7

/ 115.2k 8 Interface Pins: SP4_TXD: Transmit Data (O) 9 SP4_RXD: Receive Data (I) 10 11

Serial Port 5 (SP5) 12 13 Principal Usage: in-cabinet devices 14 Operating Modes: SYNC / HDLC / SDLC 15 Synchronous Rates (bps): 153.6k / 614.4k 16 Interface Pins: SP5_TXD: Transmit Data (O) 17 SP5_RXD: Receive Data (I) 18 SP5_TXC_INT: Transmit Clock Internal (O) 19 SP5_RXC_EXT: Receive Clock External (I) 20

21 Serial Port 6 (SP6) 22 23

Principal Usage: front panel user-interface 24 Operating Modes: ASYNC 25 Asynchronous Rates (bps): 1200 / 2400 / 4800 / 9600 / 19.2k / 38.4k / 57.6k 26

/ 115.2k 27 Interface Pins: SP6_TXD: Transmit Data (O) 28 SP6_RXD: Receive Data (I) 29 30

Serial Port 8 (SP8) 31 32 Principal Usage: general-purpose 33 Operating Modes: ASYNC / SYNC / HDLC / SDLC 34 Asynchronous Rates (bps): 1200 / 2400 / 4800 / 9600 / 19.2k / 38.4k / 57.6k 35

/ 115.2k 36 Synchronous Rates (bps): 19.2k / 38.4k / 57.6k / 76.8k / 153.6k 37 Interface Pins: SP8_TXD: Transmit Data (O) 38 SP8_RXD: Receive Data (I) 39 SP8_RTS: Request To Send (O) 40 SP8_CTS: Clear To Send (I) 41 SP8_CD: Carrier Detect (I) 42 SP8_TXC_INT: Transmit Clock Internal (O) 43 SP8_RXC_EXT: Receive Clock External (I) 44

45 46 47




1 2 Serial Peripheral Interface Port 3 4 The Engine Board shall provide a synchronous Serial Peripheral Interface Port. All SPI 5 interface pins shall be at HCT logic-levels. Input pins are indicated by (I), output pins by 6 (O). 7 8 The implementation of SPI_SEL_1 is required to support DataKey operations. 9 10 The implementation of SPI_SEL_2 is required to support a Host Module serial EEPROM 11 device containing controller configuration information. The content and organization of 12 the information will be managed by the ATC API. This EEPROM device shall have the 13 following characteristics: 14 15

• shall be a 25010-type (1K-bit) SPI EEPROM device (organized as 128x8) 16 • shall provide 5V interface signals 17 • shall operate properly with up to a 2.0 MHz SPI clock 18 • shall utilize SPI Mode 0 (CPOL=0, CPHA=0) 19 • shall be write-protected (using *WP pin) whenever POWERUP is LOW 20 • shall be readable from application software during normal ATC operation 21

22 SPI_SEL_3 and SPI_SEL_4 are currently unimplemented and are reserved for future 23 SPI-related expansion. 24 25 Serial Peripheral Interface (SPI) 26 27

Principal Usage: DataKey / serial EEPROM interface 28 Operating Modes: SYNC 29 Synchronous Rates (bps): (application-specific) 30 Interface Pins: SPI_MOSI: Master-Out-Slave-In (O) 31 SPI_MISO: Master-In-Slave-Out (I) 32 SPI_CLK: Clock (O) 33 SPI_SEL_1: Select 1 (O) 34 SPI_SEL_2: Select 2 (O) 35 SPI_SEL_3: Select 3 (O) 36 SPI_SEL_4: Select 4 (O) 37

38 Universal Serial Bus (USB) Port 39 40 The Engine Board shall provide a USB port. This port shall facilitate the transfer of large 41 data files to and from the controller through the use of USB-based memory devices and 42 is intended to provide a simple alternative to a laptop computer. 43 44 The following minimum requirements for this port have been established: 45 46




• The USB port, as a minimum, shall conform to the appropriate sections of the 1 USB v1.1 specification for both hardware and software operation in order to 2 support bulk transfer operations. 3

• To facilitate the transfer of files between dissimilar equipment, all USB memory 4 devices shall be formatted using the FAT16 file system. This provides for a 5 maximum per-device storage capacity of 2GB (assuming 32kB clusters). 6

7 Specific operational requirements for file transfers via the USB port shall be dictated by 8 the ATC API Standard. 9 10

Interface Pins: USB_DPLUS: Data Line Positive (I/O) 11 USB_DMINUS: Data Line Negative (I/O) 12

13 Ethernet Ports 14 15 The Engine Board shall provide two 10BASE-T Ethernet ports which fully conform to the 16 applicable requirements of IEEE 802.3-2002. Each port must have a unique 48-bit MAC 17 address. All components necessary to produce the Ethernet physical layer (PHY) for 18 each port, including the magnetic interface module, shall be located on the Engine 19 Board. 20 21 Guidance: Independent hubs for each Ethernet port on the Host Module will 22 provide auto-switching capability in support of both 10BASE-T and 100BASE-T 23 external to the controller. 24 25 Ethernet Interface (ENET) 26 27

Principal Usage: local and network communications 28 Operating Mode: synchronous, Manchester-encoded, differential 29 Synchronous Rates (bps): 10M 30 Interface Pins: ENET1_TX_POS: Port 1 Transmit Data Positive (O) 31 ENET1_TX_NEG: Port 1 Transmit Data Negative (O) 32 ENET1_RX_POS: Port 1 Receive Data Positive (I) 33 ENET1_RX_NEG: Port 1 Receive Data Negative (I) 34 ENET2_TX_POS: Port 2 Transmit Data Positive (O) 35 ENET2_TX_NEG: Port 2 Transmit Data Negative (O) 36 ENET2_RX_POS: Port 2 Receive Data Positive (I) 37 ENET2_RX_NEG: Port 2 Receive Data Negative (I) 38

39

5.4.4 Programming/Test Port 40 41 Interface pins are available on the Engine Board for a manufacturer-specific 42 programming and test port. Pins for this purpose are designated PROG_TEST. This 43 optional port (or ports) may be used for programming and testing of any on-board 44 device(s). Examples of this test port (or ports) include JTAG, BDM, Boundary-Scan, 45




custom CPLD programming, and proprietary In-Circuit FLASH programming. 1 Manufacturers are free to designate these pins for these purposes in any configuration 2 on special Engine Board test adapter hosts, however all mating PROG_TEST pins on 3 production ATC Controller Host Modules shall be no-connects. 4 5 Manufacturers are also free to place programming and test connectors directly on the 6 Engine Board, subject to the component placement height restrictions in Section 5.2.1. 7 8

5.4.5 Miscellaneous 9 10 CPU_RESET 11 12 CPU_RESET is an active-low, logic-level output signal generated by the Engine Board. 13 This signal shall be provided to reset other system devices and shall be accessible to 14 application programs through the ATC-API. 15 16 CPU_ACTIVE 17 18 CPU_ACTIVE is an active-low, logic-level output signal generated by the Engine Board. 19 This signal shall be provided to indicate an active CPU and shall be accessible to 20 application programs through the ATC-API. 21 22 A typical use for this signal is to drive a front-panel 'active' or 'health' LED. 23 24 DKEY_PRESENT 25 26 DKEY_PRESENT is an active-low, logic-level input signal to the Engine Board. When 27 this signal is active, it indicates the physical presence of a key in the DataKey 28 receptacle. 29 30 RESERVED 31 32 All pins marked as RESERVED are reserved for future enhancements to the Engine 33 Board and are not to be used for any purpose. They shall be no-connects on both the 34 Engine Board and Host Module. 35 36 37

DRAFT ATC Controller Standard COMMUNICATION INTERFACE DETAILS


6 COMMUNICATION INTERFACE DETAILS 1

6.1 General Description 2 3 The Communications Interface performs the signal conditioning needed to adapt the 4 ATC serial I/O to various transmission media, such as phone lines, radio and optical 5 fiber. 6 7 This Communications Interface Standard Section includes the following: 8 9

• Transmission Media 10

• Modulation and Demodulation 11

• Mechanical Form Factor 12

13 This Communications Interface Standard Section does not include the following: 14 15

• Bit Rate Generation 16

• Data Content 17

• Error Detection and Indication 18

19 This Communications Interface Standard allows the design and manufacture of 20 hundreds of different varieties of communications modules, interchangeable among 21 vendors. To meet this standard, a Communications Interface shall comply with: 22 23

• Mechanical dimensions and ATC connector of this standard 24

• Front panel connectors of this standard 25

• Modulation methods of this standard 26

27



1 2 3 4 5 6 7 8 9

Figure 6-1: Standard Specification & Option Choices 10 11

6.1.1 Interchangeability Control Guidance 12 13

1. The ATC shall provide at least one communications interface slot. 14

2. Installing communications interface modules in the ATC is optional, not required. 15

3. When used, all communications interface modules shall conform to this standard, 16 including dimensions and pin assignments. 17

4. Communications circuitry may be embedded inside the ATC, providing the field 18 connectors and pin assignments conform to this standard. 19

5. Communications circuitry embedded inside the ATC does NOT exempt the ATC 20 from providing at least one communications interface slot. 21

22

CHOICE OF MEDIA Specified Connectors For:

Private Line Public Line, Dial-Up Single Mode Fiber Multi Mode Fiber License Free Radio Hardwire, EIA-574 Hardwire, EIA-485 Wireless Infrared Ethernet

Use One or More per Module

CHOICE OF MODULATION Frequency Shift Keying Di Phase ITU V.90 Optical Amplitude Modulation Spread Spectrum Bipolar Base Band Balanced Differential Base Band 3/16 Encode / Decode Manchester

ATC STANDARD ATC Serial Port Connector Multiple Ports per Module



6.1.2 Serial Port Identification 1 2 Each Communications Interface Module may use one or more ATC Serial Ports. For 3 clarity, each Communications Interface front panel connector shall be identified with the 4 connected port. Each front panel serial port legend shall exactly match that listed in the 5 Engine Board section of this standard. For example, a 9-pin EIA-574 connector to Serial 6 Port 1 shall be labeled “SP1” on the front panel. If the front panel connector can be 7 assigned to different serial ports, the front panel legend shall indicate such. For 8 example, if a 9-pin EIA-574 front panel connector can be assigned to SP1 or SP2 via a 9 program switch, the program switch shall also illuminate either an SP1 or SP2 LED. 10 11

6.2 Mechanical Description 12 13

6.2.1 Mechanical Outline Dimensions 14 The ATC Communications Interface uses the ATC 2070 A2 slot mechanical form factor 15 and pin configuration. The mechanical dimensions are as follows: 16 17

18 19

Figure 6-2: Mechanical Dimensions 20



6.2.2 ATC Communications Connector Mechanical Pin 1 Assignments 2

3 PIN ROW A ROW B ROW C 4 1 SP1TXD+ SP6TXD+ SP5TXD+ 5 2 SP1TXD- SP6TXD- SP5TXD- 6 3 SP1RXD+ SP6RXD+ SP5TXC+ 7 4 SP1RXD- SP6RXD- SP5TXC- 8 5 SP1RTS+ SP1TXC0+ SP5RXD+ 9 6 SP1RTS- SP1TXC0- SP5RXD- 10 7 SP1CTS+ SP1TXCI+ SP5RXC+ 11 8 SP1CTS- SP1TXCI- SP5RXC- 12 9 SP1DCD+ SP1RXC+ SP3TXD+ 13 10 SP1DCD- SP1RXC- SP3TXD- 14 11 SP2TXD+ SP4TXD+ SP3RXD+ 15 12 SP2TXD- SP4TXD- SP3RXD- 16 13 SP2RXD+ SP4RXD+ SP3RTS+ 17 14 SP2RXD- SP4RXD- SP3RTS- 18 15 SP2RTS+ SP2TXCO+ SP3CTS+ 19 16 SP2RTS- SP2TXCO- SP3CTS- 20 17 SP2CTS+ SP2TXCI+ SP3DCD+ 21 18 SP2CTS- SP2TXCI- SP3DCD- 22 19 SP2DCD+ SP2RXC+ SP3TXCO+ 23 20 SP2DCD- SP2RXC- SP3TXCO- 24 21 DCGND1 NA SP3TX1+ 25 22 NETWK1 NA SP3TXC1- 26 23 NETWK2 NA SP3RXC+ 27 24 NA LINESYNC SP3RXC- 28 25 NETWK3 POWERUP CPURESET 29 26 NETWK4 POWERDN FPLED 30 27 DCGND1 DCGND1 DCGND1 31 28 +12 VDC -12 VDC +5 STDBY 32 29 +5 VDC +5 VDC +5 VDC 33 30 DCGND1 DCGND1 DCGND1 34 31 +12 VDC +12 VDC +12 VDC 35 32 DCGND2 DCGND2 DCGND2 36 37

Notes: 38 39 1. Signal directions are referenced to the Engine Board, not the Communications Interface. 40

For example, SP1TXD is Serial Port 1 data transmitted from the Engine Board to the 41 Communications Interface. SP1RxD is Serial Port 1 data received by the Engine Board 42 from the Communications Interface. 43

44 2. Multiple Communications Interface slots shall be identical to that shown. Output signals 45

FROM the Engine Board are simply transmitted to all Communications Interfaces 46



modules simultaneously. Line drivers for input signals TO the Engine Board are enabled 1 by activity on that signal, and disabled by lack of activity for 10 bit periods. 2

3

6.2.3 Mechanical Field Connections 4 5 Guidance: 6 7 The following Foreword reprinted from the EIA-574 Standard explains the change 8 from EIA-232 to EIA-574: 9 10 “The EIA-574 standard was developed in recognition of the fact that a defacto 11 interface standard had appeared in industry which, although it used the Circuit 12 Definitions and Electrical Characteristics of EIA-232-D was implemented on a 9-13 pin connector instead of the 25-pin connector specified in that Standard. As no 14 standard existed for this interface many manufacturers incorrectly labeled this 15 defacto interface “RS-232” causing confusion to the user community. EIA-574 16 provides a solution to the problem of incorrect referencing. It also provides the 17 flexibility of a new interface which specifies the use of EIA-562 Electrical 18 Characteristics which, although they are interworkable with EIA-232-D Electrical 19 Characteristics, are capable of higher data signaling rates and being driven from a 20 ± 5 volt supply.” 21

6.2.3.1 EIA-574 Field Connections 22 EIA-574 field connection to the Communications Interface shall be via a 9-pin “D” 23 connector (sockets) mounted on the Communications Interface front panel. The pin 24 assignments are as follows: 25 26

Pin Signal Description Direction 27 1 DCD Carrier Detect In 28 2 RXD Received Data In 29 3 TXD Transmitted Data Out 30 4 NA Not Used 31 5 DC GND DC Reference 32 6 NA Not Used 33 7 RTS Request to Send Out 34 8 CTS Clear to Send In 35 9 NA Not Used 36

37

6.2.3.2 EIA-485 Field Connections 38 EIA-485 field connections to the Communications Interface shall be via a choice of two 39 connector arrangements: 40 41



6.2.3.2.1 EIA-485 Port for Asynchronous Operation 1 EIA-485 field connection for asynchronous operation shall be via a 9-pin “D” connector 2 (sockets) mounted on the Communications Interface front panel. The pin assignments 3 are as follows: 4 5

Pin Signal Description Direction 6 1 TXD+ Transmitted Data Out 7 2 TXD- Transmitted Data Out 8 3 RXD+ Received Data In 9 4 RXD- Received Data In 10 5 NA 11 6 RTS+ Request to Send Out 12 7 RTS- Request to Send Out 13 8 CTS+ Clear to Send In 14 9 CTS- Clear to Send In 15

16

6.2.3.2.2 EIA-485 Port for Synchronous Operation 17 EIA-485 field connection for synchronous operation shall be via a 15-pin “D” connector 18 (sockets) mounted on the Communications Interface front panel. The pin assignments 19 are as follows: 20 21

Pin Signal Description Direction 22 1 TXDATA+ Transmitted Data Out 23 2 DC GND DC Reference 24 3 TXCLOCK+ Transmitter Clock Out 25 4 DC GND DC Reference 26 5 RXDATA+ Receiver Data In 27 6 DC GND DC Reference 28 7 RXCLOCK+ Receiver Clock In 29 8 NA Not Used 30 9 TXDATA- Transmitted Data Out 31 10 DC GND DC Reference 32 11 TXCLOCK- Transmitter Clock Out 33 12 DC GND DC Reference 34 13 RXDATA- Receiver Clock In 35 14 DC GND DC Reference 36 15 RXCLOCK- Receiver Clock In 37 38

6.2.3.3 Internal Private Line Modulator/Demodulator (Modem) 39 Connection 40

Private phone line twisted pair field connections to the Communications Interface shall 41 be via a choice of two connector arrangements: 42 43



6.2.3.3.1 Internal and External Modem Connections 1 M14 AMP connector (sockets) mounted on the Communications Interface front panel. 2 This connector includes signals for transmit twisted pair and receive twisted pair phone 3 lines for use with internal modem, plus EIA-574 signals for use with external modem. 4 The pin assignment is as follows: 5 6

Pin Signal Description Direction 7 A AUDIO IN Phone Line Receive Pair In (4 Wire) 8 B AUDIO IN Phone Line Receive Pair In (4 Wire) 9 C AUDIO OUT Phone Line Transmit Pair Out (4 Wire, I/O 2 Wire) 10 D +5 VDC +5 VDC 11 E AUDIO OUT Phone Line Transmit Pair Out (4 Wire, I/O 2 Wire) 12 F NA 13 H DCD Carrier Detect In 14 J RTS Request to Send Out 15 K TXD Transmitted Data Out 16 L RxD Received Data In 17 M CTS Clear to Send In 18 N DC GND DC Reference 19 P NA 20 R NA 21 22

5.2.3.3.2 Internal Private Line Only Modem Only Connections 23 Nine pin “D” connector (pins) mounted to the Communications Interface front panel. 24 This connector includes signals for transmit and receive twisted pair phone lines for use 25 with internal modem. The NEMA TS-2 pin out assignments are as follows: 26 27

Pin Signal Description Direction 28 1 AUDIO OUT Phone Line Transmit Pair Out (4 Wire), I/O (2 Wire) 29 2 AUDIO OUT Phone Line Transmit Pair Out (4 Wire), I/O (2 Wire) 30 3 NA 31 4 AUDIO IN Phone Line Receive Pair In (4 Wire Only) 32 5 AUDIO IN Phone Line Receive Pair In (4 Wire Only) 33 6 EQ GND 34 7 NA 35 8 NA 36 9 EQ GND 37

38

6.2.3.4 Internal Dial-Up Line Modem Connections 39 Dial-up phone line twisted pair field connections to the Communications Interface shall 40 be via an RJ-11 connector mounted to the Communications Interface front panel. The 41 pin assignments are as follows: 42 43 44 45



Pin Signal Description Direction 1 1 NC 2 2 NC 3 3 Ring 4 4 Tip 5 5 NC 6 6 NC 7

8

6.2.3.5 Single Mode Fiber Connections 9 Single-mode fiber field connections to the Communications Interface shall be via 1300 10 nM threaded FC or 1300 nM ST connector for both transmitters and receivers. 11 12

6.2.3.6 Multi Mode Fiber Connections 13 Multi-Mode fiber connections to the Communications Interface shall be via 820 nM ST 14 connectors for both transmitters and receivers. 15 16

6.2.3.7 Wide Area Radio Connections 17 Wide area radio field connections to the antenna shall be via a TNC coaxial connector. 18 19

6.2.3.8 Infrared Connections 20 Wireless infrared field connections to an external device are via a red transparent 21 window. 22 23

6.2.3.9 Ethernet Connections 24 Ethernet connections to the Communications Interface shall be via an RJ-45 modular 25 jack, with the following pin configuration: 26 27

Pin Signal Description Direction 28 1 TXD+ Transmitter Pair + Out 29 2 TXD- Transmitter Pair - Out 30 3 RXD+ Receiver Pair + In 31 4 NA 32 5 NA 33 6 RXD- Receiver Pair - In 34 7 NA 35 8 NA 36

37



6.3 Operational Description 1

6.3.1 Interface to ATC 2

6.3.1.1 EIA-485 Signals 3 Except NETWORK1-NETWORK4, CPU RESET, POWER UP, POWER DOWN and FP 4 LED, all signal lines of the 96-pin ATC connector shall be electrically EIA-485, balanced 5 differential. The electrical specifications and signal definition shall conform to the 6 requirements of EIA-485. 7 8 The EIA-485 signals are biased by the ATC (not the Communications Interface Module) 9 to provide the following: 10 11

• A 150 Ω resistor connected from DATA+ to DATA- on each simplex receiver. 12

• No termination resistor on each simplex transmitter 13

• 150 Ω resistor connected from DATA+ to DATA- on each half duplex transceiver 14

• A 1.5K resistor from DATA to +5V and a 1.5K resistor from /DATA to DCGND1 to 15 insure a stable state when the Communications Interface Module is not installed. 16

17 18 19

6.3.1.2 Ethernet Signals 20 NETWORK1-NETWORK4 lines of the 96-pin ATC connector shall be 10/100 Base-T 21 Ethernet. Proper selection of circuit board trace width, spacing, and shielding shall be 22 observed for correct characteristic impedance and to prevent cross talk to adjacent 23 signals. 24 25

6.3.1.3 Power Signals 26 DCGND1 shall be the common reference for +5 VDC, +12 VDC, -12 VDC and all 27 signals. 28 29 DCGND2 shall be the common reference for +12 VDC ISO. 30 31

6.3.1.4 Electrical Isolation 32 DCGND2 and +12 VDC ISO as a group shall be electrically isolated from all other 33 signals and power sources as a group, maintaining the isolation specifications of Section 34 10.1.4 “Electrical Isolation”. Equipment ground (EG) shall maintain the isolation 35 specifications of Section 10.1.4 “Electrical Isolation”. 36 37



Communications Interface field connections shall be electrically isolated from all ATC 1 signals, power sources and EG. 2 3 Field connections of the EIA-574 and EIA-485 versions of the Communications Interface 4 shall be optically isolated using devices capable of at least 1 Mbps. 5 6 Field connections of the Ethernet, Private Line Modem and Dial-Up Modem versions of 7 the Communications Interface shall be magnetically isolated via isolation transformers 8 with the proper characteristic impedance. 9 10 Field connections of the Single Mode Fiber, Multi Mode Fiber and Infrared versions of 11 the Communications Interface are inherently isolated via the non-conductive optical 12 media. 13 14 Field connections of the Wide Area Radio version of the Communications Interface are 15 inherently isolated via the non-conductive radio frequency media. 16 17

6.3.2 Modulation and Demodulation 18

6.3.2.1 EIA-574 19 (Guidance: This paragraph is intended to represent the present 2070-7A). 20 21 Description: 22 23 The EIA-574 versions of the Communications Interface shall convert the ATC EIA-485 24 signals to EIA-574 bipolar simplex, meaning each signal is unidirectional, point-to-point, 25 without ability to disable the transmitter. 26 Indicators: 27 28 EIA-574 versions of the Communications Interface shall include the following indicators: 29 30 Front Panel 31 Legend Indicator Function 32

TX ON= Transmitted Data at Field Wire is Positive V, per EIA-574 33 RX ON= Received Data at Field Wire is Positive V, per EIA-574 34

35 Specifications: 36 37 The electrical specifications and signal definition shall conform to the requirements of 38 EIA-574. 39 40

6.3.2.2 EIA-485 41 (Guidance: This paragraph is intended to represent the present 2070-7B). 42 43 44



1 2 Description: 3 4 EIA-485 versions of the Communications Interface shall convert the ATC EIA-485 5 signals to isolated EIA-485, which may be simplex or half duplex. 6 7 Indicators: 8 9 EIA-485 versions of the Communications Interface shall include the following indicators: 10 11 Front Panel 12 Legend Indicator Function 13

TX ON=DATA+ at Field Wire is 0V, DATA- at Field Wire is Positive V 14 RX ON=DATA+ at Field Wire is 0V, DATA- at Field Wire is Positive V 15

16 Specifications: 17 18 The electrical specifications and signal definition shall conform to the requirements of 19 EIA-485. 20 21

6.3.2.3 Private Line Modem 22 Description: 23 24 Private Line Modem versions of the Communications Interface shall convert the ATC 25 EIA-485 signals to modulated audio suitable for communications on an unconditioned 26 private phone line pair, meaning the line is direct wire not connected to a phone 27 company. 28 29 Modulation schemes used here convert the binary “1” and binary “0” bits of the data 30 stream into audio tones, known as the MARK and SPACE. The demodulation scheme 31 consists of converting each of the tones back to binary “1” and binary “0” bits to replicate 32 the original transmitted data stream at the receiving device. 33 34 When RTS is asserted by the ATC, the modem shall transmit the MARK tone for a 35 period of time, allowing the receiving modem to lock on to the tone and assert Carrier 36 Detect (DCD). At the end of this time period, the transmitting modem asserts Clear to 37 Send (CTS), signaling the ATC to begin sending data. At the end of the data packet, the 38 ATC unasserts RTS and the transmitting modem stops sending a tone. DCD is 39 unasserted by the receiving modem. 40 41 A method shall be provided on the front panel to select half or full duplex for a channel, 42 in addition to a front panel method to disable/enable a channel. 43 44 This scheme shall be capable of operating half-duplex on a single phone line, or full 45 duplex on different phone lines, one line for transmission and another line for reception, 46



allowing simultaneous data transmission in both directions, and to disable the modem 1 transmitter, in the event an ATC malfunctions with its RTS constantly asserted. 2 3 A front panel method shall break the power supply current to all channels, allowing the 4 Communications Interface to be inserted into the ATC without causing a reboot or other 5 ATC malfunction other than a normal recoverable communications error. 6 7 A switch, mounted internally, shall implement anti-streaming which shall disable the 8 modem transmitter in the event an ATC malfunctions with its RTS constantly asserted. If 9 RTS is asserted for the specified time, the modem transmitter shall be turned OFF. The 10 anti-streaming timer is reset if RTS is unasserted, or if TXD is active. This switch allows 11 anti-streaming to be disabled for situations where the transmitter is expected to 12 continuously transmit under normal operations. 13 14 Indicators: 15 16 Front Panel 17 Legend Indicator Function 18

TX ON= SPACE Tone at Field Wire 19 RX ON= SPACE Tone at Field Wire 20 CD ON= Received Tone Within Specified Sensitivity and Filter Band 21

22 Modulation Methods: 23 24 Two different modulation methods shall be allowed under this standard as follows: 25 26

6.3.2.3.1 Frequency Shift Keying (FSK), 300 to 1200 bps, 0 to 9600 bps. 27 (Guidance: This paragraph is intended to represent 2070-6A & -6B modulation 28 method). 29 30 Two different FSK versions shall be available, which are 300 to 1,200 bps, as well as 0 31 to 9,600 bps. The two versions differ in the MARK and SPACE tones. The 0 to 9,600 32 bps version handles a wider variety of bit rates, but its higher frequency tones travel 33 shorter distances. For example, both versions transmit at the same power level and 34 receive at the same sensitivity, but phone wire attenuates the higher frequencies of the 0 35 to 9600 bps version more rapidly. (Please refer to wire manufacturer’s specifications for 36 decibels (dB) loss per mile.) 37 38 Specifications: 39 40 The 300 to 1200 bps shall have the following specifications: 41 42

MARK Tone 1.2 KHz 43 SPACE Tone 2.2 KHz 44 Soft Carrier Freq 900 Hz 45 Modulation: Frequency Shift Keying (FSK), Bell Standard 202 46



Data Format: Asynchronous, serial by bit. 1 Line: Type 3002 voice-grade, unconditioned. 2 Transmit Level: 0 to –8 dB at 1.7 KHz, continuously adjustable 3 Sensitivity: 0 to –40 dB 4 Receiver Filter: 20 dB/Octave min. active attenuation outside operating band 5 RTS to CTS Delay: 8 to 14 mS 6 Carrier Detect: 6 to 10 mS within specified MARK sensitivity and band 7 Receiver Squelch: 5.5 to 7.5 mS 8 Soft Carrier OFF: 8 to 12 mS 9 Recovery Time: 22 mS maximum from Transmit to Receive 10 Error Rate: Less than 1 bit in 100,000 bits 11 Signal to Noise: 16 dB over 300 to Controller Hz band 12 Transmit Noise: -50 dB maximum into 600 Ω, 300 to Controller Hz band 13 Anti-Stream Time: 6 to 8 seconds 14

15 The 0 to 9600 bps shall have the following specifications: 16 17

MARK Tone 11.4 KHz 18 SPACE Tone 17.6 KHz 19 Soft Carrier Freq 7.8 KHz 20 Modulation: Frequency Shift Keying (FSK) 21 Data Format: Asynchronous, serial by bit. 22 Line: Type 3002 voice-grade, unconditioned. 23 Transmit Level: 0 to –8 dB at 1.7 KHz, continuously adjustable 24 Sensitivity: 0 to –40 dB 25 Receiver Filter: 20 dB/Octave min. active attenuation outside operating band 26 RTS to CTS Delay: 8 to 14 mS 27 Carrier Detect: 6 to 10 mS within specified MARK sensitivity and band 28 Receiver Squelch: 5.5 to 7.5 mS 29 Soft Carrier OFF: 8 to 12 mS 30 Recovery Time: 22 mS maximum from Transmit to Receive 31 Error Rate: Less than 1 bit in 100,000 bits 32 Signal to Noise: 16 dB over 300 to Controller Hz band 33 Transmit Noise: -50 dB maximum into 600 Ω, 300 to Controller Hz band 34 Anti-Stream Time: 6 to 8 seconds 35

36

6.3.2.3.2 Di-Phase, 2,400 to 19,200 bps 37 (Guidance: This paragraph describes a modulation/demodulation technique to 38 replace legacy 1200 bps FSK modems on existing unconditioned phone lines. 39 Equivalent transmission distances are achieved at 19,200 bps, without software 40 changes. ITU “V” series modems, such as V.90 are not recommended for this 41 application due to the excessive RTS to CTS “training” time in half-duplex polling 42 applications such as NTCIP.) 43 44 Di-phase modulation provides two tones as well as two phases, allowing increased bit 45 rates over FSK modulation. 46



1 2 Specifications: 3 4

Modulation: Differential Di-Phase, EUROCOM Standard D1 5 Data Format: Asynchronous, serial by bit. 6 Line: Type 3002 voice-grade, unconditioned. 7 Transmit Level: 0 to –8 dB at 1.7 KHz, continuously adjustable 8 Sensitivity: 0 to –40 dB 9 Receiver Filter: 20 dB/Octave min. active attenuation outside operating band 10 RTS to CTS Delay: 8 to 14 mS 11 Carrier Detect: 6 to 10 mS at MARK frequency 12 Receiver Squelch: 5.5 to 7.5 mS 13 Soft Carrier OFF: NA (no soft carrier) 14 Recovery Time: 22 mS maximum from Transmit to Receive 15 Error Rate: Less than 1 bit in 100,000 bits 16 Signal to Noise: 16 dB over 300 to 3000 Hz band 17 Transmit Noise: -50 dB maximum into 600 Ω, 300 to 3000 Hz band 18 Anti-Stream Time: 6 to 8 seconds 19

20

6.3.2.4 Dial Up Line Modem 21 (Guidance: This paragraph is intended to represent a standard dial-up modem.) 22 23 Description: 24 25 The Dial Up Modem versions of the Communications Interface shall convert the ATC 26 EIA-485 signals to audio tones attached to public phone lines and switching equipment. 27 The Dial Up Modem shall be capable of data transmission and reception, as well as 28 dialing out and dialing in on a standard analog phone line. 29 30 Indicators: 31 32 Dial Up versions of the Communications Interface shall include the following indicators: 33 34 Front Panel 35 Legend Indicator Function 36

TX ON= Transmitted Data Activity 37 RX ON= Received Data Activity 38 CD ON= Received Tone Present 39 RS ON= RTS Asserted 40

41 Specifications: 42 43 The electrical specifications and signal definition shall conform to the requirements of 44 ITU V.90. Front Panel connector shall be 9-pin “D”. 45 46



6.3.2.5 Single Mode Fiber 1 (Guidance: This paragraph is intended to represent the 2070-6D modulation 2 method.) 3 4 Description: 5 6 The Single Mode Fiber versions of the Communications Interface shall convert the ATC 7 EIA-485 transmitted data to laser light, and laser light to ATC EIA-485 received data. 8 Amplitude modulation (AM) shall be employed, meaning that a logic “0” is transmitted at 9 a high light amplitude (or brightness), while logic “1” is transmitted at a lower (or OFF) 10 amplitude. 11 12 Danger: Be aware that single-mode laser light is invisible to the human eye, but is of 13 sufficient power to cause damage. Never look directly into a laser transmitter. Always 14 cover unused laser transmitters with opaque dust covers. 15 16 Indicators: 17 18 Single Mode Fiber versions of the Communications Interface shall include the following 19 indicators: 20 21 Front Panel 22 Legend Indicator Function 23

TX ON= Transmitter is Emitting High Amplitude Light 24 RX ON= Receiver is Detecting High Amplitude Light 25

26 Specifications: 27 28

Optical 1300 nM Single Mode Laser 29 Transmit Level: -6 to –15 decibels, Continuously Adjustable 30 Receiver Sensitivity -30 decibels 31 Data Rate 100K bps minimum 32 Transmitter Compensation Temperature and aging 33

34

6.3.2.6 Multi Mode Fiber 35 (Guidance: This paragraph is intended to represent the 2070-6D.) 36 37 Description: 38 39 The Multi Mode Fiber versions of the Communications Interface shall convert the ATC 40 EIA-485 transmitted data to light, and light to ATC EIA-485 received data. Amplitude 41 modulation (AM) shall be employed, meaning that a logic “0” is transmitted at a high light 42 amplitude (or brightness), while logic “1” is transmitted at a lower (or OFF) amplitude. 43 44 Indicators: 45 46



Multi Mode Fiber versions of the Communications Interface shall include the following 1 indicators: 2 3 Front Panel 4 Legend Indicator Function 5

TX ON= Transmitter is Emitting High Amplitude Light 6 RX ON= Receiver is Detecting High Amplitude Light 7


Optical 820 nM Multi Mode Light Emitting Diode (LED) 11 Transmit Level: -6 to –15 dBm, Continuously Adjustable 12 Receiver Sensitivity -30 dBm 13 Data Rate 100K bps minimum 14 Transmitter Compensation Uncompensated 15 16

6.3.2.7 Wide Area Radio 17 (Guidance: This paragraph is intended to represent a license-free data radio 18 offering a good combination of distance and data integrity.) 19 20 Description: 21 22 The Wide Area Radio version of the Communications Interface shall convert the ATC 23 EIA-485 transmitted data to RF, and RF to ATC EIA-485 received data. Spread 24 spectrum is employed, meaning that the radio transmits at high power on a range of 25 frequency channels. This insures that the average power transmitted on any one 26 frequency is below the limit to require an FCC license. 27 28 Indicators: 29 30 Wide Area Radio versions of the Communications Interface shall include the following 31 indicators: 32 33 Front Panel 34 Legend Indicator Function 35

TX ON= Transmitted Data Activity 36 RX ON= Received Data Activity 37


Radio Frequency Band 902 – 928 MHz Part 15 Spread Spectrum 41 Data Transmission Simplex, Half Duplex and Full Duplex 42 Data Rate 1200 to 115.2 Kbps, Asynchronous 43 Transmitter Power 1 Watt Maximum 44 Error Rate: Less than 1 bit in 100,000 bits 45 Antenna Isolation: VDE 0884 46



1

6.3.2.8 Infrared 2 (Guidance: This paragraph is intended to represent an interface to a standard 3 PDA. Agencies with single door cabinets shall insure, prior to manufacture, 4 that this line of sight device be positioned so that the user does not have to 5 remove the ATC from the cabinet to utilize the infared feature.) 6 7 Description: 8 9 The Infrared versions of the Communications Interface shall convert the ATC EIA-485 10 transmitted data to light and light to ATC EIA-485 received data. The light beam is 11 infrared, meaning it is outside the visible color range detected by the human eye. The 12 light transmission is similar to a standard television remote control, meaning that its light 13 emission power is safe to the human eye. As with a TV remote control, the transmitting 14 device must be used within the line of sight, aimed towards the controller red window, 15 and located within approximately six feet of the ATC. 16 17 Indicators: 18 19 None 20 21 Specifications: 22 23

Optical: Shall conform to Infrared Data Association Physical Layer 24 Modulation 3/16 Encode / Decode 25 Data Rate 1200 bps to 115.2K bps 26

27

6.3.2.9 Ethernet 28 29 Description: 30 31 The Ethernet version of the Communications Interface shall adapt the ATC NETWK1-4 32 signals. The Ethernet port may be directly tied to NETWK1-4 or buffered as a hub. 33 34 Indicators: 35 36 Due to the higher event speeds of Ethernet, each indication shall be extended 100 mS. 37 Ethernet versions of the Communications Interface shall include the following indicators: 38 39 Front Panel 40 Legend Indicator Function 41

T ON= Transmitted Data or Received Data is logic “1” 42 100 ON= 100 MBPS Data Rate 43

44 45



1 Specifications: 2 3 The electrical specifications and signal definition shall conform to the requirements of 4 IEEE 802.3. 5

6.4 Communications Interface Versions 6 7 Each version of the Communications Interface shall consist of the following: 8 9

• A printed circuit board assembly of the size and shape described in Paragraph 10 5.2.1 11

• A connection to the ATC serial ports and power, as described in Paragraph 5.2.2 12

• One or more communications ports described in Paragraph 5.2.3 13

• Modulation / demodulation circuitry for each port, described in Paragraph 5.3. 14

15 By using different combinations of ports, an unlimited number of Communications 16 Interface versions may be configured, compliant to this standard. 17 18 Guidance: 19 The following is a list of the existing Communications Interface Versions: 20 Part 21 Number Description 22

2070-6A Dual 300 to 1200 bps Modem 23 2070-6B Dual 0 to 9600 bps Modem 24 2070-6D Fiberoptic Communications Interface 25 2070-7A Dual EIA-574 Serial Interface 26 2070-7B Dual EIA-485 Serial Interface 27 28

As new versions are defined, this list will expand. 29 30 Each version may be implemented using any of the following three design methods: 31 32 Dedicated circuit design, each version ordered as separate vendor part numbers 33 Common base board, with selectable modulation via plug-in circuit assemblies 34 Common board, with selectable modulation via digital signal processor (DSP) software 35 36 Please refer to the Joint NEMA/AASHTO/ITE ATC Standard for detailed specifications of 37 the 2070-6A, 2070-6B, 2070-7A and 2070-7B. 38 39 The Joint NEMA/AASHTO/ITE ATC Standard does not include a standard for the 2070-40 6D. The specification for the 2070-6D follows. 41 42 2070-6D Internal Fiber Modem 43 44



The 2070-6D Fiber Modem is a 1300 nM Single Mode fiberoptic transmitter and receiver. 1 The 2070-6D provides two sets of fiber transmitter and receiver pairs that can operate as 2 two independent serial channels (MASTER) or as a fiber repeater (REMOTE) via front 3 panel switch selection. The 2070-6D incorporates powerful laser transmitters that 4 provide high-speed data transmission at long distances. 5 6 2070-6D Operation 7 8 The 2070-6D Fiberoptic Converter is a printed circuit board assembly that plugs into the 9 A2 slot of the ATC 2070 that is used to condition serial ports SP1 and SP2 for use with 10 optical fiber, EIA-232, or EIA-485. The fiber cable attach to the 2070-6D via 1300 nM 11 single mode fiber, FC style threaded connectors 12 13 The 2070-6D has two front-panel switches. The MASTER/REMOTE switch selects 14 whether the 2070-6D is installed in a Master Controller, or a Remote Controller, while 15 the FIBER/DB9 switch enables or disables the EIA-574 and EIA-485 signals. 16 17 The 2070-6D contains internal rechargeable back-up storage that will power the fiber 18 drivers and receivers for more than two hours after loss of controller power, preserving 19 the integrity of the fiber link. 20 21 Operating Modes 22 23 The 2070-6D includes two 2-position front panel programming switches, resulting in four 24 possible operating modes. 25 26 Master Mode 1: MASTER/REMOTE = MASTER, FIBER/DB9 = FIBER 27 28 This mode is used to drive two independent serial fiber links on two independent serial 29 ports. In this mode, serial port SP1 transmits data on Emitter 1, and receives data on 30 Detector 1. Serial port SP2 transmits data on Emitter 2, and receives data on Detector 31 2. In this mode, the 9-PIN connector is disabled. 32 33 Applications: This mode can be used to drive two separate fiber links, but is also 34 commonly used to drive a single critical fiber ring (see Figure 6-3). 35 36 37 38 39



Figure 6-3: Master Mode 1 and Remote Mode 1 1 2 Master Mode 2: MASTER/REMOTE = MASTER, FIBER/DB9 = DB9 3 4 This mode is used to drive two fiber links simultaneously from one serial port, plus a 5 hardwired serial link from a second serial port via the 9-PIN connector. In this mode, 6 serial port SP1 transmits data simultaneously on Emitter 1 and Emitter 2. Data received 7 on SP1 is the logical “OR” of Detector 1 and Detector 2. SP2 data is transmitted and 8 received on the 9-PIN connector. The 9-PIN electrical characteristics conform to EIA-9 574 if SW1, section 1 is ON. The 9-PIN electrical characteristics conform to EIA-485 if 10 SW1, section 1 is OFF. 11 12 Applications: This mode can be used to when the Master Controller is located in the 13 center of a fiber link on SP1. The second serial channel (SP2) is a general purpose EIA-14 574 or EIA-485 serial channel to other devices. 15 16 Remote Mode 1: MASTER/REMOTE = REMOTE, FIBER/DB9 = DB9 17 18 This mode acts as a fiber signal booster/repeater on one serial port, plus a hardwired 19 serial link from a second serial port via the 9-PIN connector. In this mode, data received 20 on Detector 1 is received on serial port SP1 and also retransmitted simultaneously on 21

2070 #1 MOTHERBOARD

2070-6D

TxD

TxD

RxD

RxD

SP1

SP2

EM1

DET1

EM2

DET2

MASTER

DB9 NOT USED

FIBER CABLES

SP2 (NOT USED)

TxD

RxD

DB9

DET2

EM2

FIBER CABLES

SP1

TxD

RxD

2070 #2 MOTHERBOARD

DET1

EM1

REMOTE2070-6D

OR

OR

OR

MODEM FSK

EIA-232

FIBER CABLES

OR TxD

FSK

TxD

RxD

SP2 (NOT USED)

MODEM

DB9EIA-232

DET2

EM2

OR

RxD

2070 #3 MOTHERBOARD

OR

REMOTE2070-6D

DET1

EM1

SP1



Emitter 2. Data transmitted on Emitter 1 is the logical “OR” of data received on Detector 1 2 and data transmitted by SP1. Circuitry is provided to arbitrate collisions. If SP1 is 2 already transmitting data on Emitter 1, data received on Detector 2 is locked out as long 3 as SP1 Request to Send (RTS) is asserted. If data is already being retransmitted from 4 Detector 2 to Emitter 1, SP1 Clear to Send (CTS) is asserted during, and for a short time 5 after, the Detector 2 data. The duration of the CTS delay is either 1 mS or 10 mS after 6 the end of the Detector 2 data. This delay is 1 mS if SW1, section 2 is ON. This delay is 7 10 mS if SW1, section 2 is OFF. The 10 mS delay is recommended for use with baud 8 rates of 9600 or less. The 1 mS delay can be used for higher baud rates. SP2 data is 9 transmitted and received on the 9-PIN connector. The 9-PIN electrical characteristics 10 conform to EIA-574 if SW1, section 1 is ON. The 9-PIN electrical characteristics 11 conform to EIA-485 if SW1, section 1 is OFF. 12 13 Applications: This mode is used to communicate with Remote Controllers via SP1, while 14 boosting the optical signal to the next fiber link. The second serial channel (SP2) is a 15 general purpose EIA-574 or EIA-485 serial channel to other devices (Figure 6-3). 16 17 Remote Mode 2: MASTER/REMOTE = REMOTE, FIBER/DB9 = FIBER 18 19 This mode is reserved for future use. The 9-PIN, Emitters and Detectors are disabled. 20 21 Anti Streaming 22 23 Anti streaming prevents a serial channel from accidentally stalling and locking-up a serial 24 channel. The anti streaming circuit constantly monitors the RTS output of each serial 25 channel. If a serial channel stalls in transmit mode for seven seconds, the CTS input to 26 that channel is unasserted, which takes that channel off-line. The anti streaming circuit 27 continues hold CTS unasserted until RTS is unasserted, whereupon the 7-second anti 28 streaming timer is reset. Anti streaming is enabled when SW4 section 3 is ON. Anti 29 streaming is disabled when SW4 section 3 is OFF. Anti streaming is recommended 30 except for long data streams, such as long uploads or downloads. Long data streams 31 must be broken up into smaller packets if anti streaming is enabled. 32 33 Power Back Up 34 35 The 2070-6D includes internal lithium rechargeable batteries that will power the fiber 36 links for at least two hours upon the loss of power to the controller. The front panel 37 includes a lamp labeled “CHARGED” which illuminates when the batteries are charged 38 to full capacity. 39 40 Fiber Drivers 41 42 One fiber driver consists of EM1. A potentiometer is used to adjust the light output 43 amplitude. The second fiber driver consists of EM2 and a second potentiometer, and 44 operates in a similar fashion. Front panel lamps EM1 and EM2 are provided to indicate 45 the state of EM1 and EM2 fiber drivers. 46 47



DANGER: NEVER LOOK INTO THE FIBER DRIVERS. THE LASER LIGHT IS 1 INVISIBLE TO THE HUMAN EYE, BUT CAN CAUSE EYE DAMAGE. BE AWARE 2 THAT EM1 AND EM2 CAN BE TRANSMITTING UNDER BACK-UP POWER, EVEN 3 WHEN THE CONTROLLER IS NOT POWERED, OR EVEN WHEN THE MODULE IS 4 UNPLUGGED. FOR VISUAL STATUS, ALWAYS USE THE FRONT PANEL LAMPS, 5 NOT THE FIBER CONNECTORS. 6 7 Fiber Receivers 8 9 One fiber receiver consists of DET1, while the second fiber receiver consists of DET2. 10 Front panel lamps DET1 and DET2 provide visual status for each of the fiber receivers. 11 12 9-Pin Connector Communications 13 14

J1 is used for the 9-PIN communications. J1 is programmed by a internal DIP 15 switch on the 2070-6D, to follow either EIA-574 or EIA-485 electrical Port 6: 16 External 10/100 BPS Port (Typically for Controller Diagnostics) 17

. 18 19 Charger 20 21 All of the 2070-6D communications circuitry is powered by back-up voltage to insure the 22 fiber link remains powered. When the batteries are fully discharged, the regulator is shut 23 down, preventing further discharge of the batteries. The 2070-6D contains a charge 24 timer. If the storage device does not fully charge within the specified time, the charger 25 is turned OFF to prevent overheating. 26 27 Connectors 28 29 When programmed for EIA-574 operation, the 9-pin connector pin assignment conforms 30 to Section 6.2.3 31 32 When programmed for EIA-485 operation, the 9-pin connector pin assignment conforms 33 to Section 6.2.3. 34 35 Specifications 36 37

Item Description Min Typ Max Units 38 Ts Storage Temperature, non-operational -40 85 C 39 To Operating Temperature -34 7 4 C 40 Vcc Power Supply Voltage 4.5 5.5 VDC 41 Err Data Transmission Error Rate 0 .001 % 42


PHYSICAL AND USER INTERFACE DETAILS


7 PHYSICAL AND USER INTERFACE DETAILS 1 2

7.1 User Interface General Description 3 4 The User Interface is the device used by an operator to operate the ATC. The User 5 Interface of a controller has traditionally consisted of a keyboard and display, and more 6 recently personal computers and PDA. For example, the User Interface of a NEMA 7 controller is normally a keyboard and display, with NEMA Port 2 allocated to a personal 8 computer or PDA. The ATC 2070 provides its User Interface via either a keyboard and 9 display mounted in its Front Panel Assembly, or a serial port connector for a personal 10 computer or PDA. Going forward, it is the intent of this specification to: 11 12

• Preserve compatibility with existing 2070 ATC User Interface software 13

• Create a standard for future advanced User Interfaces, such as graphics 14

• Adhere to the ATC API specification for software compatibility 15

16 It is not the intent of this specification to: 17 18

• Preserve User Interface interchangeability among vendors 19

• Dictate User Interface requirements, other than minimum and optional 20

• Limit the choices of User Interfaces 21

22

7.1.1 Minimum User Interface 23 24 The User Interface performs two separate and necessary functions 25 26

• User Interface to the Application (Keyboard and Display, for example) 27

• User Interface to the O/S (Updating application software, O/S and API) 28

29 This standard specifies a minimum interface to the Application, plus a minimum interface 30 to the O/S. This minimum interface provides a common method to enter data and 31 update software for all hardware and software suppliers. In addition to the specified 32 minimum interface, optional interfaces are allowed. User interfaces not specified here 33 as minimum or optional are considered non-compliant. 34 35

7.1.1.1 Minimum User Interface to the Application 36 The minimum user interface to the Application shall consist of the following: 37




1 • EIA-232 SP6 connector, 9 pin “D” (Guidance: C60P of 2070 ATC) 2

• Data Key (Consistent with the requirements of ATC 2070) 3

4

7.1.1.2 Minimum User Interface to the O/S 5 The minimum User Interface to the O/S shall consist of the following: 6 7

• EIA-574 SP4 connector for O/S, 9 pin “D” (Guidance; C50S of 2070 ATC) 8

• CPU ACTIVE LED Indicator 9

• Ethernet Port (Guidance: Internal ATC 10/100 hub Port 2) 10

• USB Port, for removable memory device, only. 11

12

7.1.2 Optional User Interfaces 13 14 In addition to the minimum User Interface, the ATC may include one or more optional 15 User Interfaces. 16 17

7.1.2.1 Optional User Interfaces to the Application 18 Option 1: Keyboard, LCD and Bell (Guidance: traditional 2070 ATC) 19 Option 2: Infrared Port for PDA or Laptop (Guidance: PDA IRDA COM2) 20 Option 3: Ethernet interface to graphics device (Guidance: Flat panel 21 LCD) 22

23

7.1.2.2 Optional User Interfaces to the O/S 24 Option 1: Infrared Port for PDA or Laptop (Guidance: PDA IRDA COM2) 25

26 27

7.1.3 User Interface Pin Connections 28 29

SP4 Connector Pinout SP6 Connector Pinout 30 31 Pin Function Pin Function 32 1 NA 1 +5VDC 33 2 SP4 RXD 2 SP6 RXD 34 3 SP4 TXD 3 SP6 TXD 35 4 NA 4 NA 36 5 DCGND1 5 DCGND1 37




6 NA 6 NA 1 7 NA 7 CPURESET 2 8 NA 8 NA 3 9 NA 9 CPU ACTIVE 4

5 Guidance: 6 7 The ATC 2070 C50 Enabled and C60 Enabled signals are not included. The 8 functions of C50S and C60S may be replicated simultaneously on other 9 connectors by simply transmitting the SP4 or SP6 on all connectors and logically 10 “ORing” the received data from all connectors into SP4 or SP6. 11 12 13 14 15 16 17 18 19 20

7.1.4 User Interface Operation 21 22

7.1.4.1 Keyboard, LCD and Bell Operation 23

7.1.4.1.1 Keyboard 24 The Keyboard, at a minimum, shall be capable of the complete single keystroke 25 functionality (without key translations) of the standard ATC 2070 front panel. Each key 26 shall be engraved or embossed with its function character. Minimum key size shall be 27 0.3” x 0.3”. Minimum key spacing shall be 0.5” on centers. The actual keypad 28 arrangement is not specified here 29 30

7.1.4.1.2 CPU ACTIVE LED Indicator 31 The cathode of the CPU ACTIVE LED Indicator shall be electrically connected to the 32 CPU ACTIVE LED signal and shall have the pull-up resistor on the front panel. 33 34

7.1.4.1.3 Display 35 The Display shall consist of a Liquid Crystal Display (LCD), backlight and a contrast 36 control. Other dot matrix display technologies are allowed, but shall meet all 37 requirements of this document. The contrast control can either be a potentiometer or a 38 software-controlled contrast adjustment. If using a potentiometer contrast control, the 39 contrast shall increase with clockwise rotation. If using a software controlled contrast, 40 the contrast control shall be accomplished by pressing the (*) key to enable the 41




adjustment, followed by the (+) key to darken and the (-) key to lighten the contrast. By 1 pressing the (*) key again will disable the contrast adjustment. The contrast adjustment 2 shall provide the entire contrast range of the LCD. 3 4 The Display shall have an LED or electro-luminescent backlight. The backlight shall be 5 turned on and off by the Controller Circuitry. The backlight and associated circuitry shall 6 consume no power when in off state. The Display shall have a minimum of 8 lines with 7 40 characters each with minimum dimensions of 0.10” wide by 0.17” high. The LCD 8 shall be capable of displaying, at any position on the Display, any standard printable 9 ASCII characters as well as the user-defined special characters. 10

7.1.4.1.4 Cursor 11 Cursor display shall be turned ON and OFF by command. 12 13

• When ON, the cursor shall be displayed at the current cursor position. 14

• When OFF, no cursor shall be displayed. 15

16 All other cursor functions shall remain in effect. 17 18

7.1.4.1.5 Reset 19 The User Interface shall be reset once power is applied or have a momentary control 20 reset switch on the PCB that is logic ORed with the CPU RESET Line, producing a 21 USER Interface RESET. Upon User Interface reset being active or receipt of a valid Soft 22 Reset display command, the following shall occur: 23 24

1. Auto-repeat, blinking, auto-wrap, and auto-scroll shall be set to OFF. 25

2. Each special character shall be set to ASCII space (hex value 20). 26

3. The tab stops shall be set to columns 9, 17, 25, and 33. 27

4. The backlight timeout value shall be set to 6 (60 seconds). 28

5. The backlight shall be extinguished. 29

6. The display shall be cleared (all ASCII space). 30

7. The User Interface shall transmit a power up string to /SP6 RXD once power is 31 applied to the User Interface, or the User Interface hardware reset switch is 32 pressed. The string shall be “ ESC [PU”, (hex values “1B 5B 50 55)”. 33

7.1.4.1.6 Key Press 34 When a key press is detected, the appropriate key code shall be transmitted to SP6-35 RXD. If two or more keys are depressed simultaneously, no code shall be sent. If a key 36 is depressed while another key is depressed, no additional code shall be sent. 37 38




7.1.4.1.7 Auto Repeat 1 Auto-repeat shall be turned ON and OFF by command. When ON, the key code shall be 2 repeated at a rate of 5 times per second starting when the key has been depressed 3 continuously for 0.5 second, and shall terminate when the key is released or another key 4 is pressed. 5 6

7.1.4.1.8 Special Characters 7 The controller circuitry shall be capable of composing and storing eight special graphical 8 characters on command, and displaying any number of these characters in combination 9 with the standard ASCII characters. Undefined characters shall be ignored. User-10 composed characters shall be represented in the front panel communication protocol in 11 the 2070 ATC specification. P1 represents the special character number (1-8). Pn's 12 represent columns of pixels from left to right. The most significant bit of each Pn 13 represents the top pixel in a column and the least significant bit shall represent the 14 bottom pixel. A logic ‘1’ shall turn the pixel ON. There shall be a minimum of 5 Pn's for 15 5 columns of pixels in a command code sequence terminated by an “f”. If the number of 16 Pn's is greater than the number of columns available on the LCD, the extra Pn's shall be 17 ignored. P1 and all Pn's shall be in ASCII-coded decimal characters without leading 18 zero. 19 20

7.1.4.1.9 Character Overwrite 21 Character overwrite mode shall be the only display mode supported. A displayable 22 character received shall always overwrite the current cursor position on the Display. The 23 cursor shall automatically move right one character position on the Display after each 24 character write operation. When the rightmost character on a line (position 40) has been 25 overwritten, the cursor position shall be determined based on the current settings of the 26 auto-wrap mode. 27 28

7.1.4.1.10 Auto Wrap 29 Auto-wrap shall be turned ON & OFF by command. When ON, a new line operation 30 shall be performed after writing to the right-most position. When OFF, upon reaching 31 position 40, input characters shall continue to overwrite the right-most position. 32 33

7.1.4.1.11 Cursor Positioning 34 Cursor positioning shall be non-destructive. Cursor movement shall not affect the 35 current display, other than blinking the cursor and momentarily hiding the character at 36 that cursor position. 37 38

7.1.4.1.12 Blinking 39 Blinking characters shall be supported, and shall be turned ON and OFF by command. 40 When ON, all subsequently received displayable characters shall blink at the rate of 1 41




Hz with a 60% ON / 40% OFF duty cycle. It shall be possible to display both blinking 1 and non-blinking characters simultaneously. 2 3

7.1.4.1.13 Tab Stops 4 Tab stops shall be configurable at all columns. A tab stop shall be set at the current 5 cursor position when a SetTabStop command is received. Tab Stop(s) shall be cleared 6 on receipt of a ClearTabStop command. On receipt of the HT (tab) code, the cursor 7 shall move to the next tab stop to the right of the cursor position. If no tab stop is set to 8 the right of the current cursor position, the cursor shall not move. 9 10

7.1.4.1.14 Auto Scroll 11 Auto-scroll shall be turned ON and OFF by command. When ON, a linefeed or new line 12 operation from the bottom line shall result in the display moving up one line. When OFF, 13 a linefeed or new line from the bottom line shall result in the top line clearing, and the 14 cursor being positioned on the top line. 15 16

7.1.4.1.15 Simultaneous Auto Wrap and AutoScroll 17 If AutoScroll is OFF, nothing should happen. If AutoScroll is ON, the display should scroll down 18 one row (so that row 1 is now row 2), the cursor should go to the right-most column of the 19 "new" row 1 and write a SPACE to that location. 20

7.1.4.1.16 Refresh Rate 21 Displayable characters shall be refreshed at least 20 times per second. 22 23

7.1.4.1.17 Backlight Timeout 24 The Display back light shall illuminate when any key is pressed and shall illuminate or 25 extinguish by command. The backlight shall extinguish when no key is pressed for a 26 specified time. This time shall be program selected by command, by a number in the 27 range 0 to 63 corresponding to that number of 10-second intervals. A value of 1 shall 28 correspond to a timeout interval of 10. A value of 0 shall indicate no timeout. 29 30

7.1.4.1.18 Command Codes 31 The Command Codes shall use the following conventions: 32 33 Parameters and Options: Parameters are depicted in both the ASCII and hexadecimal 34 representations as the letter 'P' followed by a lower-case character or number. These 35 are interpreted as follows: 36 37

1. Pn: Value parameter, to be replaced by a value, using one ASCII character per 38 digit without leading zeros. 39

40




P1: Ordered and numbered parameter. One of a listed known parameters with a 1 specified order and number (Continues with P2, P3, etc.) 2

3 Px: Display column number (1- end), using one ASCII character per digit without 4

leading zeros. 5 6 Py: Display line (1- bottom) one ASCII character ...: Continue the list in the same 7

fashion 8 9

Values of 'h' (hex value 68) and 'l' (hex value 6C) are used to indicate binary 10 operations. 'h' represents ON (high), 'l' represents OFF (low). 11

12 2. ASCII Representation: Individual characters are separated by spaces for clarity; 13

these are not to be interpreted as the ASCII space character. 14 15 3. Hexadecimal Representation: Characters are shown as their hexadecimal values 16

and will be in the range 00 to 7F (7 bits). 17 18

7.1.4.1.19 Communications 19 The Controller Circuit shall communicate via a SP6 asynchronous serial interface. The 20 interface shall be configured for 38.4 kbps, 8 data bits, 1 stop bit, and no parity. 21 22

7.1.4.1.20 Bell 23 The User Interface shall include an electronic bell to signal receipt of ^G (hex value 07). 24 Receipt of all other characters and ESC codes shall continue during the time the bell 25 sounds. Bell shall be rated at 70 decibels minimum sound pressure at 4 KHz. 26 27

7.1.4.1.21 Configuration Command Codes 28 29

CONFIGURATION COMMAND CODES ASCII REPRESENTATION HEX VALUE FUNCTION HT 09 Move cursor to next tab stop CR 0D Position cursor at first position on current line LF 0A (Line Fee) Move cursor down one line BS 08 (Backspace) Move cursor one position to the left and

write space ESC 0 Py j Px f 1B 5B Py 3B Px 66 Position cursor at (Px, Py) ESC 0 Pn C 1B 5B Pn 43 Position cursor Pn positions to right ESC 0 Pn D 1B 5B Pn 44 Position cursor Pn positions to left ESC 0 Pn A 1B 5B Pn 41 Position cursor Pn positions up ESC 0 Pn B 1B 5B Pn 42 Position cursor Pn positions down ESC 0 H 1B 5B 48 Home cursor (move to 1,1) ESC 0 2 J 1B 5B 32 4A Clear screen with spaces without moving cursor




CONFIGURATION COMMAND CODES ASCII REPRESENTATION HEX VALUE FUNCTION ESC c 1B 63 Soft reset ESC 0 P1 [ Pn j Pn…f 1B 50 P1 5B Pn 3B…Pn 66 Compose special character number Pn (1-8) at current

cursor position ESC 0 < Pn V 1B 5B 3C Pn 56 Display special character number Pn (1-8) at current

cursor position ESC 0 25 h 1B 5B 32 35 68 Turn Character blink on ESC 0 25 j 1B 5B 32 35 6C Turn Character blink off ESC 0 < 5 h 1B 5B 3C 35 68 Illuminate Backlight ESC 0 < 5 l 1B 5B 3C 35 6C Extinguish Backlight ESC 0 33 h 1B 5B 33 33 68 Cursor blink on ESC 0 33 l 1B 5B 33 33 6C Cursor blink off ESC 0 27 h 1B 5B 32 37 68 Reverse video on (Note 2) ESC 0 27 l 1B 5B 32 37 6C Reverse video off (Note 2) ESC 0 24 h 1B 5B 32 34 68 Underline on (Note 2) ESC 0 24 l 1B 5B 32 34 6C Underline off (Note 2) ESC 0 O m 1B 5B 30 6D All attributes off ESC H 1B 48 Set tab stop at current cursor position ESC 0 Pn g 1B 5B Pn 67 Clear tab stop Pn = 0,1,2 at cursor = 3 all ta stops ESC 0 ? 7 h 1B 5B 30 37 68 Auto-wrap on ESC 0 ? 7 l 1B 5B 30 37 6C Auto-wrap off ESC 0 ? 8 h 1B 5B 30 38 68 Auto-repeat on ESC 0 ? 8 l 1B 5B 30 38 6C Auto-repeat off ESC 0 ? 25 h 1B 5B 30 32 35 68 Cursor on ESC 0 ? 25 l 1B 5B 30 32 35 6C Cursor off ESC 0 ? 47 h 1B 5B 3C 34 37 68 Auto-scroll on ESC 0 ? 47 l 1B 5B 3C 34 37 6C Auto-scroll off ESC 0 < Pn S 1B 5B 3C Pn 53 Set Backlight timeout value to Pn (0-63) ESC 0 Pu 1B 5B 50 55 String sent to ENGINE BOARD when EIPA power up NOTE: 1. Numerical values have one ASCII character per digit without leading zero. 2, Reverse Video & Underline NOT required for Front Panel Assembly Option 1.

Reverse Video is NOT required for Option 2. Command codes shall be available for Option 3 (C60).

1

INQUIRY COMMAND – RESPONSE CODES

COMMAND Engine Board to Front Panel Module

RESPONSE Front Panel Module to Engine Board

FUNCTION

ACIII Representation HEX Value

ASCII Representation HEX Value

ESC 0 6 n 1B 5B 36 60 ESC O Py; Px R 1B 5B Py 3B Px 52 Inquire Cursor Position

ESC 0 B n 1B 5B 42 60 ESC 0 P1; P2;….P6 R

1B 5B P1 3B P2 3B…..P6 52

Status Cursor Position P1: Auto-wrap (h, 1)




P2: Auto-scroll (h, l) P3: Auto-repeat (h, l) P4: Backlight (h, l) P5: Backlight timeout P6: AUX Switch (h, l)

ESC 0 A n 1B 5B 41 6E ESC 0 P1 R 1B 5B P1 52 P1: AUX Switch (h, l) 1 2

Table 7-1: Configuration Command Codes 3 4

7.1.4.2 Serial Port 5 The above key codes, configuration command codes and inquiry command-response 6 codes shall be communicated via SP6 in the absence of a front panel display. In lieu of 7 the keyboard and display, an intelligent device, such as a PDA may be used. 8 9

7.1.4.3 Infrared Port 10 This option specifies short distance wireless communications via a modulated light 11 beam. Please refer to the IRDA standards for operation. 12 13

7.1.4.4 Ethernet Port 14 A 10/100 Ethernet port is used for hardwired communications to external devices. 15 Please refer to the IEEE 802.3 standard for operation. 16 17

7.1.4.5 USB Port 18 USB is used as an interface to memory devices. Refer to USB specification. 19 20

7.1.4.6 Data Key 21 Datakey KeyceptacleTM (KC4210, KC4210PCB or equal) 22 23

7.1.5 User Interface Power Requirements 24 25 The User Interface, shall be powered by 4.8 to 5.2 VDC. Any additional voltages 26 required by the User Interface, such as backlight and communications, shall be derived 27 from this single power source. If the User Interface can be mounted remotely, the typical 28 and maximum current requirements of each User Interface shall be published for each 29 device. 30 31




7.2 Power Supply General Description 1 2 The Power Supply shall be an independent module, cooled by convection only. The 3 Power Supply shall be capable of supporting the internal ATC circuitry, plus provide 4 power for each optional module. The Power Supply shall convert service voltage to the 5 proper DC Voltages at the power rating needed to support the unit and any external 6 power as described in Paragraph 6.2.6. 7 8 The Power Supply must produce all output voltages with the specified tolerances and 9 capacities within 500 ms after the application of external power to the ATC. The Power 10 Supply must also raise the POWERUP and POWERDOWN signals to a HIGH state, 11 indicating that power is stable and available, within this same 500 ms time period. 12 13

7.2.1 "ON/OFF" Power Switch 14 15 An "On/Off" POWER Switch shall be provided to disconnect AC from the Power Supply. 16 The “Power On” shall be in the up position. 17 18

7.2.2 LED DC Power Indicators 19 20 Four LED DC Power Indicators shall be provided to indicate that all required DC 21 voltages meet the following conditions: 22 23

a. +5 VDC is within 4.8V to 5.25V and the ± 12 VDC is within ±8% of nominal. 24

b. 332 Parallel I/O versions, the +12 VDC ISO shall be within ±8%. 25

c. NEMA versions, the +24 VDC shall be within NEMA TS-2 tolerance. 26

7.2.3 Service Voltage Fuse 27 28 A replaceable 3AG slow blow fuse shall be provided. Fuse label shall indicate rating. 29 30

7.2.4 +5 VDC Standby Power 31 32 +5 VDC Standby Power shall be provided to hold up specified circuitry during the power 33 down period. It shall consist of the monitor circuitry, hold up capacitors, and charging 34 circuitry. A charging circuit shall be provided, that under normal operation, shall fully 35 charge and float the capacitors consistent with the manufacturers’ recommendations. 36 The Hold Up power requirements shall be a minimum constant drain of 600 µA at a 37 range of +5 to +2 VDC for over 600 minutes. Capacitors shall be fully charged within 38 one hour. 39 40




7.2.5 Monitor Circuitry 1 2 Monitor Circuitry shall be provided to monitor incoming Service Power for Power failure 3 and Restoration and LINESYNC generation. 4 5

7.2.5.1 Service Fail/Power Down and Sysreset/Power Up 6 Power Fail Calibration for Model 332 and ITS Cabinets: 7 8 The POWER DOWN Output signal shall go LOW (ground true) immediately when the 9 service voltage falls below 92 ±2 VAC. The signal shall transition to HIGH when the 10 service voltage exceeds 97 ± 2 VAC. . 11 12 Power Fail Calibration for NEMA Cabinets: 13 14 The POWER DOWN Output signal shall go LOW (ground true) immediately when the 15 service voltage falls below 85 ±2 VAC. The signal shall transition to HIGH when the 16 service voltage exceeds 90 ± 2 VAC. 17 18 The POWERUP Output signal shall transition to LOW 525 ± 25 ms after POWER DOWN 19 transition to LOW. The signal shall transition to HIGH 225 ± 25 ms after Power 20 Restoration and the supply is fully recovered. 21 22

7.2.5.2 LINESYNC 23 The LINESYNC signal shall be generated by a crystal oscillator, which shall synchronize 24 to the 60-Hz service power line at 120 and 300˚. A continuous square-wave signal shall 25 be +5 VDC amplitude, 8.333 ms half-cycle pulse duration, and 50 ± 1% duty cycle. The 26 output shall have drive sink capability of 16 mA. The monitor circuit shall compensate 27 for missing pulses and line noise during normal operation. The circuit shall continue 28 generating the signal during power fail until the +5 VDC power supply drops below its 29 minimum tolerance. The crystal oscillator used to generate this signal shall have an 30 accuracy of ± 0.005% at 25 C. The relationship of Service Voltage (top trace) and 31 LINESYNC (bottom trace) is shown as follows: 32 33 34 35 36 37




1

Figure 7-1: Relationship of Service Voltage and LINESYNC 2 3

7.2.6 External Power Supply Requirements 4 5 The following external voltages shall be within these parameters. 6 7 Each Optional Communications Interface Module: 8 9 Voltage Tolerances I Minimum I Maximum 10 +5 VDC +4.875 to +5.125 VDC 0.050 A 0.500 A 11 +12 VDC +11.4 to +12.6 VDC 0.050 A 0.100 A 12 -12 VDC -11.4 to –12.6 VDC 0.050 A 0.100 A 13

14 For NEMA TS1 and NEMA TS2 Type 2 versions: 15 16 17 Voltage Tolerances I Minimum I Maximum 18 +24 VDC +22.0 to +26.0VDC 0.050 A 0.500 A 19

20 For 332 Parallel I/O version: 21

22 Voltage Tolerances I Minimum I Maximum 23 +12 VDC ISO +11.4 to +12.6 VDC 0.050 A 0.750 A 24 25 For the Required USB Port: 26 27 Voltage Tolerances I Minimum I Maximum 28 +5 VDC +4.875 to +5.125 VDC 0.000 A 0.500 A 29 30




7.2.6.1 Line and Load Regulation 1 The Power Supply shall meet the external voltage tolerances for minimum and 2 maximum loads called out. 3 4

a. 332 Parallel I/O Version: 100 VAC to 135 VAC ± 2 VAC 5

b. NEMA: 89 VAC to 135 VAC ± 2 VAC 6

7

7.2.6.2 Ripple and Noise 8 Less than 0.5% rms, 2% peak to peak, whichever is greater. 9 10

7.2.6.3 Over Voltage 11 The Power Supply shall clamp at 130% Vout for all outputs. 12 13

7.2.6.4 Inrush Current 14 Cold Start Inrush shall be less than 25A at 115VAC. 15 16

7.2.6.5 Holdup Time 17 The power supply shall supply +5 VDC current budget for 550 ms after power loss at 18 100 VAC. The supply shall be capable of holding up the ATC for two 500 ms Power 19 Loss periods occurring in a 1.5-second period at 100 VAC. Since the Engine Board is 20 powered completely by +5 VDC, no other power supply output voltages shall need to be 21 maintained during power loss to prevent reboot. 22 23

7.2.6.6 Overload Protection 24 25 The power supply shall include automatic overload protection circuitry for each output, 26 as well as the USB +5 VDC output. The overload protection circuitry shall limit the 27 output power during overload conditions, including shorted outputs, without blowing the 28 fuse and without exceeding the ratings of any component. When the overload condition 29 is removed, the output shall automatically recover specified regulation. An overload 30 condition on the +5VDC output may simultaneously limit power of all outputs, as the ATC 31 will be RESET by the drop in +5VDC voltage. Overload on +12VDC, -12VDC, +24 VDC 32 and +12VDC ISO shall not limit the output power of +5 VDC, allowing the Engine Board 33 to log secondary overloads. Overload of the USB +5 VDC output shall not result in 34 overload of any other power supply output. 35 36

7.3 Mechanical and Physical General Description 37 38




1 The ATC Mechanical and Physical attributes provide mechanical enclosure and human 2 engineering, including: 3 4

• Maximum Size 5

• Form Factor 6

• Mounting and Installation Method 7

• Materials 8

• Structural Integrity 9

• Ease of Use 10

• Cost Effectiveness 11

It is the intent of this specification to: 12

• Preserve compatibility with existing cabinet styles 13

• Reduce the size and complexity of existing controllers 14

• Improve human engineering for intuitive use of complex control functions 15

It is not the intent of this specification to: 16

• Interchange electronic modules and mechanical assemblies among vendors 17 (except Communications Interface and Engine Board) 18

• Dictate mechanical details 19

• Preserve existing controller sizes and form factors 20

21

7.3.1 Chassis 22

7.3.1.1 Construction Materials 23 The CHASSIS including supports, mounting surfaces, power supply enclosures and front 24 panel shall be made of 0.063-inch minimum aluminum sheet metal or equivalent 25 strength non-corrosive material. Construction materials shall withstand all environmental 26 standards of this specification. 27

7.3.1.2 Weight 28 The total ATC composition weight shall not exceed 25 pounds. 29 30

7.3.1.3 Mounting Method 31 As a minimum, the chassis shall be capable of mounting to an EIA-310-B rack using 4U 32 (or smaller standard increment) open-end mounting slots. If not rack-mounted, EIA-310-33 B does not apply and other chassis mounting methods are allowed, not to exceed overall 34




dimensions specified here. Mounting method shall withstand all mechanical shock and 1 vibration requirements of this standard. 2 3

7.3.1.4 Dimensions (All dimensions are given in inches) 4 5 Details of Maximum Basic Dimensions (not restricted to shape shown) 6

7 Figure 7-2: Maximum Basic Dimensions 8

9 Guidance: 10 11 These maximum dimensions were chosen for the following reasons: 12 13 1. NEMA TS-1 2070ATC users requested dimensions smaller than the 2070N to 14

compensate for equipment added to NEMA cabinets, such as video. 15 2. The size chosen is the only size meeting all of the following specifications: 16

• NEMA TS-2, Shelf Mount (NEMA TS-2, Paragraph 3.2.1) 17 • NEMA TS-2, Rack Mount (NEMA TS-2, Paragraph 3.2.1) 18 • 2070ATC, Rack Mount for Model 332 Cabinets (2070-2A Field I/O) 19 • 2070ATC, Rack Mount for ITS Cabinets (2070-2B Field I/O) 20 • 2070ATC, Shelf Mount for TS-2 Type 1 NEMA Cabinets (2070-2N Field I/O) 21

22 Quoting NEMA TS-2 Specification, Paragraph 3.2.1 Dimensions: 23 24 “The CU shall be capable of being shelf mounted. The CU shall also be capable of being 25 mounted in a 19-inch rack (EIA Standard RS-310-C, 1982). The height of the CU shall not 26




exceed 30.48 cm (12 in.). The depth of the unit, including connectors, harnesses, and 1 protrusions, shall not exceed 36.83 cm (14.5 in.). On rack-mounted units, the mounting 2 flanges of the control unit shall be so placed that no protrusion shall exceed 27.94 cm (11 3 in.) to the rear and 8.89 cm (3.5 in.) to the front.” 4 5 Minimum and Optional components located on front of assembly are as follows: 6 7

SP4 - 9-Pin D Socket Type 8 SP6 - 9-Pin D Plug Type 9 Infrared Communication Port 10 Front Panel Display 11 Keyboard 12 ON/OFF Power Switch 13 Power Supply Service Fuse Holder (with 3AG fuse) 14 LED for each DC power source and “ACTIVE” indications 15 USB series A 4 Pin Receptacle Communication Port 16 RJ-45 Connector ETHERNET Hub Port 3 (Network Diagnostics) 17 RJ-45 Connector ETHERNET Hub Port 5 (Controller Diagnostics) 18 Two Ethernet LEDs, labeled “100” and “ACTIVE” for Hub Port 3 19 Two Ethernet LEDs, labeled “100” and “ACTIVE” for Hub Port 5 20 Datakey KeyceptacleTM KC4210, KC4210PCB or equal 21

22 Minimum and Optional components located on rear of assembly (rack mount) or on the 23 front of assembly (shelf mount) are as follows: 24 25

Parallel I/O C1S - M104 Type 26 C11S – 37-Pin Circular Plastic Type 27 Serial I/O Port 1 – 15-Pin D Socket Type 28 C13S – 25-Pin D Socket Type 29 ATC Communications Module Slots, One or More 30 RJ-45 Connector ETHERNET Hub Port 2 (Network Connection) 31 Two Ethernet LEDs, labeled “100” and “ACTIVE” for Hub Port 2 32 NEMA MSA, MSB, MSC, and MSD connectors 33

34 Transmitter and Receiver activity is displayed on the “ACTIVITY” LED. The “100” LED is 35 illuminated when the hub port is linked at 100 Mbps and extinguished at all other times. 36


PARALLEL AND SERIAL I/O DETAILS


8 PARALLEL AND SERIAL I/O DETAILS 1 2

8.1 General Information 3 The ATC Input / Output (I/O) provides both serial and parallel connections to field 4 devices connected to the ATC, as well as the input of service power. 5 6

8.1.1 Parallel Input / Output Overview 7 8 The parallel I/O connects the ATC to transportation cabinets including, but not limited to, 9 the following: 10 11

• NEMA TS-1 12

• NEMA TS-2 Type 1 13


• Model 332 15

• NEMA/AASHTO/ITE/ ITS 16

17 Guidance: Access to devices residing on a high-speed computer bus shall be 18 interfaced via the ATC Ethernet hub port 6. The user is responsible for providing 19 an external rack, power supply, high-speed bus and Ethernet interface module 20 residing in this external rack, as well as all Ethernet software drivers. 21 22

8.1.2 Serial I/O Overview 23 24 The serial connections described here provides communications for implementation of 25 existing transportation standards, including but not limited to, the following: 26 27

• NEMA TS-1 28



• Model 170 31

• Joint NEMA/AASHTO/ITE/ATC 2070 32

33




8.2 Parallel Input / Output (PI/O) 1 2

8.2.1 Parallel Connection to Model 332 Cabinets 3 4 The parallel connection to a Model 332 Cabinet shall consist of the FCU , Parallel 5 Input/Output Ports, Connectors C1S, and C11S, C12S and other Circuit Functions 6 including muzzle jumper. 7 8

8.2.1.1 Field Controller Unit (FCU) 9 The FCU shall include a programmable microprocessor/controller unit together with all 10 required clocking and support circuitry. Operational software necessary to meet 11 housekeeping and functional requirements shall be provided. 12

8.2.1.2 Parallel I/O Ports 13 14 Input Ports 15 16 The I/O Ports shall provide 64 bits of input using ground-true logic. Each input shall be 17 read logic "1" when the input voltage at its field connector input is less than 3.5 VDC, 18 and shall be read logic "0" when either the input current is less than 100 µA or the input 19 voltage exceeds 8.5 VDC. Each input shall have an internal pull-up to the +12 VDC ISO 20 power supply and shall not deliver greater than 20 mA to a short circuit to ground. 21 22 Output Ports 23 The I/O Ports shall provide 64 bits of output. Each output written as a logic "1" shall 24 have a voltage at its field connector output of less than 4.0 VDC. Each output written as 25 logic "0" shall provide an open circuit (1 MΩ or more) at its field connector output. Each 26 output shall consist of an open-collector capable of driving 40 VDC minimum and sinking 27 100 mA minimum. Each output circuit shall be capable of switching from logic "1" to 28 logic "0" within 100 μs when connected to a load of 100 kΩ minimum. Each output 29 circuit shall be protected from transients of 10 ± 2 µs duration, ±300 VDC from a 1 kΩ 30 source, with a maximum rate of 1 pulse per second. 31

Parallel I/O Port Timing 32 33 Each output shall latch the data written and remain stable until either new data is written 34 or the active-low reset signal. Upon an active-low reset signal, each output shall latch a 35 logic "0" and retain that state until a new writing. The state of all output circuits at the 36 time of Power Up or in Power Down state shall be open. It shall be possible to 37 simultaneously assert all outputs within 100 µs. An output circuit state not changed 38 during a new writing shall not glitch when other output circuits are updated. 39 40




8.2.1.3 Other Parallel I/O Functions 1

8.2.1.3.1 Signals and Capacitive Load 2 A maximum capacitive load of 100 pF shall be presented to the LINESYNC input signal. 3 4

8.2.1.3.2 Legacy Signal Monitors 5 An External WDT “Muzzle” Jumper shall be provided internal to the ATC. With the 6 jumper IN and NRESET transitions HIGH (FCU active), the FCU shall output a state 7 change on O39 every 100 ms for 10 seconds or due to ENGINE BOARD Command. 8 When the jumper is missing, the feature shall not apply. 9 10 This feature is required to operate with legacy monitors, which requires activity on O39 11 immediately after power-up to determine that the ATC is functioning. Without the Muzzle 12 Jumper installed, the ATC boot-up time prevents the application software from 13 performing this task in time. If the controller is truly malfunctioning, the activity on O39 14 ceases within 10 seconds. 15 16 More modern Monitors have an adjustable power up time, allowing the controller to boot 17 and the application software to start toggling O39 before the monitor fails. 18 19

8.2.1.3.3 Watchdog Circuit 20 A WATCHDOG Circuit shall be provided. It shall be enabled by the software at Power 21 Up with a value of 100 ms. Its enabled state shall be machine readable and reported in 22 the status byte. Once enabled, the watchdog timer shall not be disabled without 23 resetting the PI/O. Failure of the PI/O to reset the watchdog timer within the prescribed 24 timeout shall result in a hardware reset. 25 26

8.2.1.3.4 One kHz Reference 27 A synchronizable 1 kHz time reference shall be provided. It shall maintain a frequency 28 accuracy of ± 0.01% (±0.1 counts per second). 29 30

8.2.1.3.5 Millisecond Counter 31 A 32-bit Millisecond Counter (MC) shall be provided for “time stamping.” Each 1 kHz 32 reference interrupt shall increment the MC. 33 34

8.2.1.3.6 Communications Loss 35 At Power Up, the FCU loss of communications timer shall indicate loss of 36 communications with the ATC until the user program sends the Request Module Status 37 message to reset the “E” Bit and a subsequent set output command is processed. 38 39




8.2.1.3.7 Control Signals 1 LINESYNC and POWER DOWN Lines shall be isolated and routed to FCU for 2 shut down functions. CPU RESET and POWER UPLine signals shall be isolated 3 and logically ORed to form NRESET. NRESET shall be used to reset FCU and 4 other module devices. 5 6

8.2.1.3.8 Isolation 7 Isolation shall be provided between internal +5 VDC / DCG#1 and +12 VDC ISO / 8 DCG#2. +12 VDC ISO shall be used for board power and external logic. 9 10

8.2.1.4 Buffers 11 A Transition Buffer shall be provided capable of holding a minimum of 1024 recorded 12 entries. The Transition Buffer shall default to empty. There shall be two entry types: 13 Transition and Rollover. The inputs shall be monitored for state transition. At each 14 transition ( If the input has been configured to report transition), a transition entry shall 15 be added to the Transition Buffer. The MC shall be monitored for rollover. At each 16 rollover transition ($xxxx FFFF - $xxxx 0000), a rollover entry shall be added to the 17 Transition Buffer. Transition Buffer blocks are sent to the Engine Board upon command. 18 Upon confirmation of their reception, the blocks shall be removed from the Transition 19 Buffer. The entry types are depicted as follows: 20 21 22 23

Input Transition Entry Description msb lsb Byte Number Transition Entry Identifier S Input Number 1 Timestamp NLSB x x x x x x x x 2 Timestamp LSB x x x x x x x x 3 24

Millisecond Counter Rollover Entry Description msb lsb Byte Number Rollover Entry Identifier 1 1 1 1 1 1 1 1 1 Timestamp MSB x x x x x x x x 2 Timestamp NMSB x x x x x x x x 3 25

8.2.1.5 I/O Functions 26

8.2.1.5.1 Inputs 27 Input Scanning 28 29 Input scanning shall begin at Input 0 and proceed in ascending order to the highest 30 input. Each complete input scan shall finish within 100 μs. Once sampled, the Logic 31




State of input shall be held until the next input scan. Each input shall be sampled 1,000 1 times per second. The time interval between samples shall be 1 ± 0.1 ms. If configured 2 to report, each input that has transitioned since its last sampling shall be identified by 3 input number, transition state, and timestamp (at the time the input scan began) and 4 shall be added as an entry to the Transition Buffer. If multiple inputs change state during 5 one input sample, these transitions shall be entered into the Input Transition Buffer by 6 increasing input number. The MC shall be sampled within 10 μs of the completion of the 7 input scan. 8 9 Data Filtering 10 If configured, the inputs shall be filtered by the FCU to remove signal bounce. The 11 filtered input signals shall then be monitored for changes as noted. The filtering 12 parameters for each input shall consist of Ignore Input Flag and the On and Off filter 13 samples. If the Ignore Input flag is set, no input transitions shall be recorded. The On 14 and Off filter samples shall determine the number of consecutive samples an input must 15 be on and off, respectively, before a change of state is recognized. If the change of 16 state is shorter than the specified value, the change of state shall be ignored. The On 17 and Off filter values shall be in the range of 0 to 255. A filter value of 0, for either or both 18 values, shall result in no filtering for this input. The default values for input signals after 19 reset shall be as follows: 20 21 Filtering Enabled 22 On and off filter values set to 5 23 Transition monitoring Disabled (Timestamps are not logged) 24 25

8.2.1.5.2 Outputs 26 Simultaneous assertion of all outputs shall occur within 100 µs. Each output shall be 27 capable of being individually configured in state to ON, OFF, or a state synchronized 28 with either phase of LINESYNC. The condition of the outputs shall only be "ON" if the 29 PI/O continues to receive active communications from the Engine Board. If there is no 30 valid communications with the Engine Board for 2.0 s, all outputs shall revert to the OFF 31 condition, and the PI/O status byte shall be updated to reflect the loss of communication 32 from the Engine Board. 33 34 Standard Function 35 Each output shall be controlled by the data and control bits in the Engine Board-PI/O 36 frame protocol as follows: 37 38

Output Bit Translation

Case Output

Data Bit

Output Control

Bit

Function

A 0 0 Output in the OFF state B 1 1 Output is a square wave, synchronized to the LINESYNC

signal. When LINESYNC is ON (1), the output is OFF, and when LINESYNC is OFF (0), the output is ON.




C 0 1 Output is a square wave, synchronized to the LINESYNC signal. When LINESYNC is ON (1), the output is ON, and when LINESYNC is OFF (0), the output is OFF

D 1 0 Output is in the ON state. 1 Output Stability 2 In Case A above, the corresponding output shall be turned OFF if previously ON and if 3 previously OFF remain OFF until otherwise configured. For half-cycle switching (cases 4 B and C), all outputs to be changed shall be changed within 50 µs after the 5 corresponding LINESYNC transition and shall remain in the same state during the entire 6 half cycle. In Case D above, the corresponding output shall be turned ON if previously 7 OFF and if previously ON remain ON until otherwise configured. All outputs shall not 8 change state unless commanded to do so. 9 10

8.2.1.6 Other Processor Functions 11

8.2.1.6.1 Interrupts 12 All interrupts shall be capable of asynchronous operation with respect to all processing 13 and all other interrupts. MILLISECOND Interrupt shall be activated by the 1 kHz 14 reference once per ms. A timestamp rollover flag set by MC rollover shall be cleared 15 only on command. LINESYNC Interrupt - This interrupt shall be generated by both the 16 0-to-1 and 1-to-0 transitions of the LINESYNC signal. The LINESYNC interrupt shall 17 monitor the MC interrupt and set the MC error flag if there has not been an interrupt from 18 the 1 kHz source for 0.5 s (≥60 consecutive LINESYNC interrupts). The LINESYNC 19 interrupt shall synchronize the 1 kHz time reference with the 0-to-1 transition of the 20 LINESYNC signal once a second. A LINESYNC error flag shall be set if the LINESYNC 21 interrupt has not successfully executed for 0.5 s or longer (≥500 consecutive millisecond 22 interrupts). 23

8.2.1.6.2 Communication Service Routine 24 A low-level communication service routine shall be provided to handle reception, 25 transmission, and communication faults. 26 27

8.2.1.6.3 Communication Processing 28 The task shall be to process the command messages received from the Engine Board, 29 prepare, and start response transmission. The response message transmission shall 30 begin within 4 ms of the receipt of the received message. Message type processing 31 time constraints shall not exceed 70 ms per message. 32 33

8.2.1.6.4 Input Processing 34 This task shall process the raw input data scanned in by the 1 ms interrupt routine, 35 perform all filtering, and maintain the transition queue entries. 36 37




8.2.1.7 Data Communications Protocols 1

8.2.1.7.1 Protocols 2 All communication with the Engine Board shall be via command-response protocol. The 3 Engine Board shall always initiate the communication and should the command frame 4 be incomplete or in error, no PI/O response shall be transmitted. The amount of bytes of 5 a command or response is dependent upon the I/O Module identification. The physical 6 interface is not controlled by this specification, and interchangeability among vendors 7 from PI/O to Engine Board is not intended. 8 9 Guidance: 10 11 For example, communications to PI/O module may be implemented via EIA-485 at 12 614 K bps, 5V TTL, or via a 1 GHz fiber channel provided all PI/O specifications 13 herein are met, including: 14

• Command and Response Message Content 15

• Command and Response Timing 16

• Error Checking 17

• Electrical Isolation 18

19 Therefore, a “frame” is merely a field in the data stream, not related to the 20 physical interface between the CPU and the PI/O, in contrast to the 2070 ATC 21 which requires serial communications via SP5 to its Field I/O. 22 23

8.2.1.7.1.1 Frame Types 24 The frame type shall be determined by the value of the first byte of the message. The 25 command frames type values $70 - $7F and associated response frame type values $F0 26 - $FF are allocated to the Contractor diagnostics. All other frame types not called out 27 are reserved. The command-response Frame Type values and message times shall be 28 as follows: 29 30 Guidance: 31 32 The following Commands and Responses are intended to match the 33 NEMA/AASHTO/ITE ATC 2070 commands and responses. 34 35




Frame Types

Module Command

I/0 Module Response Description

Minimum Message

Time

Maximum Message

Time 49 177 Request Module Status 250 μs 275 μs 50 178 MILLISECOND CTR. Mgmt. 222.5 μs 237.5 μs 51 179 Configure Inputs 344.5 μs 6.8750 ms 52 180 Poll Raw Input Data 317.5 μs 320 μs 53 181 Poll Filtered Input Data 317.5 μs 320 μs 54 182 Poll Input Transition Buffer 300 μs 10.25 ms 55 183 Command Outputs 405 μs 410 μs 56 184 Config. Input Tracking Functions 340 μs 10.25 ms 57 185 Config. Complex Output Functions 340 μs 6.875 ms 58 186 Configure Watchdog 222.5 μs 222.5 μs 59 187 Controller Identification 222.5 μs 222.5 μs 60 188 I/O Module Identification 222.5 μs 222.5 μs

61-62-65 63 64

189-190- 193 191 192

Reserved (note below) Poll variable length raw input Variable length command outputs

317.5 μs 405 μs

320 μs 410 μs

1

8.2.1.7.1.2 ITS Cabinet Frames 2 Messages 61 / 189, 62 / 190 and 65 / 193 are for ITS Cabinet Monitor Unit. See ITS 3 Cabinet Monitor System Serial Bus #1 for Command and Response Frames. Message 4 63 / Message 191 shall be the same as Message 52 / 180 except Byte 2 of Message 5 180 response shall denote the following number of input bytes. Message 64 / 192 shall 6 be the same as Message 55 / 183 except Byte 2 of the Message 55 Command shall 7 denote the number of output data bytes plus the following output data. 8 9

8.2.1.7.2 Request Module Status 10 The Command shall be used to request PI/O status information response. 11 Command/response frames are as follows: 12 13

Request Module Status Command Description msb lsb Byte Number (Type Number = 49) 0 0 1 1 0 0 0 1 1 Reset Status Bits P E K R T M L W 2

14 Request Module Status Response




Description msb lsb Byte Number (Type Number = 177) 1 0 1 1 0 0 0 1 1 System Status P E K R T M L W 2 SCC Receive Error Count Receive Error Count 3 SCC Transmit Error Count Transmit Error Count 4 Timestamp MSB Timestamp MSB 5 Timestamp NMSB Timestamp NMSB 6 Timestamp NLSB Timestamp NLSB 7 Timestamp LSB Timestamp LSB 8 1

8.2.1.7.2.1 Request Module Status Response 2 The response status bits are defined as follows: 3 4 P -Indicates PI/O hardware reset 5 E -Indicates a communications loss of greater than 2 seconds 6 M -Indicates an error with the MC interrupt 7 L -Indicates an error in the LINESYNC 8 W -Indicates that the PI/O has been reset by the Watchdog 9 R -Indicates that the receive error count byte has rolled over 10 T -Indicates that the transmit error count byte has rolled over 11 K -Indicates the Datakey has failed or is not present 12 13

8.2.1.7.2.2 Bit Information 14 Each of these bits shall be individually reset by a '1' in the corresponding bit of any 15 subsequent Request Module Status frame, and the response frame shall report the 16 current status bits. The serial communications controller error count bytes shall not be 17 reset. When a count rolls over (255 - 0), its corresponding roll-over flag shall be set. 18 19

8.2.1.7.3 MC Management Frame 20 MC management frame shall be used to set the value of the MC. The 'S' bit shall return 21 status '0' on completion or '1' on error. The 32-bit value shall be loaded into the MC at 22 the next 0-1 transition of the LINESYNC signal. The frames are as follows: 23 24

Millisecond Counter Management Command Description msb lsb Byte Number (Type Number = 50) 0 0 1 1 0 0 1 0 1 New Timestamp MSB X x x x x x x x 2 New Timestamp NMSB X x x x x x x x 3 New Timestamp NLSB X x x x x x x x 4 New Timestamp LSB X x x x x x x x 5 25 26




Millisecond Counter Management Response Description msb lsb Byte Number (Type Number = 178) 1 0 1 1 0 0 1 0 1 Status 0 0 0 0 0 0 0 S 2 1

8.2.1.7.4 Configure Inputs 2 The Configure Inputs command frame shall be used to change input configurations. The 3 command-response frames are as follows: 4

5 Configure Inputs Command

Description msb lsb Byte Number (Type Number = 51) 0 0 1 1 0 0 1 1 1 Number of Items (n) n n n n n n n n 2 Item # - Byte 1 E Input Number 3(I-1)+3 Item # - Byte 2 Leading edge filter (e) 3(I-1)+4 Item # - Byte 3 Trailing edge filter (r) 3(I-1)+5 6

Configure Inputs Response Description msb lsb Byte Number (Type Number = 179) 1 0 1 1 0 0 1 1 1 Status 0 0 0 0 0 0 0 S 2 7 Block field definitions shall be as follows: 8 9 E - Ignore Input Flag. 10

"1" = do not report transitions for this input, 11 "0" = report transitions for this input 12 e - A one-byte leading edge filter specifying the number of consecutive input 13 samples which must be "0" before the input is considered to have entered to "0" 14 state from "1" state (range 1 to 255, 0 = filtering disabled) 15 16 r - A one-byte trailing edge filter specifying the number of consecutive input 17 samples which must be "1" before the input is considered to have entered to "1" 18 state from "0" state (range 1 to 255, 0 = filtering disabled) 19 20 S - return status S = '0' on completion or '1' on error 21

8.2.1.7.5 Poll Raw Input Data 22 The Poll Raw Input Data frame shall be used to poll the PI/O for the current unfiltered 23 status of all inputs. The response frame shall contain 8 or 15 bytes of information 24 indicating the current input status. The frames are as follows: 25 26 27

28




Poll Raw Input Data Command Description msb lsb Byte Number (Type Number = 52) 0 0 1 1 0 1 0 0 1

1 Poll Raw Input Data Response

Description msb lsb Byte Number (Type Number = 1809) 1 0 1 1 0 1 0 0 1 Inputs I0 (lsb) to I7 (msb) x x x x x x x x 2 Inputs I8 to I119 x x x x x x x x 3 to 16 Timestamp MSB x x x x x x x x 17 Timestamp NMSB x x x x x x x x 18 Timestamp NLSB x x x x x x x x 19 Timestamp LSB x x x x x x x x 20 2

8.2.1.7.6 Poll Input Filtered Data 3 The Poll Filtered Input Data frame shall be used to poll the PI/O for the current filtered 4 status of all inputs. The response frame shall contain 8 bytes(-2A) or 15 bytes (2B) of 5 information indicating the current filtered status of the inputs. Raw input data shall be 6 provided in the response for inputs that are not configured for filtering. The frames are 7 as follows: 8 9

Poll Filter Input Data Command Description msb lsb Byte Number (Type Number = 53) 0 0 1 1 0 1 0 1 1

10 Poll Filter Input Data Response

Description msb lsb Byte Number (Type Number = 181) 1 0 1 1 0 1 0 1 1 Inputs I0 (lsb) to I7 (msb) x x x x x x x x 2 Inputs I8 to I119 x x x x x x x x 3 to 16 Timestamp MSB x x x x x x x x 17 Timestamp NMSB x x x x x x x x 18 Timestamp NLSB x x x x x x x x 19 Timestamp LSB x x x x x x x x 20 11

8.2.1.7.7 Poll Input Transition Buffer 12 The Poll Input Transition Buffer frame shall poll the PI/O for the contents of the input 13 transition buffer. The response frame shall include a three-byte information field for 14 each of the input changes that have occurred since the last interrogation. The frames 15 are as follows: 16 17 18




Poll Input Transition Buffer Command Description msb lsb Byte Number (Type Number = 54) 0 0 1 1 0 1 1 0 1 Block Number x x x X x X x x 2 1 2

Input Transition Buffer Response Description msb lsb Byte Number (Type Number = 182) 1 0 1 1 0 1 1 0 1 Block Number x x x X x X x x 2 Number of Entries (N) x x x X x X x x 3 Item I S Input Number 3(I-1)+4 Item I Timestamp NLSB x x x X x X x x 3(I-1)+5 Item I Timestamp LSB x x x X x X x x 3(I-1)+6 Status 0 0 0 0 C F E G 3(N-1)+7 Timestamp MSB x x x X x X x X 3(N-1)+8 Timestamp NMSB x x x X x X x X 3(N-1)+9 Timestamp NLSB x x x X x X x X 3(N-1)+10 Timestamp LSB x x x X x X x X 3(N-1)+11

3

8.2.1.7.7.1 State Transitions 4 Each detected state transition for each active input (see configuration data) is placed in 5 the queue as it occurs. Bit definitions are as follows: 6 7

S - Indicates the state of the input after the transition 8 C - Indicates the 255 entry buffer limit has been exceeded 9 F - Indicates the buffer has overflowed 10 G - Indicates the requested block number is out of monotonic increment 11

sequence 12 E - Same block number requested, E is set in response 13

8.2.1.7.7.2 Block Number 14 The Block Number byte is a monotonically increasing number incremented after each 15 command issued by the Engine Board. When the PI/O Module receives this command, 16 it shall compare the associated Block Number with the Block Number of the previously 17 received command. If it is the same, the previous buffer shall be re-sent to the Engine 18 Board and the 'E' flag set in the status response frame. If it is not equal to the previous 19 Block Number, the old buffer shall be purged and the next block of data sent. If the 20 block number is not incremented by one, the status G bit shall be set. The block number 21 received becomes the current number (even if out of sequence). The Block Number 22 byte sent in the response block shall be the same as that received in the command 23 block. Counter rollover shall be considered as a normal increment. 24 25




8.2.1.8 Set Outputs 1 The Set Outputs frame shall be used to command the PI/O to set the Outputs according 2 to the data in the frame. If there is any error configuring the outputs, the 'E' flag in the 3 response frame shall be set to '1'. If the LINESYNC reference has been lost, the 'L' bit in 4 the response frame shall be set. Loss of LINESYNC reference shall also be indicated in 5 system status information. The output bytes depend upon field I/O module. These 6 command and response frames are as follows: 7

8 Set Outputs Command

Description msblsb Byte Number (Type Number = 55) 0 0 1 1 0 1 1 1 1 O0 (lsb) to O7 (msb) Data X x x X x x x x 2 O8 to O103 Data X x x X x x x x 3 to 14 O0 (lsb) to O7 (msb) Control X x x X x x x x 15 O8 to O103 Control X x x X x x x x 16 to 27 9

Set Outputs Response Description msb lsb Byte Number (Type Number = 183) 1 0 1 1 0 1 1 1 1 Status 0 0 0 0 0 0 L E 2 10

8.2.1.9 Configure Input Tracking Functions 11 The Configure Input Tracking Functions frame shall be used to configure outputs to 12 respond to transitions on a specified input. Each Output Number identified by Item 13 Number shall respond as configured to the corresponding Input Number identified by the 14 same Item Number. Input to Output mapping shall be one to one. If a command results 15 in more than 8 input tracking outputs being configured, the response V bit shall be set to 16 ‘1’ and the command shall not be implemented. The command and response frames 17 are as follows: 18 19

Configure Input Tracking Functions Command Description msb lsb Byte Number (Type Number = 56) 0 0 1 1 1 0 0 0 1 Number of Items (N) Number of Items 2 Item I - Byte 1 E Output Number 2(I-1)+3 Item I - Byte 2 I Input Number 2(I-1)+4 20

Configure Input Tracking Functions Response Description msb lsb Byte Number (Type Number = 184) 1 0 1 1 1 0 0 0 1 Status 0 0 0 0 0 0 0 V 2 Timestamp MSB x x x X x x x x 3 Timestamp NMSB x x x X x x x x 4 Timestamp NLSB x x x X x x x x 5




Timestamp LSB x x x X x x x x 6 1

8.2.1.9.1 Configure Input Tracking Functions Response 2 Definitions are as follows: 3 E '1’ - Enable input tracking functions for this output 4 '0' - Disable input tracking functions for this output 5 I '1' - The output is OFF when input is ON, ON when input OFF 6 '0' - The output is ON when input is ON, OFF when input is OFF 7 V '1' - The max. number of 8 configurable outputs exceeded 8 '0' - No error 9 Number of Items - The number of entries in the frame. If zero, all outputs currently 10 configured for input tracking shall be disabled. 11 12

8.2.1.9.2 Timestamp 13 The timestamp value shall be sampled prior to the response frame. 14 15

8.2.1.9.3 Output Updates 16 Outputs which track inputs shall be updated no less than once per ms. Input to output 17 signal propagation delay shall not exceed 2 ms. 18 19

8.2.1.9.4 Number of Item Field 20 The “Number of Item” field is valid from 0 to 16 (most that is sent at one time is 8 21 enables and 8 disables). If processing a command resulting in more than 8 Input 22 Tracking functions being enabled, none of the command shall be implemented and 23 response message “V” bit set to 1. If an invalid output or input number is specified for a 24 function, the FCU software shall not do that function definition. It shall also not be 25 counted toward the maximum of 8 input tracking function allowed. The rest of the 26 message shall be processed. When an Input Tracking function is disabled, the output is 27 set according to the most recently received Set Outputs Command. When an input 28 tracking function for an output is superseded (redefined as either another input tracking 29 function, or as a complex output function) nothing shall be done with the output. The 30 most recent value remains until the new function changes it. 31 32

8.2.1.10 Configure Complex Output Functions 33 The Configure Complex Output Functions frame shall be used to specify a complex 34 output for one to eight of any of the outputs. If a Configure Complex Output Function 35 command results in more than eight outputs being configured, the 'V' bit in the response 36 message shall be set to a '1', and the command shall not be implemented. Two output 37 forms shall be provided, single pulse and continuous oscillation. These output forms 38 shall be configurable to begin immediately or on a specified input trigger and, in the case 39 of continuous oscillation, to continue until otherwise configured or to oscillate only while 40




gated active by a specified input. If the command gate bit is active, the command trigger 1 bit shall be ignored and the specified input shall be used as a gate signal. The 2 command and response frames are as follows: 3 4

Configure Complex Output Functions Command Description msb lsb Byte Number (Type Number = 57) 0 0 1 1 1 0 0 1 1 Number of Items Number of Items 2 Item i - Byte 1 0 Output Number 7(i-1)+3 Item i - Byte 2 Primary Duration (MSB) 7(i-1)+4 Item i - Byte 3 Primary Duration (LSB) 7(i-1)+5 Item i - Byte 4 Secondary Duration (MSB) 7(i-1)+6 Item i - Byte 5 Secondary Duration (LSB) 7(i-1)+7 Item i - Byte 6 0 Input Number 7(i-1)+8 Item i - Byte 7 P W G E J F R L 7(i-1)+9

5 Configure Complex Output Functions Response

Description msb lsb Byte Number (Type Number = 185) 1 0 1 1 1 0 0 1 1 Status 0 0 0 0 0 0 0 V 2 Timestamp (MSB) x x x x x x x x 3 Timestamp (NMSB) x x x x x x x x 4 Timestamp (NLSB) x X x x x x x x 5 Timestamp (LSB) x X x x x x x x 6 6

8.2.1.10.1 Configure Complex Outputs Bit Fields 7 The bit fields of the command frame are defined as follows: 8 9

E '1' enable complex output function for this output 10 '0' disable complex output function for this output 11 J '1' During the primary duration, the output shall be written as a logic '1'. 12 During the secondary duration, the output shall be written as a logic '0'. 13 '0' During the primary duration, the output shall be written as a logic '0'. 14

During the secondary duration, the output shall be written as a logic '1' 15 16 Output Number - 7-bit output number identifying outputs 17 18 Primary Duration - For single pulse operation, this shall determine the number of 'ticks' 19 preceding the pulse. For continuous oscillation, this shall determine the length of the 20 inactive (first) portion of the cycle. 21 22 Secondary Duration - For single pulse operation, this shall determine the number of 23 'ticks' the pulse is active. Subsequent to the secondary duration, the output shall return 24 to the state set according to the most recently received Set Outputs command. For 25




continuous oscillation, this shall determine the length of the active (second) portion of 1 the cycle. 0 = hold output state until otherwise configured. 2 3 F '1' - The trigger or gate shall be acquired subsequent to filtering the specified 4

input. The raw input signal shall be used if filtering is not enabled for the 5 specified input. 6

'0' - The trigger or gate shall be derived from the raw input. 7 8 R '1' - For triggered output, the output shall be triggered by an ON-to-OFF 9

transition of the specified input and shall be triggered immediately upon 10 command receipt if the input is OFF. For gated output, the output shall 11 be active while the input is OFF. 12

'0' - For triggered output, the output shall be triggered by an OFF-to-ON 13 transition of the specified input and shall be triggered immediately upon 14 command receipt if the input is ON. For gated output, the output shall be 15 active while the input is ON. 16

17 Input Number - 7-bit input number identifying inputs 0 Up. 18 19 P '1' - The output is configured for single-pulse operation. Once complete, the 20

complex output function shall be disabled. 21 '0' - The output is configured for continuous oscillation. 22 23 W '1' - It is triggered by the specified input. Triggered complex output shall 24

commence within 2 ms of the associated trigger. 25 '0' - Operation shall begin within 2 ms of the command receipt. 26 27 G '1' - Operation shall be gated active by the specified input. 28 '0' - Gating is inactive. 29 30 L '1' - The LINESYNC based clock shall be used for the time ticks. 31 '0' - The MC shall be used for the time ticks. 32 33 V '1' - Indicates maximum number of configurable outputs is exceeded. 34 '0' - No error 35 36 Number of items - The number of entries in the frame. If 0, all outputs currently 37 configured as complex outputs shall be disabled. 38 39

8.2.1.10.2 Sampling Rate 40 Controlling input signals shall be sampled at least once per ms. 41 42

8.2.1.10.3 Data Range 43 The “Number of Items” field is valid from 0 to 16. Zero means disable all Complex 44 Output functions. Sixteen is the maximum because the most that is sent at one time is 8 45




enables and 8 disables. If processing a command results in more than 8 Complex 1 Output functions being enabled, none of the command shall be implemented and the 2 response message “V” bit shall be set to 1. If an invalid output or input number (the “G” 3 or “W” bits being set to 1) is specified for a function, that function definition is not done 4 by the FCU software. It shall also not be counted towards the maximum of 8 Complex 5 Output functions allowed. The rest of the message shall be processed. When a 6 Complex Output function is disabled, the output is set according to the most recently 7 received Set Outputs command. When a complex output function for an output is 8 superseded, that is, redefined as whether another Complex Output function, or as an 9 Input Tracking function, nothing special is done with the output. The most recent value 10 remains until the new function changes it. The “G” bit (gating) set to 1 takes precedence 11 over the “W” bit (triggering). If gating is ON, triggering is turned OFF, regardless of the 12 value of the “W” bit in the command message. If a Complex Output is configured with 13 the “G” bit set to 1 (gating) and the “P” bit set to 0 (continuous oscillation), the output is 14 set to OFF (0) whenever the specified input changes state so that the oscillation should 15 cease (output inactive). For a single pulse operation (“G” bit set to 1), after the 16 secondary duration completes the Complex Output function shall be disabled, and the 17 output shall be set according to the most recently received Set Outputs command. 18 19

8.2.1.11 Configure Watchdog 20 The Configure Watchdog frames shall be used to change the software watchdog timeout 21 value. The Command and response frames are as follows: 22 23

Configure Watchdog Command Description msb lsb Byte Number (Type Number = 58) 0 0 1 1 1 0 1 0 1 Timeout Value x x x x x x x x 2 24 25

Configure Watchdog Response Description msb lsb Byte Number (Type Number = 186) 1 0 1 1 1 0 1 0 1 Status 0 0 0 0 0 0 0 Y 2 26

8.2.1.11.1 Timeout Value 27 The timeout value shall be in the range between 10 to 100 ms. If the value is lower than 28 10, 10 shall be assumed. If the value is greater than 100, 100 shall be assumed. 29 30

8.2.1.11.2 Time Out Change 31 On receipt of this frame, the watchdog timeout value shall be changed to the value in the 32 message and the “Y” bit set. The response frame bit (Y) shall indicate a '1' if the 33 watchdog has been previously set and a '0' if not. 34 35




8.2.1.12 Controller Identification 1 Frame Type 59 is reserved. Type 59 and Response 187 are not supported. 2 3 Guidance: 4 5 This is a legacy 2070 ATC message command / response for Field I/O modules 6 with Datakey resident. Upon command, a response frame containing the 128 7 bytes of the Datakey. On NRESET transition to High or immediately prior to any 8 interrogation of the Datakey, the PI/O shall test the presence of the Key. If absent, 9 the PI/O Status Bit “K” shall be set and no interrogation shall take place. If a error 10 occurs during the interrogation, Bit “K” shall be set. If “K” bit set, only the first 11 two bytes shall be returned. The Command Response frames are as follows: 12 13

Controller Identification Command Description msb lsb Byte Number (Type Number = 59) 0 0 1 1 1 0 1 1 1

14 Controller Identification Response

Description msb lsb Byte Number (Type Number = 187) 1 0 1 1 1 0 1 1 1 Status 0 0 0 0 0 0 0 K 2 Datakey Data x x x x x x x x 3 to 130

15

8.2.1.13 Module Identification 16 The PI/O Identification command frame shall be used to request the PI/O Identification 17 value Response of "1" for the Model 332 PI/O, "2" for the NEMA TS-2 Type 2 PI/O, 3 for 18 the NEMA TS-2 Type 1 PI/O. The Identification value response for ITS Cabinet SIUs 19 and CMU shall be frame address. The command and response frames are shown as 20 follows: 21 22

I/O Module Identification Command Description msb lsb Byte Number (Type Number = 60) 0 0 1 1 1 1 0 0 1 23 24

I/O Module Identification Response Description msb lsb Byte Number (Type Number = 188) 1 0 1 1 1 1 0 0 1 PI/O I D byte x x x x x x x x 2 25

8.2.1.14 Mechanical Details 26




C11S

NOTES: 1. C1S Dark Circles denote guide pin locations 2. C1S Open Circles denote guide socket locations 3. Dimension “A” shall be 0.5” minimum 4. C1S shall be M104 type 5. C11S shall be 37 pin circular plastic type 6. C1S & C11S pin assigned per 2070 ATC Standard

1 Figure 8-1: C1S and C11S Pin Configuration: Refer to ATC 2070 Standard 2

3

8.2.2 Parallel Connection to NEMA TS-1 or TS-2 Type 2 Cabinets 4

8.2.2.1 Description 5 6 This PI/O shall consist of an FCU Controller, Parallel Input / Output Ports, Field 7 Connectors and Communications Circuits. It is similar in function to the Model 332 PI/O, 8 except it provides more inputs and outputs via different physical connectors. 9 10

8.2.2.2 Front Panel 11 The Front Panel shall be furnished with the following: 12 13 Incoming VAC fuse protection 14 Four NEMA Connectors, A, B, C & D 15 16

8.2.2.3 Functional Requirements Exceptions 17 This PI/O shall meet all requirements identified above except that: 18 118 bits of input and 102 bits of output shall be provided. 19 Specification for inputs applies, except the voltage is +24 V in lieu of +12 V, and logical 20 “0”, exceeds 16.0 VDC. 21 22




8.2.2.4 Fault Monitor and Voltage Monitor 1 NEMA TS-2 Controller FAULT and VOLTAGE Monitor functions (outputs to the cabinet 2 monitor) shall be provided. 3 4

8.2.2.4.1 Monitor Logic 5 Two 3-input OR gates shall be provided. The gate 1 output shall be connected to 6 Connector A, Pin A (Fault Monitor) and gate 2 output shall be connected to Connector 7 A, Pin C (Voltage Monitor). Any FALSE state input shall cause a gate output FALSE 8 (+24 V) state. 9 10

8.2.2.4.2 Watchdog 11 O78 shall normally change its state every 100 ms. A Watchdog Timer (WDT) circuit 12 shall monitor the output. No state change for 2 ± 0.1 s shall cause the circuit output to 13 generate a FALSE (+24 VDC) output (input to gates 1 and 2). Should the FCU begin 14 changing state, the WDT output shall return to TRUE (0 VDC) state. 15 16

8.2.2.4.3 The 5 VDC Monitor 17 The +5 VDC shall be monitored. When 5 VDC supply falls out of regulation (± 0.25 V), 18 this monitor circuit shall generate a FALSE output (input to gates 1 and 2) Normal 19 operation shall return the output state to TRUE state. 20 21

8.2.2.4.4 Fault Monitor Logic 22 The FCU microprocessor output shall be assigned to FAULT Monitor (input to gate 1) 23 and another output shall be assigned to VOLTAGE MONITOR (input to gate 2). 24 25

8.2.2.4.5 Monitor Control from Application Software 26 CPU Port 5 SET OUTPUT COMMAND Message 27 OUTPUTs O78 and O79 shall be assigned to FAULT (O78) and VOLTAGE (O79). 28 The bit logic “1” shall be FCU output FALSE. 29 30

8.2.2.4.6 Monitor Output Power Up Conditions 31 CPU / FCU operation at POWER UP shall be as follows: 32 33 FCU Comm Loss Flag set. FAULT & VOLTAGE MONITOR outputs set FALSE. 34 CPU REQUEST MODULE STATUS COMMAND Message with “E” bit set is sent to FCU 35 to clear Comm Loss Flag and responds to CPU with “E” bit reset. 36 37 Before the Comm Loss timer expires, the SET OUTPUTS COMMAND data must be 38 sent. In that data, the O78 and O79 logically set to “0” will cause the FCU 39 microprocessor port pins assigned for FM and VM outputs to go to their TRUE state. At 40




NOTES: 1. A = NEMA “A” Connector, Type MS-3112-22-55P 2. B = NEMA “B” Connector, Type MS-3112-22-55S 3. C = NEMA “C” Connector, Type MS-3112-24-61S 4. D = NEMA “D” Connector, Type MS-3112-24-61P 5. Spacing Between A, B, C, D Connectors = 3.0 “ min, Center to Center.

this point, the signal outputs defined in the message will be permitted at the output 1 connectors. Any number of other messages may be sent between the MODULE 2 STATUS COMMAND and SET OUTPUTS COMMAND. 3 4 If the above message sequence is not followed, Comm Loss Flag shall be set (or 5 remain) and VM & FM shall retain the FALSE output state. 6 7

8.2.2.4.7 Communications Loss 8 A CPU/FCU Communications Loss during normal operation shall cause all outputs to go 9 blank (FALSE state) and shall set the Comm Loss Flag. FM and VM outputs shall be in 10 the FALSE state. 11

8.2.2.5 Mechanical Details 12 13

14 Figure 8-2: Connector Diagram 15

16 Connector A, B, C Pin Configurations: Refer to NEMA TS-2 Specification 17 18 Connector D Pin Configuration: Refer to ATC 2070 Standard 19 20

8.2.3 Connection to NEMA TS-2 Type 1 Cabinets 21 22 Description 23




The TS-2 Type 1 PI/O provides a TS2-1 compatible interface, AC Power to the ATC, 1 Fault Monitor Logic Output and Output Frame Byte 9 Bit 6 to the NEMA TS2 Cabinet 2 Monitor Unit (CMU). 3 4

Front Panel 5 The Front Panel shall be furnished with the following: 6

• Incoming VAC fuse protection 7 • One NEMA Connector, A 8 • One NEMA Port 1 Connector 9

10 Functional Requirements Exceptions 11 This PI/O shall meet all requirements of 7.2.2, except: 12

• No C1 and C11 Connectors 13 • No 64 inputs / 64 outputs requirements 14

15 Parallel Connector 16 The parallel connector is a 10 Pin NEMA Connector A 17 18 Service Power Connection 19 Incoming AC Power is derived from Connector A, Pin C (AC+), Pin A (AC-), and Pin H 20 (Equipment Ground). 21 22 Fault Monitor 23 An FCU output shall drive a open collector transistor whose output shall be routed to 24 Connector A Pin F for use as a FAULT MONITOR Output. The transistor shall be 25 capable of sinking 200 mA at 30 VDC. 26 27 Connector A Pin Assignment 28 Connectors A pin assignment: Refer to NEMA TS-2 Specification 29 30

8.3 Serial Input / Output 31 32 Guidance: The traditional (ATC 2070) use of the serial ports is as follows: 33

SP1: External communications (NEMA Port 2) 34 SP2: External communications (NEMA Port 3) 35 SP3: ITS Cabinet SB2, , or external communication (NEMA Port 1) 36 SP4: OS console 37 SP5: Field I/O communications module 38 SP6: User Interface 39 SP7: Field I/O communications via C13S connector 40 SPI: Portable Memory Device (Data Key) 41 ENET1 Ethernet for Network 42

43




Guidance: The planned use of the added (not on ATC 2070) serial ports is as 1 follows: 2

USB Removable Memory Device 3 ENET2 Ethernet for Local Cabinet (Expansion Rack, Upload to Laptop) 4 5

Refer to Engine Board section for a description of each serial port operation. 6 7 The ATC shall provide two internal 100BASE-TX hubs per the IEEE 802.3 specification 8 for 100 Mbps Ethernet signaling with CSMA/CD over two pairs of Category 5 UTP or 9 STP wire. Ports shall be allocated as follows: 10

Port 1: Internal 10/100 BPS Port to Engine Board ENET1 11 Port 2: External 10/100 BPS Port (Typically to Network Backbone) 12 Port 3: External 10/100 BPS Port (Typically for Network Diagnostics) 13 Port 4: Internal 10/100 BPS Port to Engine Board ENET2 14 Port 5: External 10/100 BPS Spare Port (Typically for Controller Expansion) 15 Port 6: External 10/100 BPS Port (Typically for Controller Diagnostics) 16 17

18 Pictorially: 19 20 21 22 23 24 25 26 27 28 29 30

31 32 33

34 35 36 37 38

Figure 8-3: Details of Ethernet Hub Connections, Typical Use 39 40

41 Typical Hub Port Use: 42 43 44 45 46

10/100 BPS RJ-45 Network Connection

10/100 BPS RJ-45 Network Diagnostics

10/100 BPS RJ-45 Internal Expansion

10/100 BPS RJ-45 Controller Diagnostic

10/100 BPS Hub 1

10/100 BPS Hub 2

2

3

5

6

1

4

Advanced Transportation Controller

10 MBPS ENET1 ENGINE BOARD

10 MBPS ENET2




Hub 1: 1 2 Hub1, Port 1 connects to Engine Board ENET1, which handles the network traffic. 3 Although ENET1 is not expected to handle 100 Mbps data streams, the ATC may find 4 itself connected to a 100 Mbps network. Hub1 handles the speed conversion, as well as 5 provides two RJ-45 Ethernet connectors, Port 2 and Port 3. 6 7 Port 2 provides a permanent connection to the network backbone for network 8 communications, such as NTCIP. Port 2 does not act as a router or communications 9 switch. Because the Engine Board cannot respond to every Ethernet packet on the 10 trunk, the network topology should be designed to forward only packets destined for the 11 ATC. 12 13 Port 3 is configured as an uplink for use with a “straight through” Ethernet cable. This 14 eliminates the need to disconnect the ATC from the network to connect a laptop 15 computer for network diagnostics, or to connect other cabinet equipment to the network. 16 17 Hub 2: 18 19 Port 4 connects to Engine Board ENET2, which communicates to local cabinet devices. 20 Although ENET2 is not expected to handle 100 Mbps data streams, the ATC may find 21 itself connected to a 100 Mbps network. Hub2 handles the speed conversion, as well as 22 provides two RJ-45 Ethernet connectors, Port 5 and Port 6. 23 24 Port 5 provides a permanent connection for internal ATC expansion, such as connection 25 to a network interface card residing in a computer rack (VME, for example). This 26 provides a standard method to connect parallel devices such as analog to digital 27 converters, disk storage and multiple computer boards, without specifying a particular 28 computer bus. 29 30 Port 6 is configured as an uplink for use with a “straight through” Ethernet cable. This 31 eliminates the need to disconnect the ATC from the network to connect a laptop 32 computer for controller diagnostics, or to load new controller software. 33 34

8.4 Isolation Requirements 35

36 The ATC shall maintain optical or magnetic isolation of signals from the ATC to Field 37 Devices as described in the following paragraphs. 38 39 The need for isolating field connections is twofold: 40 41 • Isolation prevents electrical surge damage to the Engine Board due to lightning or 42

nearby electrical equipment picked up by the field wires. Although the I/O circuitry 43 may be damaged, isolation protects the Engine Board, allowing malfunction to be 44 logged and reported. 45




• Isolation prevents “ground loops”; insuring equipment is grounded at one place, only. 1 For example, desktop computers internally connect logic common to equipment 2 ground. Attaching an un-isolated ATC serial port to a desktop PC will ground the 3 ATC through the Engine Board or Field I/O, creating ground loop current through the 4 serial cable, resulting in data transmission errors. 5

6 Field Device Definition and Exceptions: 7 8 • Isolation is not required when the serial port is connected to another ATC assembly. 9

For example, the Front Panel is considered to be part of the ATC, meaning the SP6 10 connection to the Front Panel Device need not be electrically isolated. In this case, 11 the Front Panel shall be powered by the ATC, battery or an isolated power source. 12

• Isolation is not required when the serial port is temporarily connected to a device with 13 an isolated power source. For example, a laptop or PDA temporarily connected to 14 the SP4 Console to download software need not be electrically isolated. 15

16 Isolation Methods: 17 18 Electrical isolation shall be implemented via optical or magnetic methods. Capacitive 19 isolation is not allowed, as capacitors act as high-pass filters, passing high-frequency 20 common mode surges to the Engine Board. Optical isolators and magnetic transformers 21 effectively block common mode surges at all frequencies. 22 23

8.4.1 Engine Board Isolation 24 25 The Engine Board shall be electrically isolated from all serial and parallel field 26 connections. Engine Board signals need not be electrically isolated from one another. 27 The Engine Board, as well as +5 VDC, +12 VDC and -12 VDC are referenced to the 28 minus of the controller power supply (DCGND1). 29 30

8.4.2 Parallel I/O Isolation 31 32 Every parallel input and output shall be electrically isolated from the Engine Board, and 33 from each serial I/O signal. Parallel inputs and outputs need not be electrically isolated 34 from one another. All parallel inputs and outputs, as well as +12 VDC ISO are 35 referenced to DCGND2. External cabinet power supply (if used) shall be referenced to 36 DCGND2. 37 38 39 40

8.4.3 Serial I/O Isolation 41 42




Serial inputs and outputs connected to field devices shall be electrically isolated from the 1 Engine Board and from all parallel inputs and outputs. Signals within a serial port 2 connector need not be electrically isolated from one another. Signals of different serial 3 port connectors shall be electrically isolated from one another. Each serial port shall be 4 referenced to the attached equipment. Pictorially, dashed lines depict the isolation 5 boundaries. SP1, 2, 3, 7 are isolated on the communications interface boards. Ethernet 6 ports are not shown, as they are magnetically isolated on the Engine Board: 7 8 9

10 . 11

Figure 8-4:Isolation Boundaries12

F. PANEL

SP4 SP6

SP5 PARALLEL

I / O

ENGINE

BOARD

SP7

SP2

SP3

SP1

+ -

G

CABINET DEVICES

+12VDC -12 VDC

+5VDC DCGND1

POWER SUPPLY

+12VISO DCGND2

+24VDC

SERVICE POWER


ENVIRONMENTAL AND TEST PROCEDURES


9 ENVIRONMENTAL AND TEST PROCEDURES 1 2 NOTICE: This Electrical, Environmental, and Testing Requirements section was 3 developed using information excerpted from NEMA TS2-2003 Traffic Controller 4 Assemblies with NTCIP Requirements. Permissions and approvals for the reuse of the 5 excerpted material are pending approval by NEMA. 6

9.1 General 7 This section establishes the limits of the environmental and operational conditions in 8 which the First Article Controller Assembly will perform. This section defines the 9 minimum test procedures which may be used to demonstrate conformance of a device 10 type with the provisions of the standard. 11 12 Software shall be provided that contains a set of test programs to facilitate testing. This 13 software shall be capable of running individual tests or combinational tests. The 14 combinational tests shall include a single menu function that binds all of the tests into a 15 single module. Tests may be run either from the Front Panel or by an external Serial 16 Port. These tests shall include but are not limited to the items in the following outline: 17 18

• A testing program shall contain the following: 19 1. Introduction to the Test 20 2. Installation Instructions 21 3. Starting the Software 22 4. Running Individual Tests 23 5. Test Suite Tree for combination tests 24

25 • Individual Processor tests shall include: 26

1. DRAM Test 27 2. SRAM Test 28 3. FLASH Stress (read/write) Test 29 4. Memory Tests 30 5. Timer Tests 31 6. Datakey Tests 32 7. USB Tests. 33 8. Ethernet Tests. 34

35 • Front Panel (when used) tests shall include: 36

1. Display Tests 37 2. Keyboard Tests. 38

39 • I/O tests shall include: 40

1. I/O Loop Back Tests. 41 42 • Asynchronous/Synchronous Communication Port tests shall include: 43

1. Loop Back Tests. Single Port and Port to Port. 44




2. Aggregate throughput tests 1 2 Utility Function Tests: 3

4 • Time of Day Functions 5

1. Display Time of Day (TOD) Clock 6 2. Set Time of Day (TOD) Clock 7 3. Enable Daylight Savings Time 8 4. Disable Daylight Savings Time 9 5. Line frequency tests 10 6. Clock accuracy tests 11

12 • Ethernet Functions 13

1. Get Current IP Address 14 2. Set Current IP Address 15 3. Load IP Address from Datakey 16 4. Save IP Address from Datakey 17 5. Start Ethernet 18

19 • Clear Error Log 20

• Configure Continuous Tests 21

• Start Application. 22

23 Testing shall be performed on the Controllers either within an Environmental Chamber or 24 on a bench. Controllers are not required to be installed within a cabinet during these 25 tests. 26 27 These test procedures do not verify equipment performance under every possible 28 combination of environmental requirements covered by this standard. However, nothing 29 in this testing profile shall be construed as to relieve the requirement that the equipment 30 provided must fully comply with these standards/specifications under all environmental 31 conditions stated herein. 32 33 Individual agencies may wish to extend the testing profile or introduce additional tests to 34 verify compliance. (Authorized Engineering Information). 35 36

9.2 Inspection 37 A visual and physical inspection shall include mechanical, dimensional and assembly 38 conformance to all parts of this standard. 39 40




9.3 Testing Certification 1 Complete quality control / final test report shall be supplied with each item (see Section 2 10.1.3). 3 4

9.4 Definitions of Design Acceptance Testing (DAT) and 5

Production Testing. 6 7 Design Acceptance Testing (DAT) is performed on the first article controller unit, and is a 8 part of the pre-production process. 9 10 Production Testing is performed on all units prior to shipment to an agency. 11 12

9.5 Environmental and Operating Requirements 13 The requirements (voltage, temperature, etc.) of this section shall apply in any 14 combination. 15 16

9.5.1 Voltage and Frequency 17

9.5.1.1 Operating Voltage 18 The nominal voltage shall be 120 VAC, unless otherwise noted. 19 20

9.5.1.2 Operating Frequency 21 The operating frequency range shall be 60 Hz (±3.0 Hz), unless otherwise noted.. 22 23

9.5.2 Transients, Power Service 24 The Test Unit shall maintain all defined functions when the independent test pulse levels 25 specified in Section 9.5.2.1 on an individual unit, and Section 9.5.2.2 occur on the 26 alternating-current power service in a controller unit. 27 28

9.5.2.1 High-Repetition Noise Transients (DAT and Production 29 testing) 30

The test pulses shall not exceed the following conditions: 31 32

1. Amplitude: 300 V, both positive and negative polarity. 33 34 2. Peak Power: 2500 W. 35 36




3. Repetition: 1 pulse approximately every other cycle moving uniformly over the full 1 wave in order to sweep across 360˚ of the line cycle once every 3 seconds. 2

3 4. Pulse Rise Time: 1 µs. 4 5 5. Pulse Width: 10 µs. 6 7

9.5.2.2 Low-Repetition High-Energy Transients (DAT) 8 The test pulses shall not exceed the following conditions: 9 10

1. Amplitude: 600 V, both positive and negative polarity. 11 12 2. Energy Source: Capacitor, oil filled, 10 ± 1 µF, internal surge impedance less 13

than 1 Ω. 14 15 16 3. Repetition: 1 discharge every 10 seconds. 17 18 4. Pulse Position: Random across 360˚ of the line cycle. 19 20

9.5.3 Nondestructive Transient Immunity (DAT) 21 The Test Unit shall be capable of withstanding a high energy transient having the 22 following characteristics repeatedly applied to the alternating current input terminals (no 23 other power connected to terminals) without failure of the test specimen: 24 25

1. Amplitude: 2000 ± 100 V , both positive and negative polarity. 26 27 2. Energy Source: Capacitor, oil filled, 15 ± 1.5 µF, internal surge impedance less 28

than 1 Ω. 29 30 3. Repetition: Applied to the Test Unit once every 2 seconds for a maximum of 31

three applications for each polarity. 32 33 4. After the foregoing, the Test Unit shall perform all defined functions upon the 34

application of nominal alternating current power. 35 36

5. Repetition: 1 pulse per second, for a minimum of 5 pulses per selected terminal. 37 38 6. Pulse rise time: 1 µs. 39 40 7. Pulse width: 10 µs. 41

42




9.5.4 Temperature and Humidity 1 The Test Unit shall maintain all programmed functions when the temperature and 2 humidity ambients are within the specified limits defined herein (9.5.4.1 and 9.5.4.2). 3 4

9.5.4.1 Ambient Temperature 5 The operating ambient temperature range shall be from -37 ˚C to +74 ˚C. The storage 6 temperature range shall be from -45 ˚C to +85 ˚C. 7 8 The rate of change in ambient temperature shall not exceed 18 ˚C per hour, during 9 which the relative humidity shall not exceed 95%. 10

9.5.4.2 Humidity 11 The relative humidity shall not exceed 95% non-condensing over the temperature range 12 of -37 ˚C to +74 ˚C. 13 14 Above +46 ˚C, constant absolute humidity shall be maintained. This will result in the 15 relative humidities shown in Table 9-1 for dynamic testing. 16

17 18 19

Table 9-1: Ambient Temperature Versus Relative Humidity At Barometric 20 Pressures (29.92 In. Hg.) (Non-Condensing) 21

Ambient Temperature/ Dry Bulb (˚C)

Relative Humidity (in%)

Ambient Temperature/ Wet Bulb (˚C)

-37.0 to 1.1 10 -17.2 to 42.7 1.1 to 46.0 95 42.7

48.8 70 42.7 54.4 50 42.7 60.0 38 42.7 65.4 28 42.7 71.2 21 42.7 74.0 18 42.7

22

9.6 Test Facilities 23 All instrumentation required in the test procedures, such as voltmeters, ammeters, 24 thermocouples, pulse timers, etc. shall be selected in accordance with good engineering 25 practice. Calibration records for all test equipment shall be provided with test 26 documentation. In all cases where time limit tests are required, the allowance for any 27 instrumentation errors shall be included in the limit test. 28 29

1. Variable Voltage Source: A variable source capable of supplying 20 A from 0 30 VAC to 135 VAC. 31




1 2. Environmental Chamber: An environmental chamber capable of attaining 2

temperatures of -37 ˚C to +74 ˚C and relative humidities given in Table 9-1. 3 4 3. Transient Generator(s): Transient generator(s) capable of supplying the 5

transients outlined in Sections 9.5.2 through 9.5.4. 6 7 8 9 10 11

9.7 Test Procedure: Transients, Temperature, Voltage, 12

and Humidity 13 14

9.7.1 Test A: (DAT) Placement in Environmental Chamber and 15 Check-Out of Hook-Up 16

17 1. Place the test unit in the environmental chamber. Connect the test unit AC input 18

circuit to a variable voltage power transformer, voltmeter, and transient 19 generator. The transient generator shall be connected to the AC input circuit at a 20 point at least 25 feet from the AC power source and not over 10 feet from the 21 input to the test unit. 22

23 2. Connect test switches to the appropriate terminals to simulate the various 24

features incorporated into the test unit. Place these switches in the proper 25 position for desired operation. 26

27 3. Verify the test hook-up. Adjust the variable-voltage power transformer to 120 28

VAC and apply power to the test unit. Verify that the test unit goes through its 29 prescribed startup sequence and cycles properly in accordance with the 30 operation determined by the positioning of test switches in item 2. 31

32 Upon the satisfactory completion and verification of the test hook-up, proceed with Test 33 B. 34 35

9.7.2 Test B: (DAT) Temperature Cycling and Applied Transient 36 Tests (Power Service) 37

38 1. Program the test unit to dwell. Verify the input voltage is 120 VAC. 39 40 2. Set the transient generator to provide high-repetition noise transients as follows: 41

a. Amplitude: 300 ± 15 V, both positive and negative polarity. 42




b. Peak Power: 2500 W. 1 c. Repetition Rate: One pulse every other cycle moving uniformly over the 2

full wave in order to sweep once every 3 s across 360˚ of line cycle. 3 d. Pulse Rise Time: 1 µs. 4 e. Pulse Width: 10 µs. 5 6

3. Apply the transient generator output to the AC voltage input for at least 5 7 minutes. Repeat this test for at least two conditions of dwell for the test unit. The 8 test unit must continue to dwell without malfunction. 9

10 4. Program the test unit to cycle through normal operations. Turn on the transient 11

generator (output in accordance with item 2) for 10 minutes, during which time 12 the test unit shall continue to cycle without malfunction. 13

14 5. Set a transient generator to provide high-repetition noise transients as follows: 15

a. Amplitude: 300 ± 15 V, both positive and negative polarity. 16 b. Source Impedance: Not less than 1000 Ωnominal impedance. 17 c. Repetition: One pulse per second for a minimum of five pulses per 18

selected terminal. 19 d. Pulse Rise Time: 1 µs. 20 e. Pulse Width: 10 µs. 21 22

Program the test unit to dwell. Verify the input voltage is 120 VAC. 23 24

6. Apply the transient generator (output in accordance with item 5) between 25 logic ground and the connecting cable termination of selected Field I/O 26 input/output terminals of the test unit. 27 28 A representative sampling of selected input/output terminations shall be tested. 29 The test unit shall continue to dwell without malfunction. 30 31

7. Program the test unit to cycle. Turn on the transient generator (output in 32 accordance with item 5) and apply its output to the selected Field I/O input/output 33 terminations. The test unit shall continue to cycle without malfunction. 34

35 8. Set a transient generator to provide low-repetition high-energy transients as 36

follows: 37 a. Amplitude: 600 ± 30 V, both positive and negative polarity. 38 b. Energy Discharge Source: Capacitor, oil-filled, 10 µF. 39 c. Repetition Rate: One discharge each 10 s. 40 d. Pulse Position: Random across 360 degrees of line cycle. 41 42

9. Program the test unit to dwell. Verify the input voltage is 120 VAC. 43 44 10. Discharge the oil-filled 10 µF capacitor ten times for each polarity across the AC 45

voltage input. Repeat this test for at least two conditions of dwell. The test unit 46 shall continue to dwell without malfunction. 47




1 11. Program the test unit to cycle through normal operations. Discharge the 2

capacitor ten times for each polarity while the test unit is cycling, during which 3 time the test unit shall continue to cycle without malfunction. 4

5 12. During the preceding transient tests (item 3 through 11), the test unit must 6

continue its programmed functions. 7 8 The test unit shall not skip normal program intervals/steps or portions thereof 9 when in normal operation; place false inputs or produce false outputs while in 10 dwell; disrupt normal sequences in any manner; or change parameters. Details 11 of requirements established by appropriate DAT program. 12 13

13. Nondestructive Transient Immunity: 14 a. Turn off the AC power input to the test unit from the variable-voltage 15

power source. 16 b. Apply the following high-energy transient to the AC voltage input 17

terminals of the test unit (no other power connected to terminals): 18 (1) Amplitude: 2000 V, both positive and negative polarity. 19 (2) Peak Power Discharge: Capacitor, oil-filled, 15 µF. 20 (3) Maximum Repetition Rate: Applied to the Controller Assembly once 21

every 2 s for a maximum of three applications for each polarity. 22 c. Upon completion of the foregoing, apply 120 VAC to the test unit and 23

verify that the test unit goes through its prescribed startup sequence and 24 cycles properly in accordance with the programmed functions. The first 25 operation of the over-current protective device during this test shall not be 26 considered a failure of the test unit. 27

28 NOTE—Test C through G follow the profile indicated in Figure 9-1 to demonstrate the ability of 29 the test unit to function reliably under stated conditions of temperature, voltage, and humidity. 30




1

Figure 9-1: Test Profile 2 3

NOTES: 4 1. The rate of change in temperature shall not exceed 18˚ C per hour. 5 2. Humidity controls shall be set in conformance with the humidities given in Exhibit 3-1 6

during the temperature change between Test D and Test E. 7 3. If a change in both voltage and temperature are required for the next test, the voltage 8

shall be selected prior to the temperature change. 9 4. When testing a NEMA unit, the LOW voltage shall be 89VAC in place of 100 VAC. All 10

other units will use the 100VAC test level. 11 12

9.7.3 Test C:(DAT and Production Testing) Low-Temperature 13 Low-Voltage Tests 14

15 1. Definition of Test Conditions 16

a. Environmental Chamber Door: Closed. 17 b. Temperature: -37˚ C. 18 c. Low Voltage: 100 VAC. 19 d. Humidity Control: Off. 20 21

40

30

10

20

0

10

70

60

50

40

30

20

80

DCA+B F GE

(AMBIENT)

120

VAC

120

VAC

100

VAC

135

VAC

135

VAC

100

VAC

TEM

PER

ATU

RE,

in D

EGR

EES

CEL

SIU

S

SEE NOTES1 AND 3

SEE NOTES1 AND 2

SEE NOTES1 AND 3

X

XX

XX

X




2. Test Procedure: While at room temperature, adjust the input voltage to 100 VAC 1 and verify that the test unit is still operable. 2

a. With the test unit cycling through normal operations, lower the test 3 chamber to -37˚ C at a rate not exceeding 18˚ C per hour. Allow the test 4 unit to cycle for a minimum of 5 hours at -37˚ C with the humidity controls 5 in the off position. Then operate the test switches as necessary to 6 determine that all functions are operable. 7

b. Power shall then be removed from the test unit for a minimum period of 5 8 hours. Upon restoration of power, the test unit shall go through its 9 prescribed startup sequence and then resume cycling. 10

c. With the test unit at -37˚ C and the input voltage at 100 VAC, the following 11 items shall be evaluated against the respective standards: 12

1) Given in Section 9.10 Power Interruption Tests 13 2) Transient voltage tests 14

15 On satisfactory completion of this test, proceed with Test D. 16 17

9.7.4 Test D:(DAT and Production Testing) Low-Temperature 18 High-Voltage Tests 19


a. Environmental Chamber Door: closed. 22 b. Low Temperature: -37˚ C. 23 c. High Voltage: 135 VAC. 24 d. Humidity Controls: Off. 25 26

2. Test Procedure: While at -37˚ C and with humidity controls off, adjust the input 27 voltage to 135 VAC and allow the test unit to cycle for 1 hour. Then operate the 28 test switches as necessary to determine that all functions are operable. 29

30 3. With the test unit at -37˚ C and the input voltage at 135 VAC (humidity controls 31

off), the following items shall be evaluated against the respective standards: 32 i. Given in Section 9.10 Power Interruption Tests 33 ii. Transient voltage tests 34

35 On satisfactory completion of this test, proceed to Test E. 36 37

9.7.5 Test E: (DAT and Production Testing) High-Temperature 38 High-Voltage Tests 39


a. Environmental Chamber Door: Closed. 42 b. High Temperature: +74˚ C. 43 c. High Voltage: 135 VAC. 44




d. Humidity Controls: In accordance with the humidities given in Exhibit 3-1. 1 2

2. Test Procedure—With the test unit cycling, raise the test chamber to +74˚ C at a 3 rate not to exceed 18˚ C per hour. Verify the input voltage is 135 VAC. 4

5 3. Set the humidity controls to not exceed 95% relative humidity over the 6

temperature range of +1.1˚ C to +46˚ C. When the temperature reaches +46˚ C, 7 readjust the humidity control to maintain constant absolute humidity; +42.7˚ C 8 wet bulb which results in the relative humidities shown in Table 2-1. Verify that 9 the test unit continues to cycle satisfactory during the period of temperature 10 increase and at established levels of relative humidity. 11

a. Allow the test unit to cycle for a minimum of 15 hours at +74˚ C and 18% 12 relative humidity. Then operate the test switches as necessary to 13 determine that all functions are operable. 14

b. With the test unit at +74˚ C and 18% relative humidity and the input 15 voltage at 135 VAC, the following items shall be evaluated against the 16 respective standards: 17

i. Given in Section 9.10 Power Interruption Tests 18 ii. Transient voltage tests 19

20 On satisfactory completion of this test, proceed to Test F. 21 22

9.7.6 Test F: (DAT and Production Testing) High-Temperature 23 Low-Voltage Tests 24


a. Environmental Chamber Door: Closed. 27 b. High Temperature: +74˚ C. 28 c. Low Voltage: 100 VAC. 29 d. Humidity Controls: 18% relative humidity and +42.7˚ C wet bulb. 30 31

2. Test Procedure: Adjust the input voltage to 100 VAC and proceed to operate the 32 test switches to determine that all functions are operable. With the test unit at 33 +74˚ C and 18% relative humidity, +42.7˚ C wet bulb, and the input voltage at 34 100 VAC, the following items shall be evaluated against the respective 35 standards: 36

a. Given in Section 9.10 Power Interruption Tests 37 b. Transient voltage tests 38

39 On satisfactory completion of this test, proceed to Test G. 40 41

9.7.7 Test G: Test Termination (All tests) 42 43

1. Program the test unit to cycle according to DAT. 44




1 2. Adjust the input voltage to 120 VAC. 2 3 3. Set the controls on the environmental chamber to return to room temperature, 4

+20˚ C ± 5˚ C, with the humidity controls in the off position. The rate of 5 temperature change shall not exceed 18˚ C per hour. 6

7 4. Verify the test unit continues to cycle through normal operations properly. 8 9 5. Allow the test unit to stabilize at room temperature for 1 hour. Proceed with test 10

program to determine that all functions are operable. 11 12

9.7.8 Test H: Appraisal of Equipment under Test 13 14

1. A failure shall be defined as any occurrence which results in other than normal 15 operation of the equipment. (See item 2 for details.) If a failure occurs, the test 16 unit shall be repaired or components replaced, and the test during which failure 17 occurred shall be restarted from its beginning. 18

19 2. The test unit is considered to have failed if any of the following occur: 20

a. If the test unit skips normal program intervals/steps or portions thereof 21 when in normal operation, places false inputs, presents false outputs, 22 exhibits disruption of normal sequence of operations, or produces 23 changes in parameters beyond specified tolerances, or 24

b. If the test unit fails to satisfy the requirements of Section 9.7 Tests A to G, 25 inclusive. 26

27 3. An analysis of the failure shall be performed and corrective action taken before 28

the test unit is retested in accordance with this standard. The analysis must 29 outline what action was taken to preclude additional failures during the tests. 30

31 4. When the number of failures exceeds two, it shall be considered that the test unit 32

fails to meet these standards. The test unit may be completely retested after 33 analysis of the failure and necessary repairs have been made in accordance with 34 item 3. 35

36 5. Upon completion of the tests, the test unit shall be visually inspected. If material 37

changes are observed which will adversely affect the life of the test unit, the 38 cause and conditions shall be corrected before making further tests. 39

40 6. Upon satisfactory completion of all of the tests described in Sections 9.7.1 41

through 9.7.8, the test unit shall be tested in accordance with Section 9.8. 42 43




9.8 Vibration Test (DAT) 1 Units such as the ATC 2070 and certain Controller Assemblies that are controlled by 2 specific mechanical design specifications are not subject to the tests in Sections, 9.8 3 through 9.9.4 (Authorized Engineering Information). Shock and vibration tests shall be 4 performed prior to environmental tests. 5 6

9.8.1 Purpose of Test 7 This test is intended to duplicate vibrations encountered by the test unit (individual major 8 components) when installed at its field location. 9 10 The test unit shall be fastened securely to the vibration test table prior to the start of the 11 test. 12 13

9.8.2 Test Equipment Requirements 14 15

1. Vibration table with adequate table surface area to permit placement of the test 16 unit. 17

18 2. Vibration test shall consist of: 19

a. Vibration in each of three mutually perpendicular planes. 20 b. Adjustment of frequency of vibration over the range from 5 Hz to 30 Hz. 21 c. Adjustment of test table excursion (double amplitude displacement) to 22

maintain a ‘g’ value, measured at the test table, of 0.5g; as determined by 23 the following formula: 24

g = 0.0511df2 25 Where: 26 d = excursion in inches 27 f = frequency in Hz 28

29

9.8.3 Resonance [Mechanical Resonant Frequency] Search 30 (DAT) 31

32 1. With the test unit securely fastened to the test table, set the test table for a 33

double amplitude displacement of 0.015 inch. 34 35 2. Cycle the test table over a search range from 5 Hz to 30 Hz and back within a 36

period of 12.5 minutes. 37 38 3. Conduct the resonant frequency search in each of the three mutually 39

perpendicular planes. 40 41 4. Note and record the resonant frequency determined from each plane. 42




a. In the event of more than one resonant frequency in a given plane, record 1 the most severe resonance. 2

b. If resonant frequencies appear equally severe, record each resonant 3 frequency. 4

c. If no resonant frequency occurs for a given plane within the prescribed 5 range, 30 Hz shall be recorded. 6

7

9.8.4 Endurance Test (DAT) 8 9

1. Vibrate the test unit in each plane at its resonant frequency for a period of 1 hour 10 at amplitude resulting in 0.5 G acceleration. 11

12 2. When more than one resonant frequency has been recorded in accordance with 13

Section 9.8.4, item number 4, the test period of 1 hour shall be divided equally 14 between the resonant frequencies. 15

16 3. The total time of the endurance test shall be limited to 3 hours, 1 hour in each of 17

three mutually perpendicular planes. 18 19

9.8.5 Disposition of Equipment under Test 20 21

1. The test unit shall be examined to determine that no physical damage has 22 resulted from the vibration tests. 23

24 2. The test unit shall be checked to determine that it is functionally operable in all 25

modes of its prescribed operation. 26 27 3. The test unit may be removed from the test table. Upon satisfactory completion 28

of the vibration test, proceed with the shock (impact) test described in Section 29 9.9. 30

31

9.9 Shock (Impact) Test (DAT/Production) 32

9.9.1 Purpose of Test 33 Shock and vibration tests shall be performed prior to environmental tests. 34 35 The purpose of this test is to determine that the test unit is capable of withstanding the 36 shock (impact) to which it may reasonably be subjected during handling and 37 transportation in the process of installation, repair, and replacement. It is to be noted 38 that the test unit is not, at this time, in its shipping carton. 39 40




The test unit shall be firmly fastened to the specimen table. In each of its three planes 1 the test unit shall be dropped from a calibrated height to result in a shock force of 10 G. 2 3

9.9.2 Test Equipment Requirements 4 5

1. Shock (impact) test fixture equivalent to that suggested by the simplified sketch 6 shown in Exhibit 3-3. 7

8 2. The test table shall have a surface area sufficient to accommodate the test unit. 9 10 3. The test table shall be calibrated and the items tested as indicated. This shock 11

test defines the test shock to be 10 ± 1 G. 12 a. Calibration of the test equipment for these shock tests shall be measured 13

by three accelerometers having fixed shock settings of 9 G, 10 G, and 11 14 G. They shall be Inertia Switch Incorporated ST-355, or the equivalent. 15 These devices shall be rigidly attached to the test table. 16

b. Calibration of the fixture for each item to be tested shall be as follows: 17 1) Place a dummy load weighing within 10% of the test unit on the table. 18 2) Reset the three accelerometers and drop the test table from a 19

measured height. 20 3) Observe that the accelerometers indicate the following: 21

a) The 9 G accelerometer shall be activated. 22 b) The 10 G unit may or may not be actuated. 23 c) The 11 G unit shall not be actuated. 24

c. Repeat calibration test (a) and (b) adjusting the height of the drop until, on 25 ten successive drops, the following occurs: 26 1) The 9 G unit is actuated ten times. 27 2) The 10 G unit is actuated between four to eight times. 28 3) The 11 G unit is not actuated on any of the ten drops. 29

30




1 Figure 9-2: Shock Test Fixture 2




1

9.9.3 Test Procedure (DAT/Production) 2 3

1. The calibration height of the drop for the particular item under test as determined 4 in Section 9.9.2 shall be used in this procedure. 5

6 2. Secure the test unit to the test table surface so that the test unit rests on one of 7

its three mutually perpendicular planes. 8 9 3. Raise the test table to the calibrated height. 10 11 4. Release the test table from the calibrated height, allowing a free fall into the box 12

of energy absorbing material below. 13 14 5. Repeat the drop test for each of the remaining two mutually perpendicular 15

planes, using the same calibrated height for each drop test of the same test unit. 16 17 6. The observations of the accelerometer for the three tests of the test item shall be: 18

a. The 9 G unit is actuated for all three tests. (Repeat the calibration if the 19 unit is not actuated.) 20

b. The 10 G unit may or may not be actuated in these tests. 21 c. The 11 G unit is not actuated on any drop. (If the unit is actuated, repeat 22

the calibration only if the test unit has suffered damage.) 23 24

7. Production Testing drop test procedure: while the unit is running, tilt and lift the 25 controller from the front four inches high and drop. 26

27

9.9.4 Disposition of Test Unit 28 29

1. Check the test unit for any physical damage resulting from the drop tests. 30 31 2. Check the test unit to determine that it is functionally operable in all modes of its 32

prescribed operation. 33 34 3. Satisfactory completion of all environmental tests, including the shock (impact) is 35

required. 36 37

9.10 Power Interruption Test Procedures (DAT) 38 39 The following power interruption tests shall be conducted at low input voltage (100 VAC) 40 and high input voltage (135 VAC) at -37˚ C, and +74˚ C. 41 42 43




9.10.1 Short Power Interruption 1 2 While the Test Unit is cycling through normal operations, remove the input voltage for a 3 period of 475 ms. Upon restoration of the input voltage, check to insure that the Test 4 Unit continues normal operation as though no power interruption has occurred. Repeat 5 this test three times. 6 Verify that the controller clock has not drifted as a result of the power interruptions. 7 Additional power interruption testing is to be performed at 550 ms, 750 ms, and 1 8 second outages to verify proper restart operation. 9 10

9.10.2 Voltage Variation 11 12 All circuits of the Test Unit shall be subjected to slowly varying line voltage during which 13 the Test Unit shall be subjected to line voltage that is slowly lowered from a nominal 120 14 VAC line voltage to 0 VAC at a rate of not greater than 2 VAC per second. The line 15 voltage shall then be slowly raised to 100 VAC at which point the Test Unit shall resume 16 normal operation without operator intervention. This test shall be performed at both -37˚ 17 C and +74˚ C, at a nominal 120 VAC line voltage. Repeat this test three times. 18 Verify that the controller clock has not drifted as a result of the power variations. 19 20

9.10.3 Rapid Power Interruption 21 22 The Test Unit shall be subjected to rapid power interruption testing of the form that the 23 power shall be off for 350 ms and on for 650 ms for a period of 2 minutes. Power 24 interruption shall be performed through electromechanical contacts of an appropriate 25 size for the load. During this testing, the controller shall function normally and shall 26 continue normal sequencing (operation) at the conclusion of the test. This test shall be 27 performed at both -37˚ C and +74˚ C, at a nominal 120 VAC line voltage. Repeat this 28 test three times. 29 Verify that the controller clock has not drifted as a result of the power interruptions. 30 31 32


PERFORMANCE AND MATERIAL REQUIREMENTS


10 PERFORMANCE AND MATERIAL 1

REQUIREMENTS 2 3

10.1 General 4

10.1.1 Furnished Equipment 5 6 All equipment furnished in compliance to this standard shall be new and unused. 7 Vacuum or gaseous tubes and electro-mechanical devices shall not be used unless 8 specifically called out. 9 10

10.1.2 Edges 11 12 All sharp edges and corners shall be rounded. 13 14

10.1.3 Hardware 15 16 All washers, nuts, bolts, hinges and hinge pins shall be stainless steel unless otherwise 17 specified. 18 19

10.1.4 Electrical Isolation 20 21 Within the circuit of any device, module, or printed circuit board (PCB), electrical 22 isolation shall be provided between DC ground, EG and AC. They shall be electrically 23 isolated from each other by 500 mega-MΩ, minimum, when tested at the input terminals 24 with 500 VDC. 25 26

10.1.5 Component Sources 27 28 All components shall be second sourced and shall be of such design, fabrication, 29 nomenclature or other identification as to be purchased from a wholesale distributor or 30 from the component manufacturer, except as follows: 31 32

10.1.5.1 Circuit Designs 33 The electronic circuit design shall be such that all components of the same generic type, 34 regardless of manufacturer, shall function equally in accordance with this standard. No 35




component shall be applied contrary to its manufacturer’s recommendations or data 1 sheets. 2 3

10.1.5.2 Operational Envelopes 4 No component shall be operated above 80% of its maximum rated voltage, current or 5 power ratings. Digital components shall not be operated above 3% over their nominal 6 voltage, current or power ratings. 7 8

10.1.5.3 Component Age 9 The design life of each component, operating for 24 hours a day and operating in its 10 circuit application, shall be 10 years or longer. 11

10.1.5.4 Component Packaging 12 Encapsulation of 3 or more discrete components into circuit modules is prohibited except 13 for transient suppression circuits, resistor networks, diode arrays, solid-state switches, 14 optical isolators and transistor arrays. Components shall be arranged so they are easily 15 accessible, replaceable and identifiable for testing and maintenance. Where damage by 16 shock or vibration exists, the component shall be supported mechanically by a clamp, 17 fastener, retainer, or hold-down bracket. 18 19

10.1.6 Capacitors 20 21 The DC and AC voltage ratings as well as the dissipation factor of a capacitor shall 22 exceed the worst-case design parameters of the circuitry by 1.5 times except for 23 Supercaps. Supercaps are capacitors rated less than 10 working Volts DC with 24 capacitance values greater than or equal to 0.1F. Capacitors which shall be required to 25 meet only their stated ratings. Capacitor encasements shall be resistant to cracking, 26 peeling and discoloration. All capacitors shall be insulated and shall be marked with 27 their capacitance values and working voltages. Electrolytic capacitors shall not be used 28 for capacitance values of less than 1.0 µF and shall be marked with polarity. 29 30

10.1.7 Resistors 31 32 Fixed carbon film, deposited carbon, or composition-insulated resistors shall conform to 33 the performance requirements of Military Specifications MIL-R-11F or MIL-R-22684. All 34 resistors shall be insulated. Resistance values for all discrete resistors shall be 35 indicated by the EIA color codes, or stamped value. The resistor value shall not vary by 36 more than 5% for carbon film and deposited carbon types and 10% for composition–37 insulated type over the range of -37° C to 74° C. Special ventilation or heat sinking 38 shall be provided for all resistors rated 2 W or higher. They shall be insulated from the 39 PCB. 40 41




10.1.8 Semiconductors 1 2 All transistors, integrated circuits, and diodes shall be a standard type listed by EIA and 3 clearly identifiable. All metal oxide semiconductor components shall contain circuitry to 4 protect their inputs and outputs against damage due to high static voltages or electrical 5 fields. Device pin "1" locations shall be properly marked on the PCB adjacent to the pin. 6 7

10.1.9 Transformers and Inductors 8 9 All power transformers and inductors shall have the manufacturer's name or logo and 10 part number clearly and legibly printed on the case or lamination. All transformers and 11 inductors shall have their windings insulated, shall be protected to exclude moisture, and 12 their leads color coded with an approved EIA color code or identified in a manner to 13 facilitate proper installation. 14 15

10.1.10 Fuses 16 17 All fuses shall be 3AG Slow Blow type and resident in a holder. Fuse size rating shall be 18 labeled on the holder. Fuses shall be easily accessible and removable without use of 19 tools. 20 Fuses shall not be easily dislodged during shipping and handling. 21

10.1.11 Switches 22

10.1.11.1 DIP Switches 23 Dual-inline-package, quick snap switches shall be rated for a minimum of 30,000 24 operations per position at 50 mA, 30 VDC. The switch contact resistance shall be 100 25 mΩ maximum at 2 mA, 30 VDC. The contacts shall be gold over brass (or silver). 26 Contact for VAC or 28 VDC and shall be silver over brass (or equal). 27 28

10.1.11.2 Logic Switches 29 The switch contacts shall be rated for a minimum of 1 A resistive load at 120 VAC and 30 shall be silver over brass (or equal). The switch shall be rated for a minimum of 40,000 31 operations. 32 33

10.1.11.3 Control Switches 34 The switch contacts shall be rated for a minimum of 5 A resistive load at 120 VAC or 28 35 VDC and shall be gold over brass (or equal). The switch shall be rated for a minimum of 36 40,000 operations. 37 38




10.1.11.4 Power Switches 1 The switch contacts shall be rated for a minimum of 5 A resistive load at 120 VAC or 28 2 VDC and shall be gold over brass (or equal). The switch shall be rated for a minimum of 3 10 A at 125 VAC. 4 5

10.1.12 Wiring, Cabling, and Harnesses 6

10.1.12.1 Harnesses 7 Harnesses shall be neat, firm and properly bundled with external protection. They shall 8 be tie-wrapped and routed to minimize crosstalk and electrical interference. Each 9 harness shall be of adequate length to allow any conductor to be connected properly to 10 its associated connector or termination point. Conductors within an encased harness 11 have no color requirements. 12 13

10.1.12.2 Bundling 14 Wiring containing AC shall be bundled separately or shielded separately from all DC 15 logic voltage control circuits. Wiring shall be routed to prevent conductors from being in 16 contact with metal edges. Wiring shall be arranged so that any removable assembly 17 may be removed without disturbing conductors not associated with that assembly. 18 Splicing or cutting/replacing of bundle wrapping is not allowed. 19 20

10.1.12.3 Conductor Construction 21 All conductors shall conform to MIL-W-16878E/1 or better and shall have a minimum of 22 19 strands of copper. The insulation shall be polyvinyl chloride with a minimum 23 thickness of 10 mils or greater. Where insulation thickness is 15 mils or less, the 24 conductor shall conform to MIL-W-16878/17. Conductor color identification shall be as 25 follows: 26 27

• AC - gray or continuous white color 28 • EG - solid green or continuous green color with 1 or more yellow stripes. 29 • DC logic ground - continuous white color with 1 red stripe. 30 • AC+ - continuous black color or black with colored stripe. 31 • DC logic ungrounded or signal - any color not specified 32

33

10.1.13 Indicators and Character Displays 34 35 All indicators and character displays, when supplied, shall be readily visible at a radius of 36 up to 4 feet within the cone of visibility when the indicator is subjected to 97,000 lux 37 (9,000 foot-candles) of white light with the light source at 45 ±2˚ to the front panel. 38 39




10.1.13.1 Range of Visibility 1 All indicators and character displays shall have a minimum 90˚ cone of visibility with its 2 axis perpendicular to the panel on which the indicator is mounted. All indicators shall be 3 self-luminous. All indicators shall have a rated life of 100,000 hours minimum. Each 4 LED indicator shall be white or clear when off. 5 6

10.1.13.2 LCDs 7 Liquid Crystal Displays (LCD), when used, shall operate at temperatures of -20 °C to 8 +70 °C and shall not be damaged nor otherwise adversely affect unit’s operation at 9 temperatures of -37 °C to +74 °C. Low temperature operation must have a sufficiently 10 fast reaction time to be readable for the integer value displayed. 11 12 Some agencies may wish to specify faster LED operation and lower temperature 13 operation which may necessitate the use of heaters for the LCD. When such heaters 14 are used, they shall only be energized at low temperature to support operator interaction 15 and shall be controllable through the application software. 16

10.1.14 Connectors 17 18 All connectors shall be keyed to prevent improper insertion of the wrong connector. The 19 mating connectors shall be designated as the connector number and male/female 20 relationship, such as C1P (plug) and C1S (socket). The connector shall be called out 21 base metal with minimum 0.00005 inch nickel plated with 0.000015 inch gold. 22 23

10.1.14.1 Plastic Circular and M Type Connectors 24 Pin and socket contacts, if used, for connectors shall be beryllium copper construction. 25 Pin diameter shall be 0.062 inch. All pin and socket connectors shall use the AMP 26 #601105-1 or #91002-1 contact insertion tool and the AMP #305183 contact extraction 27 tool. 28 29

10.1.14.2 Flat Cable Connectors 30 All flat cable connectors, where used, shall be designed for use with 26 AWG cable; 31 shall have dual cantilevered phosphor bronze contacts; and shall have a current rating of 32 1 A minimum and an insulation resistance of 5 MΩ minimum. 33

10.1.14.3 PCB Header Socket Connectors 34 Each PCB header socket block shall be nylon or diallyl phthalate. Each PCB header 35 socket contact shall be removable, but crimp-connected to its conductor. The 36 manufacturer shall list the part number of the extraction tool recommended by its 37 manufacturer. Each PCB header socket contact shall be brass or phosphor bronze. 38 39




10.1.14.4 Metallic Circular Connectors [NEMA] 1 Metallic Circular Connectors shall comply and interface with MS 116 Shell type. 2 3

10.1.15 PCB Design 4 5 No components, traces, brackets or obstructions shall be within 0.175 inch of a PC 6 board edge (guide edges). The manufacturer's name or logo, model number, serial 7 number, and circuit issue or revision number shall appear and be readily visible on all 8 PCBs. Devices to prevent the PCB from backing out of its assembly connectors shall be 9 provided. All screw type fasteners shall utilize locking devices or locking compounds 10 except for finger screws, which shall be captive. Solder quality should conform to IPC 11 610 specification for Industrial ratings. Serial numbers on PCBs shall be permanent. 12 13

10.1.16 Tolerances 14 The following tolerances shall apply, except as specifically shown on the plans or in 15 these specifications: 16 17 Sheet Metal ± 1.334 mm (0.0525 inch) 18 PCB ± 0.254 mm (0.010 inch) 19 Edge Guides ± 0.381 mm (0.015 inch) 20 21 22 23


QUALITY CONTROL


11 QUALITY CONTROL 1 2 Materials in this section are considered a supplement to that provided in Section 9. In 3 the case of apparent inconsistencies, materials in Section 9 of this standard shall prevail. 4

11.1 Components 5 6 All components shall be lot sampled to assure a consistent high conformance standard 7 to the design specification of the equipment. 8 9

11.1.1 Subassembly, Unit Or Module 10 11 Complete electrical, environmental and timing compliance testing shall be performed on 12 each module, unit, printed circuit or subassembly. Housing, chassis, and connection 13 terminals shall be inspected for mechanical sturdiness, and harnessing to sockets shall 14 be electrically tested for proper wiring sequence. The equipment shall be visually and 15 physically inspected to assure proper placement, mounting, and compatibility of 16 subassemblies. 17 18

11.1.2 Predelivery Repair 19 20 Any defects or deficiencies found by the inspection system involving mechanical 21 structure or wiring shall be returned through the manufacturing process or special repair 22 process for correction. PCB flow soldering is allowed a second time if copper runs and 23 joints are not satisfactorily coated on the first run. Hand soldering is allowed for printed 24 circuit repair. 25 26

11.1.3 Manufacturers’ Quality Control Testing Certification 27 28 Guidance: If requested by the purchasing agency, quality control procedures 29 shall be submitted prior to production. A compliant test report that is part of the 30 quality control procedure shall be supplied with each delivered unit. Along with 31 pass fail information this report shall include the quality control procedure, test 32 report format, and the name of the tester. It should be counter-signed by a 33 corporate officer. 34 35 The quality control procedure shall include the following: 36 37

• Design Acceptance testing of all supplied components. 38

• Physical and functional testing of controller units. 39


QUALITY CONTROL


• Environmental testing report(s) and final acceptance. 1

• Acceptance testing of all supplied components. 2

• Physical and functional testing of all modules and items. 3

• Verification of a minimum burn-in of all equipment. 4

5 6


GLOSSARY


12 GLOSSARY 1 2

12.1 Physical Units 3 4 Wherever the following units are used, the intent and meaning shall be interpreted as 5 follows: 6 7

A Ampere 8 b - bit 9 bps - bits per second 10 B - byte 11 ˚C - Degrees Celsius 12 dB - Decibel 13 dBa - Decibels above reference noise, adjusted 14 F - Farad 15 ft - foot 16 g - gram 17 G - Earth gravitational constant 18 Hz - Hertz 19 in - inches 20 J - Joule 21 m - meter 22 N - Newton 23 Ω - Ohm 24 s - second 25 V - Volt 26 W - Watt 27 28

12.2 Modifiers 29 Wherever the following modifiers are used as a prefix to a physical unit, the intent and 30 meaning shall be interpreted as follows: 31 32

k - kilo = 1000 33 M - Mega = 1 000 000 34 m - milli = 0.001 35 µ - micro = 0.000 001 36 n - nano = 0.000 000 001 37 p - pico = 0.000 000 000 001 38


GLOSSARY


12.3 Acronyms and Definitions 1 2 AASHTO American Association of State Highway and Transportation 3

Officials 4

AC Alternating Current 5

AC- 120 VAC, 60 Hz neutral (grounded return to the power source) 6

AC+ 120 VAC, 60 Hz line source (ungrounded) 7

ANSI American National Standard Institute 8

API Application Programming Interface 9

ASCII American Standard Code for Information Interchange 10

Assembly A complete machine, structure, or unit of a machine that was 11 manufactured by fitting together parts and/or modules 12

ASTM American Society for Testing and Materials 13

ATC Advanced Transportation Controller 14

AWG American Wire Gage 15

Cabinet An outdoor enclosure generally housing the controller unit and 16 associated equipment 17

Caltrans California Department of Transportation 18

CD Carrier Detect 19

Channel An information path from a discrete input to a discrete output 20

Component Any electrical or electronic device 21

CPU Central Processing Unit 22

CTS Clear to send (data) 23

CU Controller Unit, that portion of the controller assembly devoted to 24 the operational control of the logic decisions programmed into the 25 assembly 26

DAT Design Acceptance Testing 27

DC Direct Current 28

DCD Data Carrier Detect (receive line signal detector) 29

DRAM Dynamic Random Access Memory 30

EEPROM Electrically Erasable Programmable Read-Only Memory 31

EG Equipment Ground 32

EIA Electronic Industries Association 33

EL Electro-luminescent 34


GLOSSARY


EMI Electromagnetic Interference 1

ENET Ethernet 2

EPROM Ultraviolet Erasable, Programmable, Read-Only Memory 3

Equal Connectors: comply to physical dimensions, contact material, 4 plating and method of connection. 5

Devices: comply to function, pin out, electrical and operating 6 parameter requirements, access times and interface parameters 7 of the specified device 8

ETL Electrical Testing Laboratories, Inc. 9

FCU Field Control Unit 10

Firmware A computer program or software stored permanently in PROM, 11 EPROM, ROM, or semi-permanently in EEPROM 12

FLASH solid-state, permanent, non-volatile memory typically having fast 13 access and read/write cycles 14

FPA Front Panel Assembly 15

FSK Frequency Shift Keying 16

HDLC High-level Data Link Control 17

Host Module Support for Engine Board 18

I/O Input/Output 19

IEEE Institute of Electrical and Electronics Engineers 20

IP Internet Protocol 21

ISO International Standards Organization 22

ITE Institute of Transportation Engineers 23

ITS Intelligent Transportation Systems 24

Jumper A means of connecting/disconnecting two or more conductors by 25 soldering/desoldering a conductive wire or by PCB post jumper 26

Keyed Means by which like connectors can be physically altered to 27 prevent improper insertion 28

LCD Liquid Crystal Display 29

LED Light Emitting Diode 30

LOGIC Negative logic convention (Ground True) state 31

logic-level HCT or equivalent TTL – compatible voltage interface levels 32

lsb Least Significant Bit 33

LSB Least Significant Byte 34

MIPS Million Instructions per Second 35


GLOSSARY


MMU Malfunction Monitor Unit 1

Module A functional unit that plugs into an assembly 2

msb Most Significant Bit 3

MSB Most Significant Byte 4

NA Presently Not Assigned. Cannot be used by the contractor for 5 other purposes 6

NEMA National Electrical Manufacturer's Association 7

NETA National Electrical Testing Association, Inc. 8

NLSB Next Least Significant Byte 9

NMSB Next Most Significant Byte 10

NTCIP National Transportation Communication for ITS Protocols 11

O/S Operating System 12

Open System standardized hardware interfaces in a module 13

PCB Printed Circuit Board 14

PDA Personal Data Assistant (electronic) 15

RAM Random Access Memory 16

RF Radio Frequency 17

RMS Root mean square 18

ROM Read only memory 19

RTC Real Time Clock 20

RTS Request to send (data) 21

RX Receive 22

SDLC Synchronous Data Link Control 23

SP Serial Port 24

SPI Serial Peripheral Interface 25

SRAM Static Random Access Memory 26

TEES Traffic Equipment Electrical Specification 27

TMC Transportation Management Center 28

TOD Time Of Day Clock 29

TTL Transistor-Transistor Logic 30

TX Transmit 31

UL Underwriter's Laboratories, Inc. 32

USB Universal Serial Bus 33


GLOSSARY


VAC Volts Alternating Current 1

VDC Volts Direct Current 2

WDT Watchdog Timer: A monitoring circuit, external to the device 3 watched, which senses an Output Line from the device and reacts 4

5 6 7

ATC v. 5 - Institute of Transportation Engineers --...

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