Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT...
Transcript of Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT...
![Page 1: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/1.jpg)
Asynchronous Asynchronous FSMs and FSMs and
VerilogVerilog
![Page 2: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/2.jpg)
PLD registered outputPLD registered output
![Page 3: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/3.jpg)
Outputs selection capability Outputs selection capability in CPLDin CPLD
![Page 4: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/4.jpg)
State Machine with Moore outputState Machine with Moore output
![Page 5: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/5.jpg)
State State Machine Machine with with Embedded Embedded Mealy Mealy output output definitions definitions (7.28)(7.28)
![Page 6: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/6.jpg)
Table 7.29. FSM with pipelined output definitions
![Page 7: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/7.jpg)
Test VectorsTest Vectors
![Page 8: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/8.jpg)
Test Vectors continuedTest Vectors continued
![Page 9: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/9.jpg)
Table for example state machineTable for example state machine
![Page 10: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/10.jpg)
FFs in librariesFFs in libraries
![Page 11: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/11.jpg)
Behavioral Verilog for Behavioral Verilog for DFFDFF
![Page 12: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/12.jpg)
Verilog for D FFVerilog for D FF
![Page 13: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/13.jpg)
Verilog for D FFVerilog for D FF
![Page 14: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/14.jpg)
Clock generation within a Clock generation within a test benchtest bench
![Page 15: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/15.jpg)
Moore FSM implied by Moore FSM implied by Verilog coding styleVerilog coding style
![Page 16: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/16.jpg)
Table for example Table for example FSMFSM
![Page 17: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/17.jpg)
Table 7.58. Table 7.58. Verilog Verilog
Program for Program for FSM FSM
exampleexample
![Page 18: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/18.jpg)
Synchronous and Asynchronous Synchronous and Asynchronous reset for FSMs in Verilogreset for FSMs in Verilog
![Page 19: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/19.jpg)
Verilog code for pipelined Verilog code for pipelined outputoutput
![Page 20: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/20.jpg)
Verilog FSM with pipelined Verilog FSM with pipelined outputsoutputs
![Page 21: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/21.jpg)
Table 7.61. Table 7.61. Simplified Simplified
Verilog Verilog FSM FSM
designdesign
![Page 22: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/22.jpg)
Table 7.62. Alternative Verilog for Table 7.62. Alternative Verilog for ones-counting machineones-counting machine
![Page 23: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/23.jpg)
Ones-Counting MachineOnes-Counting Machine
![Page 24: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/24.jpg)
Fastest and smallest Verilog Fastest and smallest Verilog counting logic for ones-counting counting logic for ones-counting
machinemachine
![Page 25: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/25.jpg)
Memory for lock machineMemory for lock machine
![Page 26: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/26.jpg)
Explicit FF instantiation in Explicit FF instantiation in Verilog Verilog
![Page 27: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/27.jpg)
One-Hot encodingOne-Hot encoding
![Page 28: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/28.jpg)
Table 7.68. Table 7.68. Test Bench Test Bench for FSM of for FSM of Table 7.58 Table 7.58
(with (with synchronous synchronous reset added) reset added) or Table 7.60, or Table 7.60, 7.61, 7.66 or 7.61, 7.66 or
7.577.57
![Page 29: Asynchronous FSM . Verilog - Wakerly Chapter_07.pptweb.cecs.pdx.edu/~mperkows/CLASS_17… · PPT file · Web view · 2009-05-13FSM with pipelined output definitions Test Vectors](https://reader031.fdocuments.us/reader031/viewer/2022021502/5ae431e67f8b9a5b348e6543/html5/thumbnails/29.jpg)
SR latchSR latch