Asymmetric Half Bridge (AHB) Converters - By Fairchild

8/13/2019 Asymmetric Half Bridge (AHB) Converters - By Fairchild

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www.fairchildsemi.com

1

Design Considerations for Asymmetric

Half-Bridge (AHB) Converters

Hangseok Choi

2

Agenda

Introduction

Idealized Operation of AHB Converters

Steady state Analysis of an Actual AHB Converter

Design Procedure with Example

Design Tips

Experimental Verification

Conclusion


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3

Introduction: Why Soft-Switching?

Ever increasing demand for higher power densities in power converters has forced

engineers to increase switching frequencies. Switching Losses, however, havehindered high frequency operation

Capacitive loss Reverse recovery lossOverlap of voltage and current

Soft-switching technique can reduce switching losses

4

Basic Features of an AHB Converter

Inherent zero voltage switching (ZVS) capability since parasitic

components can be incorporated to achieve ZVS

High efficiency and low EMI through ZVS

Simple topology and simple control

MOSFET voltage is clamped to the input voltage

Fixed switching frequency operation

Smaller inductor can be used compared to forward converter

topologies (less than half)


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5

Idealized Operation of an AHB Converter

Basic Concept

What if an asymmetric square wave is introduced to the transformer?

Transformer will be saturated

What if an asymmetric square wave is introduced to the transformer in series

with a DC blocking capacitor?

Not saturated thanks to the voltage of blocking capacitor

CB

+V

p

-

+V

d

-

+ VCB

-

Same area

VCB

+V

p

-

1 : 1

0

0

6


Voltage Gain

CB

+

Vp

-

+

Vd

-

- VCB

+

+

Vrec

-n : 1

D

Vin

+

Vo

-

VCB

Vp Vrec

Vo

Vd

Vin

Io

D

1-D

Q1

Q2

ILOIp

Lm

IM

Vin

-VCB

( ) (1 )

(1 ) 2 (1 )( )

in C B C B C B in

oin C B C B o

in

V V D V D V V D

VD D D DV V V V

n n V n

= =

+ = =


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7


Magnetizing Current

In steady state, the mean value of the transformer magnetizing current, IM.avg is

obtained from the condition for zero net current through the DC blocking capacitor

(CB) as

CB

+

Vp

-

+

Vd

-

- VCB

+

+

Vrec

-n : 1

D

Vin

+

Vo

-

VCB

Vp Vrec

Vo

Vd

Vin

Io

D

1-D

Q1

Q2

ILOIp

Lm

IM

. .( ) ( )(1 )O O

M avg M avg

I II D I D

n n+ = +

. (1 2 ) O

M avg

II D

n=

8

Steady State Analysis of an AHB Converter

Effect of Series Inductor

CB

+

Vp

-

+

Vd

-

+ VCB

-

+

Vrec

-

n : 1

D

Vin

+

Vo

-

VCB

0Vp

0

Vrec

Vo

Vin

0Ip

Ip

CB

+

Vp

-

+

Vd

-

+ VCB

-

+

Vrec

-

n : 1

D

Vin

+

Vo

-

VCB

0Vp

0

VrecVo

Vin

0Ip

Ip

Lr

Actual model with series inductance

Series inductor causes Ip to lag Vp

Duty loss is observed in Vrec

Ideal model without series inductance

Ip is in phase with Vp

Duty loss is not observed in Vrec


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Basic Structure

Square wave generator

produces a square wave voltage (Vd) by driving switches Q1 and Q2 complementarily

Energy transfer network

removes the DC offset of the square wave voltage (Vd) using the DC blocking capacitor(CB)

transfers the pure AC square wave voltage to the secondary side through thetransformer

Causes Ip to lag Vprto provide ZVS condition for Q1 and Q2

Rectifier network

produces a DC voltage by rectifying the AC voltage with rectifier diodes and a low-passLC filter

+

VO

-

Ro

Q1

Q2

n:1

Ip

Llkp

Lm

CB

Ids2

Im

ILO

Vin

Io+

Vd

-

Square wave generator

Energy transfer network Rectifier network

VCB

+

Vpr

-

+

Vrec

-

Ids1

C2

C1

1-D

D

10

Steady State Analysis of an

AHB Converter

Basic assumptions for steady state analysis:

The dead time is negligible since it is very small compared to the

switching cycle

The leakage inductance is much smaller than the magnetizing

inductance

The DC blocking capacitor CB is large enough to neglect the voltage

ripple across CB

The output filter inductor operates in continuous conduction mode

All circuit elements are ideal and lossless

The duty cycle for lower MOSFET, D, is less than 50%

The capacitors C1 and C2 include not only the internal output

capacitance of the MOSFETs, but also the external parasitic

capacitance


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Mode I

The lower switch Q1 is conducting and a

voltage of (Vin-VCB) is applied to the

transformer primary side (Vpr)

The transformer primary side current (Ip) is

the sum of the output inductor currentreferred to as the primary side (ILO/n) and

magnetizing current (IM)

12


Mode II

The lower switch Q1 is turned off at t1 and

the primary side current, Ip charges C1 and

discharges C2

This mode continues until the primary side

voltage drops to zero (in order words, until

C2 is discharged to VCB) at t2


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Mode III

At t2, the transformer primary side and

secondary side voltages become zero and

the secondary side is decoupled from the

primary side

Then, the output inductor current, ILObegins to freewheel in the secondary side

through the rectifiers and C2 continues to bedischarged

14


Mode IV

The body diode of Q2 is conducting and the

voltage across the switch Q2 is clamped at

zero; By turning on Q2 while the body diode

is conducting, zero voltage switching (ZVS) is

achieved.

A voltage of -VCB is applied across the

leakage inductance and the primary side

current (Ip) decreases

During this mode, energy is not transferred

to the secondary side (duty losses)


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Mode V

The upper switch Q2 is conducting and -

VCB is applied to the transformer primary

side (Vpr)

The transformer primary side current (Ip)

is the sum of output inductor current

referred to as the primary side (-ILO

/n) and

the magnetizing current (IM)

16


Mode VI

The upper switch Q2 is turned off at t5and the primary side current Ip charges C2and discharges C1

This mode continues until the primaryside voltage becomes zero (in other

words, until C1 is discharged to Vin-VCB) at

t6


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Mode VII

At t6, the transformer primary side and

secondary side voltages become zero and

the secondary side is decoupled from the

primary side

Then, the output inductor current, ILO

begins to freewheel in the secondary sideand C1 continues to be discharged

18


Mode VIII

The body diode of Q1 is conducting and the

voltage across the switch Q1 is clamped at

zero voltage. By turning on Q1 while the body

diode is conducting, zero voltage switching

(ZVS) is achieved. During this mode, a voltage of (Vin-VCB) is

applied across the leakage inductance and

the primary side current (Ip) increases

During this mode, energy is not transferred

to the secondary side (duty losses)


10/19

19


ZVS Condition

ZVS turn-on condition for Q2:2 2

2 1 2

2 .

[ ( )] ( )[ ]

(1 )( )

2

lk p in

o in S p M avg

m

L I t C C DV

I V D DTI t I

n L

> +

= + +

2 2

6 1 2

6 .

[ ( )] ( )[(1 ) ]

(1 )( )

2

lk p in

o in S p M avg

m

L I t C C D V

I V D DTI t I

n L

> +

= +

Vgs1 Vgs2

Vds1

Vgs1

Vds2

IP

Vpr

D 1-D

Vin

Vin

Vin-V

CB VCB

Vgs1

Vgs1

Vgs2

Vgs2

VprVin-VCB

VCB

Vin-V

CB VCB

Vds2 V

ds1

mode II and III mode VI and VII

t1

t3

t2

t5

t7

t6

VCB

Vin-V

CB

ZVS turn-on condition for Q1:

20

Steady State Analysis of an Actual

AHB Converter

What happens as duty cycle approaches 50%?

Voltage stresses of the rectifier diodes

are balanced

Current stresses of the rectifier diodesare balanced

Current stresses of the primary side

MOSFETs are unbalanced

Magnetizing current DC offset decreases

1

(1 )in CB inD

V V V DV

n n

= =

2CB in

D

V V DV

n n

= =

. (1 2 )o

M avg

II D

n=


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21

Steady State Analysis of an Actual

AHB Converter

What happens as duty cycle decreases from 50%? Voltage stresses of the rectifier diode are

unbalanced

Current stresses of the rectifier diodesare unbalanced

Current stresses of the primary sideMOSFETs are unbalanced

Magnetizing current DC offset increases

1

(1 )in CB inD

V V V DV

n n

= =

2CB in

D

V V DV

n n

= =

. (1 2 )o

M avg

II D

n=

22


[STEP-1] Define the system specifications

Estimated efficiency (Eff) =92%

Input voltage range: hold up time should be considered for minimum input voltage

330uF

DC link

capacitor

20ms

Holdup time

24V-8A192W400Vdcfs=100kHzLCD TV

Output voltage

(Rated current)

Rated output

powerInput voltage

Switching

frequencyApplication

max 400inV V=

192209

0.92o

in

ff

PP W

E= = =

3min 2 2

. 6

2 2 209 20 10400 367

330 10

i n H U in O PFC

in

P TV V V

C

= = =


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[STEP-2] Determine the transformer turns ratio (n=Np/NS1, NS1=NS2) It is typical to set duty cycle losses as 5~10%

Considering margin on the maximum duty cycle of the PWM controller (50%), the

worst-case maximum duty cycle to calculate the transformer turns ratio is chosen

as 42%.

max 2 2 6( ) 0.09 400 10 1043

16 16 209Loss in S

lk

in

D V TL H

P

= = =

1 2 max 2

160.09

( )

in lk Loss L L

in S

P LD D D

V T

= + =

min 2minmax maxmax max

2 6 3

( (1 )) 4( )(1 )

( ) ( )

(367 0.42 (1 0.42)) 4(24 1.2) 8 43 10 100 10367 0.42 (1 0.42)

(24 1.2) ( )

6.2

in o F o lk sin

o F o F

o F

V D D V V I L f V D Dn

V V V V

V V

+ = +

+ + +

= ++ +

=

24


[STEP-3] Calculate the nominal duty cycle ratio for maximum input voltage

and full load condition

22 2(1 )( ) ( ) o lko F inS

I LV V V D D

n n T+ =

6

max max 6

( ) 2 6.2 25.2 2 8 43 101 1 4[ ] 1 1 4[ ]2 2 400 6.2 400 10 10

0.342 2

o F o lk

in in S

nom

n V V I L

V nV T D

+ + + = = =


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25


[STEP-4] Output Inductor design

Setting 20% of output current as current ripple,

(1 )( )

2[ ]

(1 )

ino F

O lkL S

o in

V DV V

I LnI DTL n V D

=

66

(1 )( )

2[ ]

(1 )

400 (1 0.34)( 25.2)

2 8 43 106.2 [0.34 10 10 ] 32.38 0.2 6.2 400 (1 0.34)

ino F

O lko S

L in

V DV V

I LnL DTI n V D

H

=

= =

8.82

pk LL o

II I A

= +

26


[STEP-5] Determine the magnetizing inductance considering ZVS condition

for maximum input voltage condition (Coss=150pF)

To guarantee ZVS from full load to 20% load

2 2

max 6

12

6

(1 )[ ] 2 [(1 ) ]

2

(1 ) 400 (1 0.28) 0.28 10 10654

2 2 150 10 8 0.22[ (1 ) 2 ] 2[ (1 0.28) 400 2 0.28]

43 10 6.2

o in S lk M oss in

m

in Sm

oss oin

lk

I V D DTL I C D V

n L

V D DT L H

C ID V D

L n

< > + >

< = =

6

max max 6

@20%

( ) 2 6.2 25.2 2 (8 0.2) 43 101 1 4[ ] 1 1 4[ ]2 2 400 6.2 400 10 10

0.282 2

o F o lk

in in S

n V V I L

V nV T D

+ + + = = =

determine Lm=630H


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27


[STEP-6] Design the transformer

Magnetizing current can reach pulse-by-pulse current limit during the transient. Thus,

Bmax=0.15T is used to guarantee non-saturation of the transformer during transient

(EER3542, Ae=109mm2).

Then, Np=50 turns and Ns=8 turns

The maximum flux density in the worst case scenario will be checked in STEP-8

after the current limit level is determined.

max

.

(1 ) 8(1 2 ) (1 2 0) 1.29

2 6.2

in S oM pk

m

V D D T I I D A

L n

= + = =

max 6min

6

max

630 10 1.2949.7

109 10 0.15

m Mp

e

L IN turns

A B

= = =

Short one of thesecondary

windings

45H 10%18Leakage

100kHz, 1V630H 5%18Inductance

Test CondictionsSpec.Pin

28


[STEP-7] DC blocking capacitor selection

Voltage ripple of the DC blocking capacitor should be 20~30V (10~20% of VCB)

Too large a capacitor results in slow dynamic response

0

1 1[ (1 2 )]

SDT

o oCB p

B B

I IV i dt D

C C n n = +

0

1 1[ (1 2 )] 30

SDT

o op nom

B B

I Ii dt D V

C C n n= + +

> + = : Select CB=220nF

Voltage rating: more than 400V

Current rating: 1.27A

2 2 2 2

0 0 3 3 4 4 7 7( ) ( ) (1 )3 3

rms P P P P P P P P p

I I I I I I I II D D

+ + + += +


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[STEP-8] Current sensing resistor selection

6

6

(1 )(2 2 )

2

8 400 0.34 (1 0.34) 10 10(2 2 0.34) 2.41

6.2 2 630 10

pk o in nom nom S p nom

m

I V D D TI D

n L

A

= +

= + =

Since Vth=0.6V, Select Rsense=0.2 ohms

Then, the pulse-by-pulse current limit =3A

The transformer maximum flux density in the worst case scenario is

6

max min 6

630 3100.35

109 10 50

worst m L IM

e p

L IT

A N

= = =

30


[STEP-9] Choose the rectifier diode

1

2D inV V D

n=

2

2(1 )D inV V D

n=

Considering the worst case of D=50%,

Considering the worst case of D=0%,

1

2400 0.5 64

6.2DV V= =

2

2400 1 128

6.2DV V= =

Considering the voltage spike, 100V and 200V diodes are selected for D1

and D2, respectively


16/19

31

Design Tips

IP

Ids1

Ids1

1SLO

p

I

2SLO

p

NI

N1 2S SN>

0.5D

Asymmetric Half Bridge (AHB) Converters - By Fairchild

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