#04-2020-1000-214 CSCI 150

Jetic GūColumbia CollegeThis assignment is due on 21 March. 2020Please remember to write your name and student number.Please submit a single PDF for each assignment. Handwritten submissions and proprietary formats (e.g. Pages or MS Word) will not be accepted. The Lab portion must be submitted separately.

Assignment 4 Answer1. , and waveforms, one latch and two flip-flops are shown in the following figure. For the latch

and the flip-flops, carefully sketch the output waveform, , obtained in response to the input waveforms.

Assume that the propagation delay of the storage elements is negligible. Initially, all storage elements

store 0.

…2. A sequential circuit has three D flip-flops A, B, and C, and one input X. The circuit is described by the fol-

lowing input equations:

A. Derive the state table for the circuit.

Clock S RQi

SEQUENTIAL CIRCUITS

7. *A sequential circuit has three D flip-flops A, B, and C, and one input X. Thecircuit is described by the following input equations:

!

!

!

(a) Derive the state table for the circuit.(b) Draw two state diagrams, one for X ! 0 and the other for X ! 1.

8. A sequential circuit has one flip-flop Q, two inputs X and Y, and one outputS. The circuit consists of a D flip-flop with S as its output and logicimplementing the function

D = X ! Y ! S

with D as the input to the D flip-flop. Derive the state table and statediagram of the sequential circuit.

Q1

Q3

Q2

R

C

S

SR

Triggered SR

S

C

Triggered SR

S

R

C

S

R

R

FIGURE 38Waveforms and Storage Element for Problem 5

DA BC BC"( )X BC B C"( )X"

DB A

DC B

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DA = (BC + BC )X + (BC + B C )XDB = ADC = B

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B. Draw two state diagrams, one for and the other for .

X=0

X=1

3. Starting from state 00 in the following state diagram, determine the state transitions and output sequence

that will be generated when an input sequence of 10011011110 is applied.

Present State Input Next State

A B C X A B C

0 0 0 0 1 0 0

0 0 0 1 0 0 0

0 0 1 0 0 0 0

0 0 1 1 1 0 0

0 1 0 0 0 0 1

0 1 0 1 1 0 1

0 1 1 0 1 0 1

0 1 1 1 0 0 1

1 0 0 0 1 1 0

1 0 0 1 0 1 0

1 0 1 0 0 1 0

1 0 1 1 1 1 0

1 1 0 0 0 1 1

X = 0 X = 1

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01/0 -> 00/1 -> 00/0 -> 01/0 -> 11/0 -> 00/1 -> 01/0 -> 11/0 -> 10/0 -> 10/0 -> 00/14. A Universal Serial Bus (USB) communication link requires a circuit that produces the sequence 00000001.

You are to design a synchronous sequential circuit that starts producing this sequence for input . Once the sequence starts, it completes. If , during the last output in the sequence, the sequence repeats. Otherwise, if , the output remains constant at .

1. Draw the state diagram for the circuit.

2. Find the state table and make a state assignment.

Solution not unique*3. Design the circuit using flip-flops and logic gates. A reset should be included to place the circuit in

the appropriate initial state at which is examined to determine if the sequence of constant 1s is to be produced.

SEQUENTIAL CIRCUITS

State Diagram

The information available in a state table may be represented graphically in the formof a state diagram. A state is represented by a circle, and transitions between statesare indicated by directed lines connecting the circles. Examples of state diagrams aregiven in Figure 17. Figure 17(a) shows the state diagram for the sequential circuit inFigure 15 and its state table in Table 1. The state diagram provides the same informa-tion as the state table and is obtained directly from it. The binary number inside eachcircle identifies the state of the flip-flops. For Mealy model circuits, the directed linesare labeled with two binary numbers separated by a slash. The input value during thepresent state precedes the slash, and the value following the slash gives the outputvalue during the present state with the given input applied. For example, the directedline from state 00 to state 01 is labeled 1/0, meaning that when the sequential circuitis in the present state 00 and the input is 1, the output is 0. After the next clock tran-sition, the circuit goes to the next state, 01. If the input changes to 0, then the outputbecomes 1, but if the input remains at 1, the output stays at 0. This information isobtained from the state diagram along the two directed lines emanating from the cir-cle with state 01. A directed line connecting a circle with itself indicates that nochange of state occurs.

The state diagram of Figure 17(b) is for the sequential circuit of Figure 16.Here, only one flip-flop with two states is needed. There are two binary inputs, andthe output depends only on the state of the flip-flop. For such a Moore model circuit,the slash on the directed lines is not included, since the outputs depend only on thestate and not on the input values. Instead, the output is included under a slash belowthe state in a circle. There are two input conditions for each state transition in thediagram, and they are separated by a comma. When there are two input variables,each state may have up to four directed lines coming out of the corresponding circle,depending upon the number of states and the next state for each binary combinationof the input values.

There is no difference between a state table and a state diagram, except fortheir manner of representation. The state table is easier to derive from a givenlogic diagram and input equations. The state diagram follows directly from the

(a)

0/0 1/0

0/1

0/1 0/1

1/01/0

1/0

00 01

10 11

(b)

00, 11

01, 10

01, 10

00, 110/0 1/1

FIGURE 17State Diagrams

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E = 1E = 1

E = 0 1Problem Solutions – Chapter 4

13

4-20.

Present state Next State For Input Output

D2D1D0 E=0 E=1 Z

000 001 010 011 100 101 110 111

001 010 011 100 101 110 111 111

001 010 011 100 101 110 111 000

0 0 0 0 0 0 0 1

The state assignment could be different. E. g., state 7 could be 000 with state 0 001. This would permit use of R inputs on the D flip-flops for RESET.

0/0 7/16/04/03/02/01/0 5/0

E=0

E=1

Present stateNext StateFor Input Output

D2D1D0 E=0 E=1 Z

000001010011100101110111

001010011100101110111111

001010011100101110111000

00000001

CLK

Z

E

The state assignment could be diff erent.E. g., state 7 could be 000 with state 0001. This would permit use of R inputson the D f lip-f lops f or RESET.

D0

D1

D2

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

Problem Solutions – Chapter 4

13

4-20.

Present state Next State For Input Output

D2D1D0 E=0 E=1 Z

000 001 010 011 100 101 110 111

001 010 011 100 101 110 111 111

001 010 011 100 101 110 111 000

0 0 0 0 0 0 0 1

The state assignment could be different. E. g., state 7 could be 000 with state 0 001. This would permit use of R inputs on the D flip-flops for RESET.

0/0 7/16/04/03/02/01/0 5/0

E=0

E=1

Present stateNext StateFor Input Output

D2D1D0 E=0 E=1 Z

000001010011100101110111

001010011100101110111111

001010011100101110111000

00000001

CLK

Z

E

The state assignment could be diff erent.E. g., state 7 could be 000 with state 0001. This would permit use of R inputson the D f lip-f lops f or RESET.

D0

D1

D2

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

DE

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Solution not unique*5. A sequential circuit has two flip-flops and , one input , and one output . The state diagram is shown

in the following figure. Design the circuit with flip-flops using a 1-hot state assignment.

Problem Solutions – Chapter 4

13

4-20.

Present state Next State For Input Output

D2D1D0 E=0 E=1 Z

000 001 010 011 100 101 110 111

001 010 011 100 101 110 111 111

001 010 011 100 101 110 111 000

0 0 0 0 0 0 0 1

The state assignment could be different. E. g., state 7 could be 000 with state 0 001. This would permit use of R inputs on the D flip-flops for RESET.

0/0 7/16/04/03/02/01/0 5/0

E=0

E=1

Present stateNext StateFor Input Output

D2D1D0 E=0 E=1 Z

000001010011100101110111

001010011100101110111111

001010011100101110111000

00000001

CLK

Z

E

The state assignment could be diff erent.E. g., state 7 could be 000 with state 0001. This would permit use of R inputson the D f lip-f lops f or RESET.

D0

D1

D2

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

A B X YD

SEQUENTIAL CIRCUITS

27. *A set-dominant master–slave flip-flop has set and reset inputs. It differsfrom a conventional master-slave SR flip-flop in that, when both S and R areequal to 1, the flip-flop is set. (a) Obtain the state table of the set-dominant flip-flop. (b) Find the state diagram for the set-dominant flip-flop.(c) Design the set-dominant flip-flop by using an SR flip-flop and logic gates

(including inverters).

28. +The state table for a 3-bit twisted ring counter is given in Table 16. Thiscircuit has no inputs, and its outputs are the uncomplemented outputs ofthe flip-flops. Since it has no inputs, it simply goes from state to statewhenever a clock pulse occurs. It has an asynchronous reset that initializes itto state 000.(a) Design the circuit using D flip-flops and assuming that the unspecified

next states are don’t-care conditions. (b) Add the necessary logic to the circuit to initialize it to state 000 on

power-up master reset.(c) In the subsection “Designing with Unused States” of Section 5, three

techniques for dealing with situations in which a circuit accidentally enters an unused state are discussed. If the circuit you designed in parts (a) and (b) is used in a child’s toy, which of the three techniques given would you apply? Justify your decision.

(d) Based on your decision in part (c), redesign the circuit if necessary.(e) Repeat part (c) for the case in which the circuit is used to control engines

on a commercial airliner. Justify your decision.(f) Repeat part (d) based on your decision in part (e).

0

1

00/10

1

01/0

0

11/0

0

10/0

1

1

FIGURE 44State Diagram for Problem 26

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6. The following figure is the logic simulation of an Master–Slave flip-flop. Obtain a similar timing diagram for a positive-edge-triggered JK flip-flop during four clock pulses. Show the timing signals for , , , , and . Assume that initially the output is equal to 1, with and for the first pulse. Then, for successive pulses, goes to 1, followed by going to 0 and then going back to 0. Assume that each

input changes near the negative edge of the pulse.

Problem Solutions – Chapter 4

17

4-27.* To use a one-hot assignment, the two flip-flops A and B need to be replaced with four flip-flops Y4, Y3, Y2. Y1.

Present State Input Next State Output

A B Y4 Y3 Y2 Y1 X A’ B” Y4’Y3’Y2’Y1 Z

0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0

0 1 0 1 0 1 0 1

0 1 0 0 0 1 1 0 1 1 1 0 1 1 0 0

0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1

1 1 0 0 0 0 0 0

No Reset State Specified. D1 Y1 X·Y1 X·Y4D2 Y2 X·Y1 X·Y2D3 Y3 X·Y2 X·Y3D4 Y4 X·Y3 X·Y4

c �c �c �c �

To use a one-hot assignment, the two flip-flops A and Bneed to be replaced with f our f lip-f lops Y4, Y3, Y2. Y1.

Present State Input Next State Output

A B Y4 Y3 Y2 Y1 X A’ B" Y4’Y3’Y2’Y1 Z

0 00 00 10 11 01 01 11 1

0 0 0 10 0 0 10 0 1 00 0 1 00 1 0 00 1 0 01 0 0 01 0 0 0

0101010

1

0 10 00 11 01 11 01 10 0

0 0 1 00 0 0 10 0 1 00 1 0 01 0 0 00 1 0 01 0 0 00 0 0 1

11000000

No Reset State Specif ied.

D1 = Y1’= X·Y1 + X·Y4D2 = Y2’ = X·Y1 + X·Y2D3 = Y3’ = X·Y2 + X·Y3D4 = Y4’ = X·Y3 + X·Y4

D

C

D

C

X

Y1

Y2

Y

Clock

D

C

D

C

Y3

Y4

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

SRC J K Y

Q Q J = 0 K = 1J K J

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……

SEQUENTIAL CIRCUITS

Note that these changes are delayed from the pulse changes by gate delays. Also,the external inputs S and R can change anytime after the clock pulse goes throughits negative transition. This is because, as the C input reaches 0, the master is dis-abled, and S and R have no effect until the next clock pulse.

The next sequence of signal changes illustrates the “1s catching” behavior ofthe SR master–slave flip-flop. A narrow pulse to 1 occurs on S at the beginning ofa clock pulse. The master latch responds to the 1 on S by changing Y to 1. Then Sgoes to 0 and a narrow 1 pulse occurs on R. The master latch responds to the 1 onR by changing Y back to 0. Since there are no further 1 values on S or R, the mas-ter continues to store 0, which is copied to the slave latch, changing Q to 0, inresponse to the clock’s change to 0. Thus, the master latch “caught” both the 1 onS and the 1 on R. Since the 1 on R was caught last, the output Q remained at 0. Ingeneral, the “correct” response is assumed to be the response to the input valueswhen the clock goes to 0. So, in this case, the response happens to be correct,although more by accident with the changing values in the master.

For the next clock pulse, a narrow 1 pulse occurs on S, setting the masteroutput Y to 1. The clock then goes to 0 and the value 1 is transferred to the slavelatch and appears on Q. In this case, the correct value on Q should be 0, since Qwas 0 before the clock pulse and both S and R are 0 just before the clock goes to0. Since Q equals 1, due to “1s catching” on S, the flip-flop is in the wrong state.

For the final clock pulse of interest, both S and R become 1 before the clockgoes to 0. This applies the invalid combination to the master latch, making both Yand equal to 1. When the clock changes to 0, the latch within the mastersees its inputs change from (0, 0) to (1, 1), causing the master latch to enter anunknown state, which is immediately transferred to the inputs of the slave,which also enters an unknown state. This demonstrates that S = 1, R = 1 is aninvalid input combination for the SR master–slave flip-flop.

Now consider a sequential system containing many master–slave flip-flops,with the outputs of some flip-flops going to inputs of other flip-flops. Assume thatthe clock pulses to all of the flip-flops are synchronized and occur at the sametime. At the beginning of each clock pulse, some of the masters change states, but

0 50 ns 100 ns 150 ns 200 ns

C

S

R

Y

Q

FIGURE 10Logic Simulation of an SR Master–Slave Flip-Flop

Y SR

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Lab 3You must complete the following assignment and submit a PDF of instructions enough to replicate your re-sults, and required documentation. You will also need to upload LogicWork circuit design files as specified, and your own library file. Then upload a single ZIP file to student portal. If you don't have the software, draw the circuit design only and include it in the PDF.

1. Save the library and circuit files we created in class containing the following designs in the final ZIP file:

(1) latch (circuit1-1.cct);

(2) flip-flop (circuit1-2.cct);

(3) Implement , , (circuit1-3.cct);

(4) Draw the state table and diagram for (3).

2. Draw the state diagram of rotator, write down the equations for each flip-flop, and complete the imple-

mentation (circuit2.cct).

Start state : original 4-bit, implement using binary switches

Input 0: for left rotation (output );

1: for right rotation (output );

Behaviour

Every CLK triggers a shift

State Diagram:

State Assignment and Equations:

Flip-flops , , , , initially

D

D

DA = X A + XY DB = X B + X A Z = X B

D

X3X2X1X0

YX2X1X0X3

X0X3X2X1

A B C D ABCD = X3X2X1X0

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If , at each time: , , ,

If , at each time: , , ,

Basically, is used as switch between 2 options for each flip-flops. This can be solved using a 2-to-

1 multiplexer for each flip-flop.

Circuit:

… I think at this point it should be simple enough.

3. Find a state-machine diagram that is equivalent to the following state diagram. Reduce the complexity of

the transition conditions as much as possible. Attempt to make outputs unconditional by changing Mealy

outputs to Moore outputs. Make a state assignment to your state-machine diagram and find an implemen-tation for the corresponding sequential circuit using flop-flops, AND gates, OR gates, and inverters.

(1) Draw the state-machine diagram.

(2) Write down the Flip-Flop Input Equations and Output Equations.

(3) Implement the circuit, save as circuit3.cct .

Y = 0 DA = B DB = C DC = D DD = A

Y = 1 DA = D DB = A DC = B DD = C

Y D

DA = (Y ⋅ B) + (Y ⋅ D)

DB = (Y ⋅ C ) + (Y ⋅ A)

DC = (Y ⋅ D) + (Y ⋅ B)

DD = (Y ⋅ A) + (Y ⋅ C )

DSEQUENTIAL CIRCUITS

to Moore outputs. Make a state assignment to your state-machine diagramand find an implementation for the corresponding sequential circuit using Dflop-flops, AND gates, OR gates, and inverters.

36. Verify that the transitions in the state-machine diagram in Figure 29 obeythe two transition conditions for state diagrams.

37. *You are to find the state-machine diagram for the following electronicvending-machine specification. The vending machine sells jawbreaker candy,one jawbreaker for 25¢. The machine accepts N (nickels = 5¢), D (dimes =10¢), and Q (quarters = 25¢). When the sum of the coins inserted insequence is 25¢ or more, the machine dispenses one jawbreaker by makingDJ equal to 1 and returns to its initial state. No change is returned DJ equals0 for all other states. If anything less than 25¢ is inserted and the CR (CoinReturn) pushbutton is pushed, then the coins deposited are returnedthrough the coin return slot by making RC equal to 1, after which themachine returns to its initial state. RC equals 0 in all other states. Use Mooreoutputs for your design.

38. Design the sequential circuit for the state-machine diagram from Problem37. You may either solve Problem 37 or find its solution on the textbookwebsite. Use a 1-hot state assignment, D flip-flops and AND gates, OR gates,and inverters.

39. You are to find the state-machine diagram for the following electronicvending-machine specification. The vending machine sells soda for $1.50 perbottle. The machine accepts only D ($1 bills) and Q (quarters = 25¢). Whenthe sum of money is greater than $1.50, i.e., two $1 bills, the machine returnschange in the coin return (two quarters). When $1.50 has been paid, themachine lights an LED to indicate that a soda flavor may be selected. Thechoices by pushbutton are C (Cola), L (Lemon soda), O (Orange soda), andR (Root Beer). When one pushbutton is pushed, the selected soda isdispensed and the machine returns to its initial state. One other feature isthat an LED comes on to warn the user that two quarters are not availablefor change, so if a second $1 bill is inserted, no change will be given. (a) Find the state-machine diagram for the soda vending machine as

specified.

ResetInput X, YOutput Z A B DC

01/1, 10/100/1, 10/0

10/0, 11/1

00/0, 01/000/1, 11/1

00/0,01/101/1, 11/010/0, 11/0

FIGURE 45State Diagram for Problem 35

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Problem Solutions – Chapter 4

4-33. a)

b) � �

�

A

B

D AB BY ABY

D AY

Z AB AB

4-34.

4-35.

0 1

0 1

0

1

0 1

0

1 0

2 0

3 1

1

Format is State

Output value

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© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved. This material is protected under all copyright laws as they currently exist. No portion of this material may be reproduced, in any form or by any means, without permission in writing from the publisher.

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