Assemler_lec

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Assembler Design

Transcript of Assemler_lec

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Assembler Design

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Role of Assembler

Source

ProgramAssembler

Object

Code

Loader

Executable Code

Linker

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Elements of Assembly Language Format of Statement

[label] <opcode> <operand>[,..<operand>..]

Label – symbolic name associated with memory word.

Opcode – m/c instruction or assembler directive or declaration.

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Operand – First operand (Register)

Second operand(Memory Word)

<symbolic name> [+<displacement>] [<Index Register>]

AREA

AREA + 5

AREA(4)

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Types of Assembly Statements IMPERATIVE STATEMENTS DECLARATION STATEMENTS ASSEMBLER DIRECTIVES

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Imperative Statements Memory Reference/ Transfer Control Arithmetic Logical Flow Control

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Imperative StatementsSTOP 00 READ 09

ADD 01 PRINT 10

SUB 02

MULT 03

MOVER 04

MOVEM 05

COMP 06

BC 07

DIV 08

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EXAMPLES : MOVER BREG , ONE MOVEM BREG, TERM

NEXT MULT CREG,TERM

COMP CREG, N BC LE, NEXT

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DECLARATION STATEMENTS DS – Reserves storage space DC – Declares constant & reserves memory Formats

DS: [label] DS <constant>

e.g. A DS 1

A DS 10

DC: [label] DC ‘<value>’

e.g. T DC ‘5’

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Literals vs. DC vs. Immediate OperandsLiterals Constants Immediate

OperandsADD AREG, ‘=5’ ADD AREG,FIVE

……..……..FIVE DC ‘5’

ADD AREG, 5

Value can’t be changed

Value can be changed

No architectural provision is needed

Architectural provision is needed

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Assembler Directive Statements Instructs Assembler No m/c equivalent is generated START, END, ORIGIN, LTORG, EQU

START

Syntax: START <constant>

e.g. START 200

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END

Syntax: END [<operand spec>]

e.g. END

END 205

ADVANCED ASSEMBLER DIRECTIVES

ORIGIN

Syntax: ORIGIN < address spec>

<address spec> - constant or operand

Set the value of LC to address

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EQU

Syntax: <symbol> EQU <Address Spec>

LTORG Assigns memory locations to various literals. Literal Pool BY default assembler places literals after the

END statement.

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???? START 100 L1 MOVER AREG, =’6’ BC LE, NEXT ORIGIN L2 C DC ‘5’ N DS 1 END L2

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Language Processor Analysis Phase Synthesis Phase

ASSEMBLER: General Design Specification Phases Data Structures Translation Schemes

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General Design Specifications

Specify the Problem & identify information

Specify data structures Define the format of the data structures

required Specify the algorithm to be used

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Translation Scheme Single Pass Translation Two Pass Translation

Single Pass Assembler Two Pass Assembler

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Two Pass Assembler

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PASS 1 Isolate label, mnemonic opcodes, operands Uses OPTAB Symbol Table Literal Table Location Counter Processing Construct IC

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PASS II Uses OPTAB, SYMTAB, LITTAB Generate machine instructions of the

statements.

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Pass 1 Pass 2IR Object programSource program

OPTAB

SYMTABLC

LITTAB

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Data Structures Used Symbol Table (SYMTAB) Literal Table (LITTAB) Operation Code Table (OPTAB,POT,MOT) Location Counter (LC) Pool table (POOLTAB)

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OPTABMnemonic

OpcodeClass Mnemonic Info

MOVER IS (04,1)

DS DL R#7

START AD R#1

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Symbol Table (SYMTAB)SYMBOL LOCATION LENGTH

A 101 3

L1 104 1

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Literal Table ( LITTAB)

Literal Address

1 =‘6’

2 =‘1’

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POOLTAB

LITERAL NO.

#1

#2

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FLOW CHART & ALGORITHM

PASS - I

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