Aspects of Digital Electronics Chemistry 838 · Chemistry 838 Aspects of Digital Electronics...

November 4, 2004 - 1 - Version 1.1

Aspects of Digital Electronics

Chemistry 838

Thomas V. Atkinson, Ph.D. Senior Academic Specialist Department of Chemistry Michigan State University East Lansing, MI 48824

Table of Contents TABLE OF CONTENTS ............................................................................................................. 1

TABLE OF TABLES.................................................................................................................... 2

TABLE OF FIGURES.................................................................................................................. 3

1. INTRODUCTION............................................................................................................... 4

2. GENERIC GATES AND FLIP FLOPS............................................................................ 4 2.1. GATES ............................................................................................................................. 4 2.2. FLIP FLOPS ...................................................................................................................... 6

3. BINARY VARIABLES ...................................................................................................... 7

4. GATES................................................................................................................................. 8 4.1. LOGIC GATES .................................................................................................................. 8 4.2. GATE SYMBOLS............................................................................................................... 9 4.3. GATING SIGNALS .......................................................................................................... 10

4.3.1. And ............................................................................................................................ 10 4.3.2. Or .............................................................................................................................. 10 4.3.3. Nand.......................................................................................................................... 11 4.3.4. Nor ............................................................................................................................ 11 4.3.5. Time Varying Example.............................................................................................. 12

4.4. PHYSICAL IMPLEMENTATIONS....................................................................................... 12 4.4.1. And ............................................................................................................................ 14 4.4.2. Or .............................................................................................................................. 14 4.4.3. Inverse....................................................................................................................... 15

4.5. DIGITAL CIRCUIT ANALYSI ........................................................................................... 16

5. LATCHES ......................................................................................................................... 16 5.1. SIMPLE LATCH .............................................................................................................. 16

Chemistry 838 Aspects of Digital Electronics Table of Tables


5.2. GATED LATCH............................................................................................................... 18 5.3. GATED LATCH WITH PRESET......................................................................................... 19 5.4. DATA LATCH................................................................................................................. 20 5.5. SIMPLE FLIP FLOP ......................................................................................................... 20 5.6. JK FLIP FLOP.................................................................................................................. 21

6. COUNTERS ...................................................................................................................... 22 6.1. BINARY ......................................................................................................................... 22

6.1.1. Two Stages ................................................................................................................ 22 6.1.2. Three Stages.............................................................................................................. 23 6.1.3. n Stages ..................................................................................................................... 25

6.2. VARIABLE MODULUS .................................................................................................... 26 6.2.1. Modulo 0 ...................................................................................................................... 28 6.2.2. Modulo 1 ...................................................................................................................... 28 6.2.3. Modulo 2 ...................................................................................................................... 29 6.2.4. Modulo 3 ...................................................................................................................... 29 6.2.5. Modulo 4 ...................................................................................................................... 30 6.2.6. Modulo 5 ...................................................................................................................... 30 6.2.7. Modulo 6 ...................................................................................................................... 31 6.2.8. Modulo 7 ...................................................................................................................... 32 6.2.9. Modulo 8 ...................................................................................................................... 33 6.2.10. Timing Example (Modulo 5) ...................................................................................... 34

6.3. BINARY COUNTER WITH PRESET ................................................................................... 35 6.4. VARIABLE MODULUS COUNTER.................................................................................... 36 6.5. UP/DOWN COUNTER ..................................................................................................... 39

7. REVISION HISTORY ..................................................................................................... 41

Table of Tables TABLE 1 - GENERIC GATE, SWITCH, LATCH - DEFINITIONS............................................................................................5 TABLE 2 - TRI-STATE GATE - TABLE OF STATES ............................................................................................................5 TABLE 3 - DEFINING BEHAVIOR OF FLIP FLOP ...............................................................................................................6 TABLE 4 - FLIP FLOP - SET AND CLEAR ..........................................................................................................................7 TABLE 5 - BINARY VARIABLES - TABLE OF STATES .......................................................................................................8 TABLE 6 - ALTERNATIVE REPRESENTATION...................................................................................................................8 TABLE 7 - ALTERNATIVE REPRESENTATION 2 ................................................................................................................8 TABLE 8 - LOGIC VARIABLES AND OPERATORS - TRUTH TABLES ..................................................................................8 TABLE 9 - XOR AND EQUALITY GATES...........................................................................................................................9 TABLE 10 - AND CIRCUIT - TABLE OF STATES..............................................................................................................14 TABLE 11 - OR CIRCUIT - TABLE OF STATES ................................................................................................................14 TABLE 12 - INVERSE CIRCUIT - TABLE OF STATES .......................................................................................................15 TABLE 13 - LOGIC FAMILIES ........................................................................................................................................15 TABLE 14 - 4 NAND CIRCUIT - TABLE OF STATES.........................................................................................................16 TABLE 15 SIMPLE LATCH - TABLE OF STATES..............................................................................................................17 TABLE 16 - GATED LATCH - TABLE OF STATES............................................................................................................18 TABLE 17 - GATED LATCH WITH PRESET – TABLE OF STATES .....................................................................................19 TABLE 18 - D LATCH - TABLE OF STATES ....................................................................................................................20 TABLE 19 – JK FLIP FLOP – TABLE OF STATES .............................................................................................................21 TABLE 20 - 2 STAGE COUNTER TABLE OF STATES .......................................................................................................23 TABLE 21 - 3 STAGE COUNTER TABLE OF STATES .......................................................................................................24

Chemistry 838 Aspects of Digital Electronics Table of Figures


TABLE 22 - POWERS OF 2 .............................................................................................................................................25 TABLE 23 - SUMMARY OF VARIABLE MODULUS CONFIGURATIONS.............................................................................27 TABLE 24 – 4 STAGE COUNTER WITH OVERFLOW - STATE TABLE ...............................................................................36 TABLE 25 – MODULO 5 COUNTER, PRELOAD VALUE = 11 ...........................................................................................37 TABLE 26 –MODULO 9 COUNTER, PRELOAD VALUE = 7 ..............................................................................................38 TABLE 27 - - 2-BIT MULTIPLEXER - TABLE OF STATES ................................................................................................40 TABLE 28 - - 2-BIT MULTIPLEXER - TABLE OF STATES (ABBREVIATED) ......................................................................40

Table of Figures FIGURE 1 - GENERIC GATE, SWITCH, AND LATCH ..........................................................................................................4 FIGURE 2 - TRI-STATE GATE ..........................................................................................................................................5 FIGURE 3 - GENERIC FLIP FLOP ......................................................................................................................................6 FIGURE 4 - EXAMPLE TIME COURSE...............................................................................................................................6 FIGURE 5 - FLIP FLOP - TIMING DIAGRAM......................................................................................................................7 FIGURE 6 - INVERTER .....................................................................................................................................................9 FIGURE 7 - ONE APPROACH TO IMPLEMENTING AN INVERTER .......................................................................................9 FIGURE 8 - AND GATE....................................................................................................................................................9 FIGURE 9 - OR GATE ......................................................................................................................................................9 FIGURE 10 - NAND GATE................................................................................................................................................9 FIGURE 11 - NOR GATE ..................................................................................................................................................9 FIGURE 12 - NOR GATE (EQUIVALENT) ........................................................................................................................10 FIGURE 13 - NAND GATE (EQUIVALENT) .....................................................................................................................10 FIGURE 14 - EXCLUSIVE OR GATE - XOR .....................................................................................................................10 FIGURE 15 - EQUALITY GATE.......................................................................................................................................10 FIGURE 16 - GATED SIGNAL EXAMPLE.........................................................................................................................12 FIGURE 17 - BINARY VARIABLES - PHYSICAL IMPLEMENTATION .................................................................................13 FIGURE 18 - AND CIRCUIT............................................................................................................................................14 FIGURE 19 - OR CIRCUIT ..............................................................................................................................................14 FIGURE 20 - INVERSE CIRCUIT......................................................................................................................................15 FIGURE 21 - ANALYSIS OF 4 NAND CIRCUIT.................................................................................................................16 FIGURE 22 - SIMPLE LATCH..........................................................................................................................................16 FIGURE 23 - GATED LATCH ..........................................................................................................................................18 FIGURE 24 - GATED LATCH - SYMBOL .........................................................................................................................18 FIGURE 25 - GATED LATCH WITH PRESET ....................................................................................................................19 FIGURE 26 - GATED LATCH WITH PRESET - SYMBOL....................................................................................................19 FIGURE 27 - D LATCH ..................................................................................................................................................20 FIGURE 28 - SIMPLE FLIP FLOP.....................................................................................................................................20 FIGURE 29 - RACE CONDITION .....................................................................................................................................21 FIGURE 30 – TWO COUPLED FLIP FLOPS ......................................................................................................................22 FIGURE 31 - TWO COUPLED FLIP FLOPS - TIMING DIAGRAM........................................................................................22 FIGURE 32 - THREE STAGE RIPPLE COUNTER...............................................................................................................23 FIGURE 33 - VARIABLE MODULUS COUNTER ...............................................................................................................27 FIGURE 34 - MODULO 5 COUNTER TIMING...................................................................................................................34 FIGURE 35 - 4 PULSE TRAINS........................................................................................................................................34 FIGURE 36 - BINARY COUNTER WITH PRELOAD ...........................................................................................................35 FIGURE 37 – MODULO-5 COUNTER TIMING..................................................................................................................37 FIGURE 38 – MODULO-9 COUNTER TIMING..................................................................................................................39 FIGURE 39 – 2-BIT DIGITAL MULTIPLEXER..................................................................................................................39 FIGURE 40 - SIMPLE UP/DOWN COUNTER ....................................................................................................................40

Chemistry 838 Aspects of Digital Electronics Introduction


1. Introduction Digital electronics is the basis of all modern computing and digital instrumentation including the digital watches that many people wear. This document provides an introduction to the subject and is the transcription of my lecture notes as they have evolved over the past three plus decades.

2. Generic Gates and Flip Flops 2.1. Gates Figure 1 and Table 1 define three generic devices, which may be either analog or digital devices. The devices are three port devices with two inputs, e.g. ein and a control signal eGC, eSC, or eLC, and one output, eout. The devices have two states. The control signal determines in which of the two states the device is at a particular time.

GateSwitchLatch_01.cdr 7-Oct-2004

Gateein

eGC

eout Switchein

eSC

eout Latchein

eLC

eout

eSC

SwitchControl

Figure 1 - Generic Gate, Switch, and Latch

The gate nomenclature comes from the barnyard gate, i.e. when the gate is open, the animals can go through the gate; when the gate is closed then animals can not go through the gate. The latch is basically a camera, i.e. it captures a snapshot of the value of ein at the time of the transition of eLC and holds it for later inspection.

Chemistry 838 Aspects of Digital Electronics Generic Gates and Flip Flops


Table 1 - Generic Gate, Switch, Latch - Definitions

Device State Control Signal Behavior

Gate Open eGC = Open eout = ein

Closed eGC = Closed eout = constant ( also may be disconnected)

Switch Closed eSC = Closed eout = ein

Open eSC = Open eout = constant

Latch Follow eLC = Follow eout = ein

Latched eLC = Latch eout = ein (t =

Latch

Follow )

Figure 2 illustrates a derivative combination, the tri-state gate which has the characteristics shown in Table 2. This device derives its name from the fact that there are essentially three states: high, low, and disconnected. Such devices have great utility when constructing a “bus,” i.e. a “party line” or shared communication facility. The digital bus is discussed further in “Aspects of Computer Architecture.”

TriStateGate_01.cdr 10-Oct-2004

Gateein

eGC

Switch

eSC

eout

Figure 2 - Tri-State Gate

Table 2 - Tri-State Gate - Table of States

Switch Control Gate Control Behavior

eSC = Closed eGC = Open eout = ein

eSC = Closed eGC = Closed eout = constant

eSC = Open eGC = Open Device is disconnected from the following circuitry.

eSC = Open eGC = Closed Device is disconnected from the following circuitry.

These generic concepts have widespread application in both digital and analog electronics. The remainder of this document will explore how these devices are implemented and applied in the digital domain.

Chemistry 838 Aspects of Digital Electronics Generic Gates and Flip Flops


2.2. Flip Flops Figure 3 is the symbol used for the generic flip flop. The behavior of the device is shown in Table 3 and Figure 4

Clock

Set

Clear

Q

Q

FlipFlops_1.cdr 5-Oct-2004

Figure 3 - Generic Flip Flop

Clock

Time

1

0

FlipFlop_2.cdr 5-Oct-2004

t0 t1 t2 t3 t4 t5 t6

Figure 4 - Example Time Course

Table 3 - Defining Behavior of Flip Flop

Time Q Q

0 0 1

1 1 0

2 0 1

3 1 0

4 0 1

5 1 0

6 0 1

Actually, the transitions occur on a rising edge ( ) or a falling edge ( ) of the Clock signal depending on the implementation of the device.

The roles of the Set and Clear inputs are described in Table 4. Notice that the toggle behavior is only seen when neither Set nor Clear is asserted. The term asserted was chosen because some actual devices have these two input signals being asserted on a Hi, while other devices assert on a Lo.

Chemistry 838 Aspects of Digital Electronics Binary Variables


Table 4 - Flip Flop - Set and Clear

Results of Action Action

Q Q Action

Assert Set 1 0 Flip Flop is set

Assert Clear 0 1 Flip Flop is cleared

Assert neither Set or Clear Q Q Flip Flop is allowed to toggle

Assert both Set or Clear ? ? Undefined, not allowed

If Clock is a periodic signal, the behavior shown in Figure 5 occurs. Notice that ClockQ pp 2= or

2ff Clock

Q = . Thus, the flip flop is also called a “divide by 2” circuit. Don’t forget that this holds

only for periodic signals. FlipFlop_4.cdr 5-Oct-2004

Clock1

0

pClock

Q 1

0

pQ

1

0

pQ

Q Figure 5 - Flip Flop - Timing Diagram

3. Binary Variables Logic is a traditional subject found in philosophy and mathematics that deals with the manipulation of entities that can exist in only two forms or states. In traditional logic, the two forms are named “true” and “false.” Combinations of these entities can be created using the operations of logic. The combinations are in themselves members of the set of logical entities. Another naming convention uses “1” and “0.” With the advent of physical implementations of this subject during the 1940’s and 1950’s, an additional naming conventions of “High” and “Low” came into use to reflect the voltage levels used to represent the logical entities. The additional naming conventions “Hi” and “Lo,” and “Open” and “Closed” are also used.

The mathematics of entities that exist in only two states and the attendant operations is called Boolean Algebra.

Typically, the two state entities are called variables and are identified with names or strings of characters such as A, B, C, D, AA, BB, Clock, Apple, Clear, Set, Orange, xxyy, etc. Table 5

Chemistry 838 Aspects of Digital Electronics Gates


shows the conventions used in this document. In this example, the two possible values of the variable A, are labeled 0 and 1. Table 6 and Table 7 illustrate two analogous representations.

The concept of “inverse” is also included in Table 5 and Table 6 and Table 7. The inverse of a variable is defined as a new binary variable, identified with the symbol A for the original variable A, that is always in the opposite state. Any variable with the bar “⎯” over the name is the inverse of the original variable. The bar is a unary operator called “inverse,” “bar,” or “not.”

Table 5 - Binary Variables - Table of States

A A

0 1

1 0

Table 6 - Alternative Representation

A A

lo hi

hi lo

Table 7 - Alternative Representation 2

A A

F T

T F

4. Gates 4.1. Logic Gates The discussion of gates in digital electronics begins with a discussion of the operators of traditional logic. Table 8 defines two of the basic operators, “and” and “or,” of binary logic. The third basic operator is the “not” or “inverse” operator. A fourth operator, “xor,” will be introduced later. The behavior of these operators is based in the following four definitions.

The inverse of a logic variable is a logic variable that is always in the opposite state.

The “and” of any number of logic variables is a logic variable that is true only when all of the variables being combined are true.

The “or” of any number of logic variables is a logic variable that is true when any of the variables being combined are true.

The “exclusive or” (“xor”) of two logic variables is a logic variable that is true when one and only one variable is true.

Table 8 - Logic Variables and Operators - Truth Tables

B A B A A.AND.BBA •

A.OR.BBA +

B.AND.A

BA • B.OR.A

BA + A.AND.B

BA •

A.OR.B

BA +

0 0 1 1 0 0 1 1 1 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0



Table 9 shows the definition of the “exclusive or”, i.e. “xor”, and “equality” operations. These operators can be derived from the basic three operators, “and”, “or,” and “not.”

Table 9 - Xor and Equality Gates

B A BA⊕ BA⊕ 0 0 0 1

0 1 1 0

1 0 1 0

1 1 0 1

Notice that the two following are true.

BABA •=+

BABA +=• These are De Morgan Theorems and are examples of Boolean Algebra. This section contains the total basis of digital electronics and computing. Everything else can be derived from these basic principles.

4.2. Gate Symbols The following symbols are used to represent both the logic operations and the physical devices that implement the logic operations. When the symbols refer to physical devices remember that the real devices require connections to power and common. These connections will be understood and not included in the symbols.

Logic01c _AA

Figure 6 - Inverter

Logic01b

_M = AA

Figure 7 - One Approach to Implementing an Inverter

Logic01a

AB

M = A•B

Figure 8 - And Gate

Logic03a

AB

M = A+B

Figure 9 - Or Gate Logic01

AB

___M = A•B

AB

Figure 10 - Nand Gate

Logic03

AB

____M = A+B

Figure 11 - Nor Gate



Logic101

AB

_ _ ___M = A•B= A+B

Figure 12 - Nor Gate (Equivalent)

Logic102.cdr

AB

_ _ ___ M = A+B = A•B

Figure 13 - Nand Gate (Equivalent) Logic103.cdr

AB

M = A+B

Figure 14 - Exclusive Or Gate - Xor

Logic09

AB

M

Figure 15 - Equality Gate

4.3. Gating Signals These devices are commonly called “gates.” The motivation for this nomenclature can be seen in the following four examples where each of the basic gates is shown to have the gating behavior, i.e. one signal controls whether the other passes through the device or not.

4.3.1. And

Logic01a

AB

M = A•B

B A A.AND.B

BA •

0 0 0 0 1 0 1 0 0 1 1 1

Let B be the gate control: If B = 1, then A1ABA M =•=•= . Thus, the gate is OPEN, the signal A can pass through. If B = 0, then 00ABAM =•=•= Thus, the gate is CLOSED, the output is independent of the signal A.

4.3.2. Or



Logic03a

AB

M = A+B

B A A.OR.B

BA +

0 0 0 0 1 1 1 0 1 1 1 1

Let B be the gate control: If B = 1, then 11ABAM =+=+= Thus, the gate is CLOSED, the output is independent of the signal A. If B = 0, then A0ABAM =+=+= . Thus, the gate is OPEN, the signal A can pass through.

4.3.3. Nand

Logic01

AB

___M = A•B

AB

B A A.AND.B

BA •

0 0 1 0 1 1 1 0 1 1 1 0

Let B be the gate control: If B = 1, then A1ABAM =•=•= . Thus, the gate is OPEN, the signal A can pass through but the signal is inverted. If B = 0, then 1==•=•= 00ABAM . Thus, the gate is CLOSED, the output is independent of the signal A.

4.3.4. Nor

Logic03

AB

____M = A+B

B A A.OR.B

BA +

0 0 1 0 1 0 1 0 0 1 1 0

Let B be the gate control: If B = 1, then 0==+=+= 11ABAM Thus, the gate is CLOSED, the output is independent of the signal A.



If B = 0, then A0ABAM =+=+= . Thus, the gate is OPEN, the signal A can pass through but the signal is inverted.

4.3.5. Time Varying Example Figure 16 contains an example of gating a time varying signal. In this case, the Nor gate is being used to control the flow of the signal A. Input B is to be considered as the gate control. Notice that signal A is not periodic and was chosen to illustrate that arbitrary signals can be manipulated by the gate. The inverse of the signal A is passed through the gate during the period of time between t1 and t2, i.e. when the gate is open.

A

B

A+B

___A+B

1

1

0

0

1

0

GatedSignal.cdr 7-Oct-2004

t1 t2

1

0

Figure 16 - Gated Signal Example

4.4. Physical Implementations Physical devices can be built that implement the logic operations illustrated in Table 8 and Table 9. Below are the symbols for these devices. Each of the logic states is represented by a voltage range as illustrated in Figure 17. The voltages shown here are but an example, each logic family will have a definition of the ranges. Notice that there is a buffer region between the two states. This makes it easier to differentiate between signals that are “high” and signals that are “low.” In effect, this decreases the effect that noise has in the circuits. This is often called the source of the “digital advantage” over analog techniques.



Buffer Region

High

Low

HiHigh

LoHigh

LoLow

HiLow

5 volts

4 volts

1 volts

0 volts

DigitalAdvantage_1.cdr 9-Oct-2004

Figure 17 - Binary Variables - Physical Implementation

Below are three physical implementations of logic function. The implementations included in a particular family of logic will vary as the designers seek to optimize the figures of merit.



4.4.1. And PhysicalGates_01.cdr 7-Oct-2004

eout

R

+5 volts

C1

S1

SwitchControl

C2

S2

SwitchControl

Figure 18 - And Circuit

Table 10 - And Circuit - Table of States

S2 S1 C2 C1 eout M

Closed Closed 0 0 0 0

Closed Open 0 1 0 0

Open Closed 1 0 0 0

Open Open 1 1 5 volts 1

4.4.2. Or PhysicalGates_02.cdr 7-Oct-2004

eout

R

+5 volts

C1

S1

SwitchControl

C2

S2

SwitchControl

Figure 19 - Or Circuit

Table 11 - Or Circuit - Table of States

S2 S1 C2 C1 eout M

Open Open 0 0 0 0

Open Closed 0 1 5 volts 1

Closed Open 1 0 5 volts 1

Closed Closed 1 1 5 volts 1



4.4.3. Inverse PhysicalGates_03.cdr 7-Oct-2004

eout

R

+5 volts

C1

S1

SwitchControl

Figure 20 - Inverse Circuit

Table 12 - Inverse Circuit - Table of States

S1 C1 eout M

Open 0 5 volts 1

Closed 1 0 0

Table 13 - Logic Families

Name Full Name Contains

1940’s- 1950’s Vacuum tubes, R, C

RTL Resistor Transistor Logic Transistors, R, C

DTL Diode Transistor Logic Diodes, transistors, R, C

TTL Transistor Transistor Logic Transistors, R, C

ECL Emitter Coupled Logic Transistors, R, C

CMOS Complementary Metal Oxide Semiconductor Fet Logic Fet transistors, R, C

Figures of merit for Logic Families

Speed

Power Consumption

Fan out – How many gates the output of a gate can drive

Size

Cost

Chemistry 838 Aspects of Digital Electronics Latches


4.5. Digital Circuit Analysi

Logic100

A

1

2

3

4

B 0011 0011

0011

0101 01011011

1101

11010110

10110101

1110

1110

M = A+B

Figure 21 - Analysis of 4 Nand Circuit

Table 14 - 4 Nand Circuit - Table of States

Inputs Nand Outputs

B A 1 2 3 4

0 0 1 1 1 0

0 1 1 1 0 1

1 0 1 0 1 1

1 1 0 1 1 0

5. Latches 5.1. Simple Latch

Latch_01.cdr 7-Oct-2004

R

S M1

M2

Figure 22 - Simple Latch



The behavior of the device is derived by examining the six cases below. The notation, MiP, is used to indicate the value of Mi at the time of the transition from the previous state to the present.

S = 0, R = 1 10M0MSM 221 ==•=•= M1 is forced to be 1

0MM1MRM 1112 ==•=•= M2 is forced to be 0. Thus the device is Set.

S = 1, R = 0 10M0MRM 112 ==•=•= M2 is forced to be 1

0MM1MSM 2221 ==•=•= M1 is forced to be 0. Thus the device is Cleared.

S = 1, R = 1

M1P=0 M2P=1 1001M1MRM 1P1P2 ==•=•=•= M2 remains = M2P.

0MM1MSM 22P2P1 ===•=•= 1 M1 remains = M1P, thus latch is achieved.

M1P=1, M2P=0 0111M1MRM P1P12 ==•=•=•= M2 remains = M2P.

1MM1MSM 2P2P2P1 ===•=•= 0 M1 remains = M1P, thus latch is achieved.

S = 0, R = 0 10M0MRM 112 ==•=•= This is an undesirable situation.

1==•=•= 0M0MSM 221

Table 15 Simple Latch - Table of States

Set Reset Q Q

S R M1 M2 Comments

1 1 M1P 1PM Latched

1 0 0 1 Reset

0 1 1 0 Set

0 0 1 1 Undesirable

A disadvantage of this simple latch is that the outputs change whenever the inputs change.



5.2. Gated Latch Figure 23 shows an approach to separate the inputs from the latched device. When Load = 0, the inputs are uncoupled from the Simple Latch.


R

Load(Clock)

S1

2

3

4

M3 M1

M4

M2 Figure 23 - Gated Latch

Clock

S

R

Q

Q


Figure 24 - Gated Latch -

Symbol

Table 16 - Gated Latch - Table of States

Load Set Reset Q Q

S R M1 M2 Comment

0 X X M1P 1PM Latched

1 1 1 M1P 1PM Latch new

value

1 1 0 0 1 Reset

1 0 1 1 0 Set

1 0 0 1 1 Undesirable



5.3. Gated Latch with Preset


R

Load(Clock)

Preset

Clear

S M3

M1

M4 M2

Figure 25 - Gated Latch with Preset

Clock

Preset

Clear

S

R

Q

Q


Figure 26 - Gated Latch with Preset -

Symbol

Table 17 - Gated Latch with Preset – Table of States

Clear PreSet Load Set Reset Q Q

S R M3 M4 Comment

0 0 X X X 1 1 Undesirable

0 1 X X X 1 0 Reset

1 0 X X X 0 1 Set

1 1 0 X X 1 1 Latched

1 1 1 0 0 M1P 1PM Latch new

value

1 1 1 0 1 0 1 Reset

1 1 1 1 0 1 0 Set

1 1 1 1 1 1 1 Undesirable



5.4. Data Latch


X X _1 X

__ _M X3P

M X3P

_1 X

1 X

0 1Load

Data M3

M is the previous value of , i.e. that at the time of the last transition of LOAD from 1 to 0.

3P M3

M1

M4

M2

1

2

3

4

Figure 27 - D Latch

Table 18 - D Latch - Table of States

Load Data Q Q

S R M3 M4 Comment

0 X M1P 1PM Latched

1 0 X 0 Reset

1 1 1 1 Set

5.5. Simple Flip Flop The next step is to fashion a flip flop out of these real devices. This is attempted by cross coupling the inputs and outputs as in Figure 28. Assume the flip flop is set initially and Clock is not asserted. As soon as the clock is asserted, the inputs cause the outputs to change, which in turn presents new values to the inputs, which cause the outputs to change again. This oscillation keeps up as long as Clock is asserted. Furthermore, the state in which the circuit lands when the assertion of Clock is removed is indeterminate. Figure 29 illustrates the time course of this undesirable “race” condition.

Clock

S

R

Q

Q

SimpleFlipFLop_01.cdr 10-Oct-2004

Figure 28 - Simple Flip Flop



S 1

1

1

1

1

1 1Q

R 0

0

0

0

0

0 0

10

SimpleFlipFLop_02.cdr 10-Oct-2004

Q Figure 29 - Race Condition

5.6. jk Flip Flop


R R

Clock

Clock Clock

Master Slave

Sj

k

SQ Q M1

M2

Q Q


Clock

Master latchedSlave follows

Master followsSlave latched

Master latchedSlave follows

1 4

32

Table 19 – jk Flip Flop – Table of States

j k Q Q Comments

0 0 1 1 Latched

0 1 0 1 Reset

1 0 1 0 Set

1 1 Q t-1 Qt-1 Toggles

Chemistry 838 Aspects of Digital Electronics Counters


6. Counters The next topic is the examination of digital counters, which have utility in the measurement of time and frequency, computing and many modern instrumental techniques. For this topic, the generic flip flops will be used.

6.1. Binary

6.1.1. Two Stages

Returning to the discussion of the generic flip flop (see Section 2.2. Flip Flops), the next step is to combine two of the devices as shown in Figure 30.

ClockIn

Set

Clear

Q

A B

Q

Clock

Set

Clear

Q

Q


Figure 30 – Two Coupled Flip Flops

FlipFlop_6.cdr 5-Oct-2004

In1

0

pIn

QA

QB

1

1

0

0

1

0

pQA

pQB

QA

t0 t1 t2 t3 t4 t5 t7 t8t6

Figure 31 - Two Coupled Flip Flops - Timing Diagram

If In is a periodic signal and both flip flops are initially in the cleared state, then the circuit behaves as shown in Figure 31. Notice that the initial state is seen at t0, t4, and t8. Further, notice

that InQAQB ppp 42 == or 4

f2

ff InQA

QB == . Thus, this combination of the two flip flops is often

called a “divide by 4” circuit. Don’t forget that this holds only for periodic signals.



An alternative approach to describing this circuit is shown in Table 20 where the state of the device after each pulse on In is listed.

Table 20 - 2 Stage Counter Table of States

Values at ti

Decimal QB QA i

0 0 0 0

1 0 1 1

2 1 0 2

3 1 1 3

0 0 0 4

1 0 1 5

2 1 0 6

3 1 1 7

0 0 0 8

1 0 1 9

Notice that the counter “rolls over” every 4 counts and returns to the initial state.

6.1.2. Three Stages

Next, three flip flops will be cascaded as shown in Figure 32

ClockIn

Set

Clear

Q

A B C

Q

Clock Clock

Set Set

Clear Clear

Q Q

Q Q


Figure 32 - Three Stage Ripple Counter

The behavior of this circuit could be described with timing diagrams as was done for the case of one and two flip flops. However, as the number of stages increase, the approach embodied in Table 21 becomes more economical.



Thus, InQAQBQC pppp 842 === or 8f

4f

2f

f InQAQBQC ===

and this combination of the three flip flops is also called a “divide by 8” circuit. Don’t forget that this holds only for periodic signals.

Table 21 - 3 Stage Counter Table of States

Decimal QC QB QA After Pulse on In

0 0 0 0 0

1 0 0 1 1

2 0 1 0 2

3 0 1 1 3

4 1 0 0 4

5 1 0 1 5

6 1 1 0 6

7 1 1 1 7

0 0 0 0 8

1 0 0 1 9

2 0 1 0 10

3 0 1 1 11

4 1 0 0 12

5 1 0 1 13

6 1 1 0 14

7 1 1 1 15

0 0 0 0 16

1 0 0 1 17

Notice that the counter “rolls over” every 8 counts and returns to the initial state.



6.1.3. n Stages

Table 22 - Powers of 2

n DEC OCT HEX Common Name

0 1 1 1

1 2 2 2

2 4 4 4

3 8 10 8

4 16 20 10

5 32 40 20

6 64 100 40

7 128 200 80

8 256 400 100

9 512 1000 200

10 1024 2000 400 1K

11 2048 4000 800 2K

12 4096 10000 1000 4K

13 8192 20000 2000 8K

14 16384 40000 4000 16K

15 32768 100000 8000 32K

16 65536 200000 10000 64K

17 131072 400000 20000 128K

18 262144 1000000 40000 256K

19 524288 2000000 80000 512K

20 1048576 4000000 100000 1M or 1Meg

21 2097152 1000000 200000 2M or 2Meg

22 4194304 20000000 400000 4M or 4Meg

23 8388608 40000000 800000 8M or 8Meg

24 16777216 100000000 1000000 16M or 16Meg

25 33554432 200000000 2000000 32M or 32Meg

26 67108864 400000000 4000000 64M or 64Meg

27 134217728 1000000000 8000000 128M or 128Meg

28 268435456 2000000000 10000000 256M or 256Meg

29 536870912 4000000000 20000000 512M or 512Meg

30 1073741824 10000000000 40000000 1G or 1Gig

31 2147483648 20000000000 80000000 2G or 2Gig

32 4294967296 40000000000 100000000 4G or 4Gig

If the QA, QB, and QC are considered digits of a binary number, this circuit can be seen to be counting the number of pulses presented at In. This behavior can be generalized. Given n stages of flip flops cascaded as described above, the results is a counter that has 2n unique states and



counts from 0 to 2n-1. The 2nth count causes the counter to “roll over” or reset to the initial state, i.e. all zeros. Actually, adding one to the counts causes a carry to be generated, which is disregarded in these devices.

Table 22 contains the values of the first 32 powers of 2 expressed in base 10 (decimal or DEC), base 8 (octal or Oct), and base 16 (hexadecimal or Hex). The right most column of Table 22 contains the common names often given to the corresponding quantities. This nomenclature is an artifact of the computer industry which early on chose to use the short hand name “one K” to represent the much longer and more appropriate name “One thousand twenty four,” etc.

A real flip flop, as with any real device, takes time to change states, i.e. there is a delay between the time new values occur on the inputs of the device and the outputs change to reflect the new inputs. When devices are cascaded as seen here, the first device takes an amount of time to settle to the new state after the clock pulse and the next stage doesn’t even see the effect of the pulse until after the first delay has occurred. The third device has to wait for the second stage to settle, and so on. Thus, the new value “ripples” through the counter. For a counter with n stages, the time for a new value to settle is on the order of n*tdelay where tdelay is the time required for one flip flop to settle. This defines the maximum speed at which the counter can properly operate, i.e. the new value settles in before the next clock pulse occurs at the input of the circuit. To count faster, one must use faster flip flops or go to other techniques, e.g. synchronous counters.

6.2. Variable Modulus The approach seen above can be extended to counters of other than modulo 2. These counters can be implemented by resetting the flip flops of the binary counter at the proper point during the accumulation of counts. This section will explore a few of these.

The circuit of Figure 33 is completed by connecting various outputs of the flip-flops to the inputs, X, Y, and Z, of the three input Nand gate. A pulse train (periodic or not) is connected to the input IN. All three flip flops are initially cleared. The flip flops are cleared by a low on the Clear inputs. The 1 Shot or monostable outputs a pulse of constant width that is determined by RC. This is done to insure that CLEARALL is low long enough to cause all stages to clear.

As you will see, only the configurations for modulo 5, 6, 7, and 8 are worthwhile. In fact, the Modulo 8 configuration is exactly the case of Figure 32. Modulo 4 can be accomplished with two flip-flops with out the extra logic. Modulo 3 can be achieved with two flip-flops and a two input Nand Gate. The modulo 0 and 1 configurations have no value.



ClockIn

Set

Clear

Q

A B C

Q

Clock Clock

Set Set

Clear Clear

Q Q

Q Q

VariableModulusCounter.cdr 10-Oct-2004

Trig

Q

R C

1Shot

Q

X

YZ

CLEARALL

Figure 33 - Variable Modulus Counter

Table 23 - Summary of Variable Modulus Configurations

Modulo Z Y X Comment

8 none none none Only need the three flip-flops without the extra logic.

7 CQ BQ AQ Valid use of circuit.

6 CQ BQ

AQ Valid use of circuit.

5 CQ

BQ AQ Valid use of circuit.

4 CQ

BQ AQ Why not just use the two flip-flops without the extra logic?

3 CQ BQ AQ Why not just use two flip-flops with a two input Nand?

2 CQ BQ

AQ Why not just use a single flip-flop?

1 CQ BQ AQ Why bother?

0 CQ BQ AQ

Does nothing.

In the tables below, the following convention is used.

This state is very short lived. Flip-flops are immediately reset within the delay time that is characteristic of the devices.



6.2.1. Modulo 0 Connections: AQ to X, BQ to Y, CQ to Z

CLEARALL =

ABC QQQ •• ABC QQQ •• CQ BQ AQ Decimal

CQ BQ AQ After

Pulse #

0 1 1 1 1 0 0 0 0 Before 1st

0 1 1 1 1 0 0 0 0 1

0 1 1 1 1 0 0 0 0 2

0 1 1 1 1 0 0 0 0 3

0 1 1 1 1 0 0 0 0 4

0 1 1 1 1 0 0 0 0 5

0 1 1 1 1 0 0 0 0 6

0 1 1 1 1 0 0 0 0 7

0 1 1 1 1 0 0 0 0 8

0 1 1 1 1 0 0 0 0 9

0 1 1 1 1 0 0 0 0 10

Clear is always asserted, flip-flops will never toggle.


CLEARALL =


CQ BQ AQ After

Pulse #

1 0 1 1 0 0 0 0 0 Before 1st

0 1 1 1 1 1* 0 0 1 1

1 0 1 1 0 0 0 0 0 clear immediately

0 1 1 1 1 1* 0 0 1 2


0 1 1 1 1 1* 0 0 1 3


0 1 1 1 1 1* 0 0 1 4


0 1 1 1 1 1* 0 0 1 5


0 1 1 1 1 1* 0 0 1 6


0 1 1 1 1 1* 0 0 1 7


0 1 1 1 1 1* 0 0 1 8


* Transitory. Disappears immediately.




CLEARALL =

ABC QQQ •• ABC QQQ •• CQ BQ

AQ Decimal CQ BQ AQ After Pulse #

1 0 1 0 1 0 0 0 0 Before 1st

1 0 1 0 0 1 0 0 1 1

0 1 1 1 1 2* 0 1 0 2


1 0 1 0 0 1 0 0 1 3

0 1 1 1 1 2* 0 1 0 4


1 0 1 0 0 1 0 0 1 5

0 1 1 1 1 2* 0 1 0 6


1 0 1 0 0 1 0 0 1 7

0 1 1 1 1 2* 0 1 0 8



6.2.4. Modulo 3 Connects: AQ to X, BQ to Y, CQ to Z

CLEARALL =


CQ BQ AQ After

Pulse #

1 0 1 0 0 0 0 0 0 Before 1st

1 0 1 0 1 1 0 0 1 1

1 0 1 1 0 2 0 1 0 2

0 1 1 1 1 3* 0 1 1 3


1 0 1 0 1 1 0 0 1 4

1 0 1 1 0 2 0 1 0 5

0 1 1 1 1 3* 0 1 1 6


1 0 1 0 1 1 0 0 1 7

1 0 1 1 0 2 0 1 0 8

0 1 1 1 1 3* 0 1 1 9


1 0 1 0 1 1 0 0 1 10





CLEARALL =

ABC QQQ •• ABC QQQ •• CQ BQ AQ Decimal CQ BQ AQ After

Pulse #

1 0 0 1 1 0 0 0 0 Before 1st

1 0 1 1 0 1 0 0 1 1

1 0 1 0 1 2 0 1 0 2

1 0 1 0 0 3 0 1 1 3

0 1 1 1 1 4* 1 0 0 4


1 0 1 1 0 1 0 0 1 5

1 0 1 0 1 2 0 1 0 6

1 0 1 0 0 3 0 1 1 7

0 1 1 1 1 4* 1 0 0 8




CLEARALL =


Pulse #

1 0 0 1 0 0 0 0 0 Before 1st

1 0 0 1 1 1 0 0 1 1

1 0 0 0 1 2 0 1 0 2

1 0 0 0 1 3 0 1 1 3

1 0 1 1 0 4 1 0 0 4

0 1 1 1 1 5* 1 0 1 5


1 0 0 1 1 1 0 0 1 6

1 0 0 0 1 2 0 1 0 7

1 0 0 0 1 3 0 1 1 8

1 0 1 1 0 4 1 0 0 9

0 1 1 1 1 5* 1 0 1 10






CLEARALL =


Pulse #

1 0 0 0 1 0 0 0 0 Before 1st

1 0 0 0 0 1 0 0 1 1

1 0 0 1 1 2 0 1 0 2

1 0 0 1 0 3 0 1 1 3

1 0 1 0 1 4 1 0 0 4

1 0 1 1 0 5 1 0 1 5

0 1 1 1 1 6* 1 1 0 6


1 0 0 0 0 1 0 0 1 7

1 0 0 1 1 2 0 1 0 8

1 0 0 1 0 3 0 1 1 9

1 0 1 0 1 4 1 0 0 10

1 0 1 1 0 5 1 0 1 11

0 1 1 1 1 6* 1 1 0 12





6.2.8. Modulo 7 Connections: CQ to X, BQ to Y, AQ to Z

CLEARALL =

ABC QQQ •• ABC QQQ •• CQ BQ AQ Decimal CQ BQ AQ After Pulse #

1 0 0 0 0 0 0 0 0 Before 1st

1 0 0 0 1 1 0 0 1 1

1 0 0 1 0 2 0 1 0 2

1 0 0 1 1 3 0 1 1 3

1 0 1 0 0 4 1 0 0 4

1 0 1 0 1 5 1 0 1 5

1 0 1 1 0 6 1 1 0 6

0 1 1 1 1 7* 1 1 1 7


1 0 0 0 1 1 0 0 1 8

1 0 0 1 0 2 0 1 0 9

1 0 0 1 1 3 0 1 1 10

1 0 1 0 0 4 1 0 0 11

1 0 1 0 1 5 1 0 1 12

1 0 1 1 0 6 1 1 0 13

0 1 1 1 1 7* 1 1 1 14





6.2.9. Modulo 8 Connections: None

CQ BQ AQ Decimal CQ BQ AQ After Pulse #

0 0 0 0 0 0 0 Before 1st

0 0 1 1 0 0 1 1

0 1 0 2 0 1 0 2

0 1 1 3 0 1 1 3

1 0 0 4 1 0 0 4

1 0 1 5 1 0 1 5

1 1 0 6 1 1 0 6

1 1 1 7 1 1 1 7

0 0 0 0 0 0 0 8

0 0 1 1 0 0 1 9

0 1 0 2 0 1 0 10

0 1 1 3 0 1 1 11

1 0 0 4 1 0 0 12

1 0 1 5 1 0 1 13

1 1 0 6 1 1 0 14

1 1 1 7 1 1 1 15

0 0 0 0 0 0 1 16



6.2.10. Timing Example (Modulo 5)

pIn

t0 t1 t2 t3 t4 t5 t7 t8t6

Modulo5Timing.cdr 10-Oct-2004

In

QA

QB

QA

QB

QC• •Q QB A

QC

QC

1

0

pQB

1

0

1

1

0

0

1

0

1

0

1

1

0

0

t9 t10 t11 t12 t13 t15 t16t14

Figure 34 - Modulo 5 Counter Timing

Figure 34 illustrates the timing for the modulo 5 counter. Notice that InQC pp 5= or 5

ff InQC =

and this combination of the three flip flops can be called a “divide by 5” circuit.

CountingEdges.cdr 10-Oct-2004

A 1

0

B

D

1

1

0

0

1

0C

Figure 35 - 4 Pulse Trains

An important fact to remember is that all of the binary and variable modulo counters are really counting edges. Thus, all 4 pulse trains in Figure 35 would give the same answer, i.e. 8, when



input to the counter of Figure 32. The circuits have “divide by n” property only when the input signal is periodic.

6.3. Binary Counter with Preset Up to this point, the assumption has been made that the counters begin zeroed, i.e. all flip flops are in the cleared state. Figure 36 illustrates a 4 stage binary counter where a starting value can be loaded before the counting begins by presenting the value to the Preseti and strobing Load. The counter also has a fifth stage to indicate when an overflow occurs. Table 24 is the table of states for the counter.

Clock Clock

Set

Clear

Q

Q

Clock

Set

Clear

Q

Q

Set

Clear

Q

Q

Set

Clear

Q

Q

Set

Clear

Q

Q

Clock

Set

Clear

Q

Q

Set

Clear

Q

Q

Clock

Set

Clear

Q

Q

Set

Clear

Q

Q

A

IN

Load

PresetA PresetB PresetC PresetD

B C D Overflow

Over

Under

Counter_Presets.cdr 28-Oct-2004

Figure 36 - Binary Counter with Preload



Table 24 – 4 Stage Counter with Overflow - State Table

Hex Dec Under DQ CQ BQ AQ Hex Dec Over DQ CQ BQ AQ After Pulse #

F 15 1 1 1 1 1 0 0 0 0 0 0 0 0, Before 1st

E 14 1 1 1 1 0 1 1 0 0 0 0 1 1

D 13 1 1 1 0 1 2 2 0 0 0 1 0 2

C 12 1 1 1 0 0 3 3 0 0 0 1 1 3

B 11 1 1 0 1 1 4 4 0 0 1 0 0 4

A 10 1 1 0 1 0 5 5 0 0 1 0 1 5

9 9 1 1 0 0 1 6 6 0 0 1 1 0 6

8 8 1 1 0 0 0 7 7 0 0 1 1 1 7

7 7 1 0 1 1 1 8 8 0 1 0 0 0 8

6 6 1 0 1 1 0 9 9 0 1 0 0 1 9

5 5 1 0 1 0 1 A 10 0 1 0 1 0 10

4 4 1 0 1 0 0 B 11 0 1 0 1 1 11

3 3 1 0 0 1 1 C 12 0 1 1 0 0 12

2 2 1 0 0 1 0 D 13 0 1 1 0 1 13

1 1 1 0 0 0 1 E 14 0 1 1 1 0 14

0 0 1 0 0 0 0 F 15 0 1 1 1 1 15

F 15 0 1 1 1 1 10 16 1 0 0 0 0 16

6.4. Variable Modulus Counter The preload feature provides the ability to implement a counter of variable modulus. Such a counter with n stages plus the overflow stage may have any modulus between 2 and 2n. The selection of the modulus is made by the choice of the value to be preloaded. If the modulus m is desired, the value to be preloaded will be 2n – m for an n stage counter. There will also have to be logic added to automatically reload the counter with the preload value every time the counter overflows. This logic will not be shown here.

Table 25 and Figure 37 show the behavior of a modulo-5 counter with a periodic signal on In. Table 26 and Figure 38 illustrate a modulo-9 counter.



Table 25 – Modulo 5 Counter, Preload Value = 11

Hex Dec Under DQ CQ BQ AQ Over Hex Dec DQ CQ BQ AQ After Pulse #

4 4 11 0 1 0 0 0 B 11 1 0 1 1 Before 1st

3 3 1 0 0 1 1 0 C 12 1 1 0 0 1

2 2 1 0 0 1 0 0 D 13 1 1 0 1 2

1 1 1 0 0 0 1 0 E 14 1 1 1 0 3

0 0 1 0 0 0 0 0 F 15 1 1 1 1 4

15 F 0 1 1 1 1 1 0 0 0 0 0 0 5

4 4 1 0 1 0 0 0 B 11 1 0 1 1 Preload immediately

3 3 1 0 0 1 1 0 C 12 1 1 0 0 6

2 2 1 0 0 1 0 0 D 13 1 1 0 1 7

1 1 1 0 0 0 1 0 E 14 1 1 1 0 8

0 0 1 0 0 0 0 0 F 15 1 1 1 1 9

15 F 0 1 1 1 1 1 0 0 0 0 0 0 10

4 4 1 0 1 0 0 0 B 11 1 0 1 1 Preload immediately

3 3 1 0 0 1 1 0 C 12 1 1 0 0 11

2 2 1 0 0 1 0 0 D 13 1 1 0 1 12

1 1 1 0 0 0 1 0 E 14 1 1 1 0 13

0 0 1 0 0 0 0 0 F 15 1 1 1 1 14

15 F 0 1 1 1 1 1 0 0 0 0 0 0 15

1 2 3 4 5 6 7 8 9 10 11 1213 14 15

IN

QA

QB

QC

QD

Over

1

01

01

01

0

1

0

1

0

Mod05CounterTiming.cdr 28-Oct-2004

Figure 37 – Modulo-5 Counter Timing



Table 26 –Modulo 9 Counter, Preload Value = 7

Hex Dec Under DQ CQ BQ AQ Hex Dec Over DQ CQ BQ AQ After Pulse #

8 8 1 1 0 0 0 7 7 0 0 1 1 1 Before 1st

7 7 1 0 1 1 1 8 8 0 1 0 0 0 1

6 6 1 0 1 1 0 9 9 0 1 0 0 1 2

5 5 1 0 1 0 1 A 10 0 1 0 1 0 3

4 4 1 0 1 0 0 B 11 0 1 0 1 1 4

3 3 1 0 0 1 1 C 12 0 1 1 0 0 5

2 2 1 0 0 1 0 D 13 0 1 1 0 1 6

1 1 1 0 0 0 1 E 14 0 1 1 1 0 7

0 0 1 0 0 0 0 F 15 0 1 1 1 1 8

F 15 0 1 1 1 1 10 16 1 0 0 0 0 9

8 8 1 1 0 0 0 7 7 0 0 1 1 1 Preload immediately

7 7 1 0 1 1 1 8 8 0 1 0 0 0 10

6 6 1 0 1 1 0 9 9 0 1 0 0 1 11

5 5 1 0 1 0 1 A 10 0 1 0 1 0 12

4 4 1 0 1 0 0 B 11 0 1 0 1 1 13

3 3 1 0 0 1 1 C 12 0 1 1 0 0 14

2 2 1 0 0 1 0 D 13 0 1 1 0 1 15

1 1 1 0 0 0 1 E 14 0 1 1 1 0 16

0 0 1 0 0 0 0 F 15 0 1 1 1 1 17

F 15 0 1 1 1 1 10 16 1 0 0 0 0 18

8 8 1 1 0 0 0 7 7 0 0 1 1 1 Preload immediately

7 7 1 0 1 1 1 8 8 0 1 0 0 0 19

6 6 1 0 1 1 0 9 9 0 1 0 0 1 20

5 5 1 0 1 0 1 A 10 0 1 0 1 0 21

4 4 1 0 1 0 0 B 11 0 1 0 1 1 22

3 3 1 0 0 1 1 C 12 0 1 1 0 0 23

2 2 1 0 0 1 0 D 13 0 1 1 0 1 24

1 1 1 0 0 0 1 E 14 0 1 1 1 0 25

0 0 1 0 0 0 0 F 15 0 1 1 1 1 26

F 15 0 1 1 1 1 10 16 1 0 0 0 0 27



1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16 17 18 19 20

IN

QA

QB

QC

QD

Over

1

01

01

01

0

1

0

1

0

Mod05CounterTiming.cdr 28-Oct-2004

Figure 38 – Modulo-9 Counter Timing

6.5. Up/Down Counter Table 24 is the Table of States for a 4 stage binary counter with an additional stage to indicate when the counter “rolls over” or “overflows.” Included are not only the values for the Qi but also the iQ . Notice that as the Qi count up, the iQ .are counting down. This fact makes provides the basis for implementing a counter that will count either up or down.

Figure 40 illustrates one approach to implement the desired counter. The signal Up selects whether Qi or iQ , will be presented at the outputs, Outi. The starting value is presented to the Preseti and Load is strobed. The circuit takes advantage of the 2-bit multiplexer that is shown in Figure 39. Table 27 is the table of states for the 2-Bit Multiplexer. Careful inspection of Table 27 indicates that the behavior is completely described by the abbreviated table of states shown in Table 28

A B

Up

OutCounter_UpDn_02.cdr 12-Oct-2004

1

2 3

4

0 BA 0

A B

1 0

0 1

Figure 39 – 2-Bit Digital Multiplexer



Table 27 - - 2-Bit Multiplexer - Table of States

C B A 1 2 3 Out

0 0 0 1 0 0 0

0 0 1 1 0 0 0

0 1 0 1 0 1 1

0 1 1 1 0 1 1

1 0 0 0 0 0 0

1 0 1 0 1 0 1

1 1 0 0 0 0 0

1 1 1 0 1 0 1

Table 28 - - 2-Bit Multiplexer - Table of States (Abbreviated)

C Out

0 B

1 A

Clock

Set

Clear

Q

Q

A

IN

Up

Load

PresetA

Clock

Set

Clear

Q

Q

B

PresetB

Clock

Set

Clear

Q

Q

C

PresetC

OutA OutB OutC OutD

Clock

Set

Clear

Q

Q

D

PresetD

OverUnder

Clock

Set

Clear

Over

Under

Q

Q

OverFlow

Counter_UpDn.cdr 10-Oct-2004

Figure 40 - Simple Up/Down Counter

Chemistry 838 Aspects of Digital Electronics REVISION HISTORY


7. REVISION HISTORY Revision History for Aspects of Digital Electronics

Version Date Authors Description

1.0 12-Oct-2004 T V Atkinson This document is the transcription of my lecture notes as distilled over 3 decades of CEM 838. This is the first edition of the material in this form.

1.1 4-Nov-2004 T V Atkinson Added the variable modulus and up/down counters.

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