ASIC Development for Vertex Detector ’07 6/14 Y. Takubo (Tohoku university)
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Transcript of ASIC Development for Vertex Detector ’07 6/14 Y. Takubo (Tohoku university)
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ASIC Development for Vertex Detector
’07 6/14 Y. Takubo(Tohoku university)
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Introduction
Motivation to develop readout ASIC• A large number of FPCCD channel must be read with ASIC.
• Test sample will be delivered within 2007.
• Readout ASIC is necessary to test the FPCCD test sample.
Today’s talk• Requirement to the readout ASIC
• Chip design
• Schedule
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ILC-FPCCDILC-FPCCD• Pixel size : 5m
• Thickness : 15m
• Signal level : ~500e for penetration with large angle→ Readout ASIC must be low noise.
• Wafer size L1, L2 : 10 x 65 mm2
L3-L6 : 20 x 100 mm2
• Readout channel : 16 or 32 ch L1, L2 : 13,000 x 128 pix/ch L3-L6 : 20,000 x 128 pix/ch
ILC vertex detector is constructed with FPCCD wafers.
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FPCCD vertex detector
Size (mm2) ch/wafer # of wafers # of chL1, L2 10 x 65 16 15 x 2(z) 480
L3, L4 20 x100 32 16 x 2(z) 1024
L5, L6 20 x 100 32 24 x 2(z) 1536
Total 220 6080
cos = 0.95
cos = 0.9
L1
L6
FPCCD vertex detector• # of wafers : 220
• Readout channel : ~6000ch
• All pixels in one channel is read within 200ms
• Required power consumption : < 100W.
to be investigated
Structure and performance of FPCCD determines requirement to the readout ASIC.
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Requirement to the readout ASICRequirement to the readout ASIC• Amplifier, LPF, CDS, ADC and DSP are mounted on one chip.
• Readout rate : >10 Mpix/sec [20000 x 128 pix]/[0.2 s]
• Total noise level including the CCD : <50 electrons
• Power consumption : < 10mW/ch (~100W/6000ch)
• Channel width : 0.64 mm 5m x 128pix
To achieve these requirement, readout ASIC is designed by Ikeda-san.
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Block diagram of readout ASICDesign concept was made by Ikeda-san.
From CCD Voltage
amplifierLow-pass filter
Charge-sharing ADC (6bit)
Charge-sharing ADC (6bit)
LVDS driver
Reset
Gain control
Band-width control
Track/Hold
Conversion
CK(100MHz)
Serial output
2 ADCs are activated alternatively.
Specification of the ASIC design is summarized.
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Specification of readout ASICSpecification of readout ASIC• 0.35 m process by TSMC• Size : 3 x 3 mm2
• # of pad : 80• # of signal channels : 4• AD conversion rate : 10 MHz x 2• Clock frequency : 100 MHz• Data width : 6bit + sign bit• Power rail : ±1.65 V• Analog gain : adjustable• Frequency bandwidth : adjustable• Interface : LVDS/LVTTL Performance of the readout ASIC
is estimated.
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Expected performanceExpected performance• Power consumption < 5 mW
Charge-sharing ADC realizes low power and fast AD conversion.
• Readout rate : 20 Mpix/sec Data conversion rate : 10x2 MHz 130 ms/ch : [20000 x 128 pix/ch] x [5 x 10 - 8 s/pix]
• Channel width : 0.75mm (=3/4)
To be evaluated• Determination of signal scale• Estimation of noise level
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Schedule• ~ August in 2007
Simulation study Determination of chip design Ordering the readout chip
• ~ January in 2008 The chip will be delivered. Response test of the readout chip Readout test of FPCCD with readout ASIC Improvement of the chip design for the 2nd prototype.
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23/05/14 Conceptual Design for FPCCD ASIC 11
C1
C2
Gain= -C1/C2
To be arrange as a binary weighted arrayLocated to improve peakingcharacteristics
Switch for DC restoration
Low noise amplificationelement
Bias voltagegenerator
To mitigatethe clock-feedthru
Source followerfor DC level-shift
Voltage amplifier
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23/05/14 Conceptual Design for FPCCD ASIC 12
To subtract DC levelduring rest phase(CDS)
Second-order low—passfilter with gm-C filter technique
Band-pass node
Low-pass node
G=1
Low-pass filter
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23/05/14 Conceptual Design for FPCCD ASIC 13
INPUT
Parallel out
Serial out
Data valid
Reference voltage
Shift register
Switch control and bit-storage
For settleing
OUTP
OUTM
Charge sharing successive approximation AD converter
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23/05/14 Conceptual Design for FPCCD ASIC 14
MSB LSB0.4 pF + 0.4 pF 0.0625 pF
Capacitor bank
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23/05/14 Conceptual Design for FPCCD ASIC 15
Driven by clock
Low-assertedfor meta-stable transients
Comparator
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23/05/14 Conceptual Design for FPCCD ASIC 16
Driver Reciever
LVDS interface
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23/05/14 Conceptual Design for FPCCD ASIC 17
Driver Receiver
LVTTL interface