Array-Based Architecture for FET-Based, Nanoscale Electronics
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Array-Based Architecture for FET-
Based, Nanoscale Electronics
André DeHon2003
Presented By Mahmoud Ben Naser
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Move to Nanotechnology CMOS size limits
Cost of Fabrication
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Source: Kahng/ITRS2001
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Differences with current technologyCMOS Top Down construction Precise placement of devicesNanotechnology Bottom Up construction Stochastic assembly.
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Building Blocks (Wires) Carbon Nanotubes (CNTs or NT) Silicon NanoWires (SiNW or NW)
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Carbon Nanotube Built by “exploding” carbon or carbon
vapor. Can be conducting or semiconducting A few nm diameter Can’t selectively manufacture one type or
the other.
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Silicon Nanowires “Grown” by vapor
deposition Precise diameter control
of a few nm Microns long Selectively dope length to
control electrical properties
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Devices (Switches) CNT Suspended Memories Molecular Switches SiNW FET
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CNT switches CNTs in parallel suspended above
perpendicular set of CNTs
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SiNW Core Shell NW Gated by NT or NW
Diode FET
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ArchitectureUsing building blocks and switches what can
we build? Crossbar Arrays Memory, PLA, or Interconnect Collection of small
arrays to exploit logical structure and isolate faults
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Electrical OperationDiode Logic NW or NT crosspoint directly touching Wired-OR Programmable
Junction Problem:
Non-restring
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Electrical Operation FET Logic (PFET) Problems:
Generally Non-Programmable Logic Static Power Consumption
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NOR Results
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Using the Crossbar Array Connect to the microworld without loosing
gains from nano-pitch Program junctions
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Addressing individual NWs Can’t connect a W to each NW. Use a nanodecoder with 2-hot addressing
(minimize the effect fault on address line).
To Crossbar Array
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Nano-Decoder Evaluation Advantage: Precise predefined codeset
Only loose Sqrt(n) wires on address fault Disadvantage: Hard to create nano-imprint
pattern Use axially doped NW instead
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Big Picture 4 Decoders 2 Decoders
Can disable decoders if needed during operation
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Programmable FET Arrays
Using Core-Shelled NWs on the bottom and NTs on the top.
During operation use decoder as pull up or pull down network.
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Bigger Picture
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Crosspoint Density Decoders add a lot of overhead, is it still
worth it to “go nano”? Still do better then CMOS bit-density. Can
easily achieve 50% of core density.
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Defect ToleranceTypes of defects Broken wire Defective crosspoint Defective array
Add Redundancy
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Broken Wire Components fully interchangeable Rout around defect.
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Defective Crosspoints HP calculates 15% of crospoints “Stuck” Use algorithm to successfully rout around
this
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Defective Array Though more unlikely, it’s possible. Ensure availability of more resources to
completely rout around the array.
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Effects of Defects Look at expected yield of address decoder
and multiply by expected yield of crossbar array.
Both dependant on design model chosen Type of codes used in decoder Building block used
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Conclusion Nanoelectronic systems provide several advantages
over conventional silicon, most importantly increased density.
Because of their extremely small size, nanoscale devices present new problems in fabrication and fault tolerance that must be overcome.
must be able to interface with conventional silicon chips, at least in the short run.