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ARM-TUTORIAL Vishal Pattanashetty {BE, MTECH, ISTE }. Assistant professor, Dept. of IT, BVBCET Hubli.

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ARM microcontroller basics

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ARM-TutorialVishal Pattanashetty {BE, MTECH, ISTE }.Assistant professor, Dept. of IT, BVBCET Hubli.1AgendaIntroductionMicroprocessor and MicrocontrollerBasics of ARMARM Programming Introduction

First microprocessor IN-4004Introduction :Processor architecturesBased on memoryVon Neumann and Harvard architecture Based on instructionsCISC and RISCIntroduction: Von Neumann and Harvard architecture

Introduction: CISC and RISCThe major characteristics of CISC architecture are: Large number of instructions .Some instructions that perform specialized tasks and are used infrequently. Large variety of addressing modes. Variable length instruction formats. Instructions that manipulate operands in memory.

The major characteristics of RISC architecture are:

Relatively few instructions Relatively few addressing modes Memory access limited to load and store instructions All operations done within the registers of the CPU Fixed-length, easily decoded instruction format Single-cycle instruction execution Hardwired rather than microprogrammed control Relatively large number of registers in the processor unit Use of overlapped register windows to speed-up procedure call and return Efficient instruction pipeline Ability to execute one instruction per clock cycle Compiler support for efficient translation of high-level language programs into machine language programs

Microprocessor and Microcontroller

Microprocessor-Based System


MPU-Based System10ARMAcorn/Advanced RISC MachineDeveloped at Acorn Computers Limited,of Cambridge, England,between 1983 and 1985Low powerLow costTiny8/16/32 bit microprocessorThumb modeARM7- Von Neuman ArchitectureARM9 Harvard ArchitectureARMTypical RISC architecture:Large uniform register fileLoad/store architectureSimple addressing modesUniform and fixed-length instruction fieldsEnhancements:Each instruction controls the ALU and shifterAuto-incrementand auto-decrement addressing modesMultiple Load/StoreConditional execution


Data forwardingADD R3, R2, R1 ; R3=R2+R1 DependencyADDR5, R4, R3 ;R5=R4+R3

SOLUTION :ADD R3, R2, R1 ; R3=R2+R1 ADD R7,R6ADDR5, R4, R3 ;R5=R4+R3