ARM CONTROLLER

CISC versus RISCCISC RISC Emphasis on hardware Emphasis on software Includes multi-clockcomplex instructions Single-clock,reduced instruction only Memory-to-memory:"LOAD" and "STORE"incorporated in instructions Register to register:"LOAD" and "STORE"are independent instructions Small code sizes,high cycles per second Low cycles per second,large code sizes Transistors used for storingcomplex instructions Spends more transistorson memory registers

ARM LtdFounded in November 1990Spun out of Acorn Computers

Designs the ARM range of RISC processor coresLicenses ARM core designs to semiconductor partners who fabricate and sell to their customers.ARM does not fabricate silicon itself

Also develop technologies to assist with the design-in of the ARM architectureSoftware tools, boards, debug hardware, application software, bus architectures, peripherals etc.The ARM processor core originates within a British computer company called Acorn. In the mid-1980s they were looking for replacement for the 6502 processor used in their BBC computer range, which were widely used in UK schools. None of the 16-bit architectures becoming available at that time met their requirements, so they designed their own 32-bit processor.Other companies became interested in this processor, including Apple who were looking for a processor for their PDA project (which became the Newton). After much discussion this led to Acorns processor design team splitting off from Acorn at the end of 1990 to become Advanced RISC Machines Ltd, now just ARM Ltd.Thus ARM Ltd now designs the ARM family of RISC processor cores, together with a range of other supporting technologies.One important point about ARM is that it does not fabricate silicon itself, but instead just produces the design - we are an Intellectual Property (or IP) company. Instead silicon is produced by companies who license the ARM processor design.Origin Of the Name ARM7TDMIARM Acron Risc Machine (Now Advanced Risc Machine)T The Thumb 16 bit instruction set.D On chip Debug support.M Enhanced MultiplierI Embedded ICE hardware to give break point and watch point support.

3/16/20133ARMARM stands for Advanced RISC Machines

An ARM processor is basically any 16/32bit microprocessor designed and licensed by ARM Ltd, a microprocessor design company headquartered in England, founded in 1990 by Herman Hauser

A characteristic feature of ARM processors is their low electric power consumption, which makes them particularly suitable for use in portable devices.

It is one of the most used processors currently on the market

Why ARM?The ARM is a 32-bit reduced instruction set computer (RISC).

It was known as the Advanced RISC Machine, and before that as the Acorn RISC Machine

ARM processors made them suitable for low power applications.

This has made them dominant in the mobile and embedded electronics market as relatively low cost. APPLICATIONSConsumer electronics including PDAs, mobile phones, digital media and music players, hand-held game consoles, calculators and computer peripherals such as hard drives and routers.

It uses innovative architectural design to achieve high performance with low power consumption.

It is highly utilized in mobile and embedded devices due to its power characteristics and is one of the most populous processors currently used..

FEATURES OF LPC2148PACKAGE:16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

MEMORY:8 to 40 kB of on-chip static RAM

32 to 512 kB of on-chip flash program memory.

SPEED:128 bit wide interface/accelerator enables high speed 60 MHz operation.

In-System / In-Application Programming (ISP/IAP) via on-chip boot-loader software.

Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.

USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.

In addition, the LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by DMA.

ADC: Two 10-bit A/D converters(AD0 and AD1) provide a total of 14 analog inputs conversion times as low as 2.44 s per channel.

DAC:Single 10-bit D/A converter provides variable analog output.

TIMERS:

Two 32-bit timers/external event counters

Each timer with four capture and four compare channels

PWM unit (six outputs)

Watchdog timer

RTC: Low power real-time clock with independent power and dedicated 32 kHz clock input.

Serial Interfaces:

I2C-bus:Two Fast I2C-bus with 400 kbit/s

Serial communication:Two UARTs (16C550)

SPI (Serial Peripheral Interface) and SSP(Synchronous Serial Port) with buffering and variable data length capabilities

Fast GPIO:Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.INTERRUPTS:Vectored interrupt controller with 16 configurable priorities and vector addresses.9 edge or level sensitive external interrupt pins available.

60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 s.

OSCILLATOR: On-chip integrated oscillator operates with an external crystal in range from 1 MHz to 30 MHz and with an external oscillator up to 50 MHz

Power saving modes: Idle mode Power-down mode

CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.Applications Industrial control Medical systems Access control Point-of-sale Communication gateway Embedded soft modem General purpose applicationsMODES AND REGISTERSProcessor ModesARM has 7 operating modes-User (unprivileged mode under which most tasks run)-Fast Interrupt Request Mode FIQ (to handle high priority interrupt )-Interrupt Mode IRQ (entered when a low priority interrupt is raised )-Supervisor Mode SVC (entered on reset or a software interrupt )-Abort Mode ABT (used to handle memory access violation)-Undefined Mode UND (used to handle undefined instruction)-System Mode SYS (uses same registers as user mode)

3/16/201317MODESMost application program run in User Mode

A program in user mode is unable to access some protected system resources or to change mode , other than by causing exception

Mode change can be by -Software control-External interrupts-Exception processing

3/16/201318MODESModes other than user mode are called privileged modes

Privileged modes has full access to the system resources

Five of them are called exception modes-FIQ-IRQ-SVC-ABT-UND

3/16/201319MODESProcessor enters into Privileged modes under specific exception condition

All the exception Modes uses some additional registers ,to avoid corrupting the user state when exception occurs

SYS uses the same no: of registers as the User Mode 3/16/201320 REGISTER BANKARM 7 uses load and store Architecture.

Data has to be moved from memory location to a central set of registers.

Data processing is done and is stored back into memory.

Register bank contains, general purpose registers to hold either data or address.

It is a bank of 16 user registers R0-R15 and 2 status registers.

Each of these registers is 32 bit wide.

3/16/201321REGISTERSARM has 37 32 bit long registers

30 general purpose registers5 dedicated Saved Program Status Registers1 dedicated Current Program Status Register1 dedicated program counter 3/16/201322General Purpose RegistersCan be divided into three groups Un-banked r0-r7Banked r8-r14PC r153/16/201323Un-banked Registers

Registers r0 to r7

Each of these registers address the same physical registers for all the modes

Completely general purpose registers , with no uses implied by the architecture

3/16/201324Banked RegistersRegisters r8 to r14

physical registers referred to by each of them depends on the mode of operation

Banked register contents are preserved across operating mode changes

3/16/201325Banked Registersr8 to r12 * two banked physical registers each *one for FIQ and other for all other modes *referred to as r8_usr to r12_usr & r8_fiq to r12_fiq

r13 & r14 *has six banked registers each *one in USER & SYS and rest five in each exception modes *referred to as r13_/r14_(for exception modes)3/16/201326

General Purpose Registers30 32 bit registers

15 general purpose registers are visible at one time , depending on the current processor mode ,as r0,r1,r2 r13,r14

r13-conventionally used as stack pointer

r14 conventionally used as link register to store the return address for exception/ sub-routine call

3/16/201327Program CounterPC is accessed as r15

Incremented by 4 bytes for ARM state and 2 bytes for THUMB state

Branch instruction loads destination address into the PC

Can also be loaded using data operation instruction

3/16/201328ARM REGISTERS3/16/201329r0r1r2r3r4r5r6r7r8r9r10r11r12r13r14 r15(PC)CPSRr0r1r2r3r4r5r6r7 r8_fiq r9_fiqr10_fiqr11_fiqr12_fiqr13_fiqr14_fiq r15(PC)CPSRSPSR_fiqr0r1r2r3r4r5r6r7r8r9r10r11r12r13_svcr14_svc r15(PC)CPSRSPSR_svcr0r1r2r3r4r5r6r7r8r9r10r11r12r13_abtr14_abt r15(PC)CPSRSPSR_abtr0r1r2r3r4r5r6r7r8r9r10r11r12r13_irqr14_irq r15(PC)CPSRSPSR_irqr0r1r2r3r4r5r6r7r8r9r10r11r12r13_undr14_und r15(PC)CPSRSPSR_undSYS/USERFIQSVCABTIRQUNDEFINEDCPSR - Current Program Status RegisterCPSR holdsCopies of ALU status flagsThe current processor modeInterrupt disable flag

ALU status flags are used to determine whether conditional instructions are executed or not

On THUMB capable processors ,the CPSR holds the current processor state

3/16/20133004 3 2 1567303129 28NZCVIFTMODEFLAGSCondition code flags

N(31) *set to bit 31 of the result of the instruction *N=0 if positive *N=1 if negative

Z(30) *Z=1 if result is zero *Z=0 if not zero

C(29) *for addition ,set to 1 if carry occurs & 0 otherwise *for subtraction ,set to 0 if borrow occurs & 1 otherwise *for shift operations , C contains the last bit shifted

V (28) *for addition and subtraction V set to 1 if signed overflow occurs 3/16/201331FLAGSControl bits

I(7) *when set disables IRQ interrupt

F(6) *when set disables FIQ interrupt

T(5) *on T variants T=0 ,indicates ARM execution T=1 ,indicates THUMB execution

3/16/201332FLAGSMODE BITS (4:0)

M(4:0)Mode10000User10001FIQ10010IRQ10011Supervisor10111Abort11011UND11111SYS3/16/201333SPSR-Saved Program Status RegisterUsed to store CPSR when an exception is taken

One SPSR is accessible in each of the exception handling mode

User Mode and System Mode doesnt have SPSR as they dont handle exceptions

3/16/201334BLOCK DIAGRAM

Types of buses

AMBA BusLOCAL BusVPB BusCrystal oscillatorWhile an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz can be used by the LPC2141/2/4/6/8 if supplied to its input XTAL1 pin.

This microcontrollers onboard oscillator circuit supports external crystals in the range of 1 MHz to 30 MHz only.

If the on-chip PLL system or the boot-loader is used, the input clock frequency is limited to an exclusive range of 10 MHz to 25 MHz.Crystal oscillatorThe oscillator output frequency is called FOSC and the ARM processor clock frequency is referred to as CCLK for purposes of rate equations, etc.. FOSC and CCLK are the same value unless the PLL is running and connected.

The onboard oscillator in the LPC2141/2/4/6/8 can operate in one of two modes: Slave mode oscillation mode.In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF with an amplitude of at least 200mVrms. The X2 pin in this configuration can be left not connected. If slave mode is selected, the FOSC signal of 50-50 duty cycle can range from 1 MHz to 50 MHzPIN CONFIGURATION

Lpc 2144/6//8 consists 45 GPIO functionality in is 2 port which as

Port0 (P0.0 to P0.31)Port1 (P1.16 to P1.31)

It consist of 19 different peripherals such asFUNCTION PIN TYPE & DESCRIPTION

D+ 10 INPUT/OUTPUT(USB bidirectional D+ line)D- 11 INPUT/OUTPUT(USB bidirectional D- line) XTAL1 62 INPUT(Input to the oscillator circuit and internal clock generator circuits)XTAL2 61 OUTPUT(Output from the oscillator amplifier)RTXC1 3 INPUT(Input to the RTC oscillator circuit)RTXC2 5 OUTPUT(output to the RTC oscillator circuit)VSS 6, 18, INPUT ( Ground: 0 V reference) 25,42,50

VSSA 52 INPUT(Analog Ground: 0 V reference)VDD 23, 43, 51 INPUT(power supply)

VDDA 7 INPUT(analog power supply)VREF 63 INPUT(A/D Converter Reference)VBAT 49 INPUT(RTC power supply)Functionality of pinsFUNCTIONALITY OF PINSPINSEL0 Pin function selectRead/Write 0x0000 0000

PINSEL1 Pin function selectRead/Write 0x0000 0000

PINSEL2 Pin function selectRead/Write 0x0000 0000

PIN FUNCTION SELECT REGISTER 0(Pin ofSelect Port Pin slection FunctionRsister) line 1:0 P0.0 00 GPIO Port 0.0 01 TXD (UART0) 10 PWM1 11 Reserved

3:2 P0.1 00 GPIO Port 0.1 01 RxD (UART0) 10 PWM3 11 EINT0

5:4 P0.2 00 GPIO Port 0.2 01 SCL0 (I2C0) 10 Capture 0.0 (Timer 0) 11 Reserved

7:6 P0.3 00 GPIO Port 0.3 01 SDA0 (I2C0) 10 Match 0.0 (Timer 0) 11 EINT1

9:8 P0.4 00 GPIO Port 0.4 0 01 SCK0 (SPI0) 10 Capture 0.1 (Timer 0) 11 AD0.6

11:10 P0.5 00 GPIO Port 0.5 0 01 MISO0 (SPI0) 10 Match 0.1 (Timer 0) 11 AD0.7

13:12 P0.6 00 GPIO Port 0.6 0 01 MOSI0 (SPI0) 10 Capture 0.2 (Timer 0) 11 Reserved[1][2] or AD1.0[3]

15:14 P0.7 00 GPIO Port 0.7 01 SSEL0 (SPI0) 10 PWM2 11 EINT2

17:16 P0.8 00 GPIO Port 0.8 01 TXD UART1 10 PWM4 11 Reserved[1][2] or AD1.1[3]

19:18 P0.9 00 GPIO Port 0.9 01 RxD (UART1) 10 PWM6 11 EINT3

21:20 P0.10 00 GPIO Port 0.10 01 Reserved[1][2] or RTS (UART1)[3] 10 Capture 1.0 (Timer 1) 11 Reserved[1][2] orAD1.2[3]

23:22 P0.11 00 GPIO Port 0.11 01 Reserved[1][2] or CTS (UART1)[3] 10 Capture 1.1 (Timer 1) 11 SCL1 (I2C1)

25:24 P0.12 00 GPIO Port 0.12 0 01 Reserved[1][2] or DSR (UART1)[3] 10 Match 1.0 (Timer 1) 11 Reserved[1][2] or AD1.3[3]27:26 P0.13 00 GPIO Port 0.13 001 Reserved[1][2] or DTR (UART1)[3]10 Match 1.1 (Timer 1) 11 Reserved[1][2] orAD1.4[3]

29:28 P0.14 00 GPIO Port 0.14 0 01 Reserved[1][2] or DCD (UART1)[3] 10 EINT1 11 SDA1 (I2C1) 31:30 P0.15 00 GPIO Port 0.15 001 Reserved[1][2] or RI (UART1)[3]10 EINT2 11 Reserved[1][2] orAD1.5[3]

29:28 P0.14 00 GPIO Port 0.14 0 01 Reserved[1][2] or DCD (UART1)[3] 10 EINT1 11 SDA1 (I2C1) 31:30 P0.15 00 GPIO Port 0.15 001 Reserved[1][2] or RI (UART1)[3] 10 EINT2 11 Reserved[1][2] orAD1.5[3]

PIN FUNCTION SELECT REGISTER 11:0 P0.16 00 GPIO Port 0.16 0 01 EINT0 10Match 0.2 (Timer 0) 11 Capture 0.2 (Timer 0) 3:2 P0.1700 GPIO Port 0.15 001 Capture 1.2 (Timer 1)10 SCK1 (SSP) 11 Match 1.2 (Timer 1)

5:4 P0.18 00 GPIO Port 0.18 0 01 Capture 1.3 (Timer 1) 10 Match 0.2 (Timer 0) 11 MISO1 (SSP) 7:6 P0.19 00 GPIO Port 0.19 0 01 Match 1.2 (Timer 1) 10 MOSI1 (SSP) 11 Capture 1.2 (Timer 1)9:8 P0.20 00 GPIO Port 0.20 0 01 Match 1.3 (Timer 1) 10 SSEL1 (SSP) 11 EINT3 11:10 P0.21 00 GPIO Port 0.21 001 PWM510 Reserved[1][2] or AD1.6[3] 11 Capture 1.3 (Timer 1)

13:12 P0.22 00 GPIO Port 0.22 0 01 Reserved[1][2] or AD1.7[3] 10 Capture 0.0 (Timer 0)11 Match 0.0 (Timer 0) 15:14 P0.23 00 GPIO Port 0.23 001 VBUS10 Reserved 11 Reserved

17:16P0.24 00 Reserved 01 Reserved 10 Reserved11 Reserved 19:18P0.25 00 GPIO Port 0.25 001 AD0.410Reserved[1] or Aout(DAC)[2][3] 11 Reserved

21:20P0.26 00 Reserved 01 Reserved 10 Reserved11 Reserved 23:22P0.27 00 Reserved01 Reserved10Reserved 11 Reserved

25:24P0.28 00 GPIO Port 0.28 01 AD0.1 10 Capture 0.2 (Timer 0)11 Match 0.2 (Timer 0) 27:26P0.29 00 GPIO Port 0.2901 AD0.210 Capture 0.3 (Timer 0) 11 Match 0.3 (Timer 0)

29:28P0.30 00 GPIO Port 0.30 01 AD0.3 10 EINT311 Capture 0.0 (Timer 0) 31:30P0.31 00 GPO Port only01UP_LED10 CONNECT 11 Reserved

PIN FUNCTION SELECT REGISTER 2

GPIO Every physical GPIO port is accessible via either the group of registers providing an enhanced features and accelerated port access or the legacy group of registers Accelerated GPIO functions: GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved Mask registers allow treating sets of port bits as a group, leaving other bits unchanged All registers are byte and half-word addressable Entire port value can be written in one instructionBit-level set and clear registers allow a single instruction set or clear of any number of bits in one portDirection control of individual bitsAll I/O default to inputs after resetBackward compatibility with other earlier devices is maintained

ApplicationsGeneral purpose I/ODriving LEDs, or other indicatorsControlling off-chip devices Sensing digital inputsGPIO REGISTER MAP

GPIO port Direction register (IODIR)This word accessible register is used to control the direction of the pins when they are configured as GPIO port pins. Direction bit for any pin must be set according to the pin functionality.GPIO port Pin value register (IOPIN)This register provides the value of port pins that are configured to perform only digital functions.The register will give the logic value of the pin regardless of whether the pin is configured for input or output, or as GPIO or an alternate digital function. As an example, a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output as selectable functions. Any configuration of that pin will allow its current logic state to be read from the IOPIN registerIf a pin has an analog function as one of its options, the pin state cannot be read if the analog configuration is selected. Selecting the pin as an A/D input disconnects the digital features of the pin.In that case, the pin value read in the IOPIN register is not valid.Writing to the IOPIN register stores the value in the port output register, bypassing the need to use both the IOSET and IOCLR registers to obtain the entire written value.This feature should be used carefully in an application since it affects the entire portGPIO port output Set register (IOSET)This register is used to produce a HIGH level output at the port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing 1 to the corresponding bit in the IOSET has no effect.Reading the IOSET register returns the value of this register, as determined by previous writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins.GPIO port output Clear register (IOCLR)This register is used to produce a LOW level output at port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears the corresponding bit in the IOSET register. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing to IOCLR has no effect.Fast gpioFAST GPIO REGISTER MAP

Fast GPIO port Mask register (FIOMASK)This register is available in the enhanced group of registers only. It is used to select ports pins that will and will not be affected by a write accesses to the FIOPIN, FIOSET or FIOSLR register. Mask register also filters out ports content when the FIOPIN register is read.A zero in this registers bit enables an access to the corresponding physical pin via a read or write access.If a bit in this register is one, corresponding pin will not be changed withwrite access and if read, will not be reflected in the updated FIOPIN register.Registers of fast gpioFIODIR:Fast GPIO Port Direction control register.FIOPIN:Fast Port Pin value register using FIOMASK.FIOSET:Fast Port Output Set register using FIOMASK.FIOCLR:Fast Port Output Clear register using FIOMASK0.GPIO programmingProgram to blink single led

#includevoid delay(unsigned int);int main(){IODIR0=0X00000001;while(1){IOSET0=0X00000001;delay(20);IOCLR0=0X00000001;delay(20);}}void delay(unsigned int i){int j,k;for(j=0;j