ARM-Intro

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ARM

(Advanced RISC Machines )

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Introduction

ARM core uses a RISC Architecture

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RISC Architecture

Simple but powerful instructions that executewithin a single cycle at a high clock speed.

Reduced complexity of instruction performed by

hardware. Provides greater flexibility and intelligence insoftware, therefore places greater demand on thecompiler.

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ARM design philosophy

High code density (The amount of space that an

executable program takes up in memory ) Reduced area of ARM core-required for

embedded systems.

Incorporates hardware debug technology withinprocessor.

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ARM design philosophy

The Thumb instruction set features a subset of themost commonly used 32-bit ARM instructionswhich have been compressed into 16-bit wideoperation codes. On execution, these 16-bit

instructions are decoded to enable the samefunctions as their full 32-bit ARM instructionequivalents.

provides enhanced code density.

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ARM PROCESSOR

It incorporates these typical RISC architecture

features:

Large uniform register file Load/store architecture, where data-processing

operations only operate on register contents, not

directly on memory contents Simple addressing modes, with all load/store

addresses being determined from register contents

and instruction fields only.

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ARM PROCESSOR

In addition, the ARM architecture provides:

Instructions that combine a shift with anarithmetic or logical operation

Auto-increment and auto-decrement addressing

modes to optimize program loops

Load and Store Multiple instructions to maximize

data throughput

Conditional execution of almost all instructions to

maximize execution throughput.

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ARM PROCESSOR

These enhancements to a basic RISC architectureenable ARM processors to achieve a good balance

of high performance, small code size, low power

consumption, and small silicon area. ARM processor is small to reduce power

consumption and extend battery operation. Eg

mobile phones and PDAs.

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ARM PROCESSOR

ARM core is a 32-bit processor.

ARM processor uses load-store architecture.

There are no data processing instructions that

directly manipulate data in memory.

Data processing is carried out solely in registers.

Register file is made up of 32-bit registers.

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REGISTERS

General purpose registers hold either data or

address

All registers are 32-bit in size.

16 data registers ( R0 to R15) and 2 PSR

ARM processor has assigned special functions to

3 registers.

R13- Stack Pointer (SP)

R14- Link Register (LR) R15- Program Counter (PC)

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Registers

Stack Pointer- stores the head of the stackin the current processor mode

Link register- core puts the return address

when it calls a subroutine

Program counter- contains the address of

the next instruction to be fetched by theprocessor.

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Registers

In ARM state the registers R0 R13 areorthogonal.

Any instruction that you can apply to R0

can equally well apply to other registers.

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Program Status Register

CPSR-Current Program Status Register

- 32-bit register- contains the present status of an internal

operation

SPSR-Saved Program Status Register

- 32-bit register

- contains the status of an internal operation

in the previous mode

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CPSR

ARM uses CPSR to monitor and controlinternal operations.

CPSR is a dedicated 32-bit register and

resides in the register file.

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Generic program Status Register

Flags Status Extensions Control

Processor

mode

Inter-

rupt

MasksCondition flags

ModeTFIVCZN

4 056728293031

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Generic program Status Register

Modes

10000User

11011Undefined

11111System

10011Supervisor

10010Interrupt request

10001Fast interrupt request10111Abort

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Processor Modes

Processor Modes determine - which

registers are active and have access rights to

the CPSR.

Priviledged mode

- allows full read write access to CPSR Non Priviledged mode

- read access to control field of CRSP- read-write access to conditional flags

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Processor Modes

Priviledged Modes

Abort

Fast interrupt request

Interrupt request

SupervisorSystem

Undefined

Nonpriviledged modeUser

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Processor Modes

The ARM has seven operating modes: User(unprivileged mode under which most user tasks

run)

FIQ (entered when a high priority (fast) interrupt israised)

IRQ (entered when a low priority (normal) interrupt israised)

Supervisor(entered on reset or when a SoftwareInterrupt instruction is executed). OS kernel executes.

Abort(used to handle memory access violations)

Undefined(used to handle undefined instructions)

System (privileged mode using the same registers asuser mode). OS routines can be configured to run in thismode.

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Banked Registers

ARM has 37 registers in total, all of whichare 32-bits long.

1 dedicated program counter

1 dedicated current program status register

5 dedicated saved program status registers

30 general purpose registers

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Banked Registers

20 registers are hidden from a program atdifferent times.

These registers are called banked registers

They are available only when the processor

is in a particular mode.

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Banked Registers

Banked registers are arranged into several banks,

with the accessible bank being governed by the

processor mode. Each mode can access a particular set of r0-r12 registers

a particular r13 (the stack pointer) and r14 (link

register)

r15 (the program counter)

cpsr (the current program status register)

and privileged modes can also access

a particular spsr (saved program status register)

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Register OrganisationGeneral registers and Program Counter

Program Status Registers

r15 (pc)

r14 (lr)

r13 (sp)

r14_svc

r13_svc

r14_irq

r13_irq

r14_abt

r13_abt

r14_undef

r13_undef

User32 / System FIQ32 Supervisor32 Abort32 IRQ32 Undefined32

cpsr

sprsr_fiqsprsr_fiqsprsr_fiq spsr_abtspsr_svcsprsr_fiqsprsr_fiqspsr_fiq sprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqspsr_irq

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r7

r4

r5

r2

r1

r0

r3

r6

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r12

r10

r11

r9

r8

r7

r4

r5

r2

r1

r0

r3

r6

r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc)

cpsrcpsrcpsrcpsrcpsr

r14_fiq

r13_fiq

r12_fiq

r10_fiq

r11_fiq

r9_fiq

r8_fiq

sprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqsprsr_fiqspsr_undef

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Banked registers

Every mode except the user mode, can change

mode by writing directly to the mode bits of the

cpsr. All processor modes except system mode have a

set of associated banked registers that are a subset

of the main 16 registers. A banked register maps one-on-one onto a user

mode register.

With change of mode, a banked register from thenew mode will replace an existing register.

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Register Example: User to FIQ Mode

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State and instruction sets

The state of the core determines whichinstruction set is being executed.

Three instruction sets

ARM-Arm state

Thumb-Thumb state

Jazelle- Jazelle state

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ARM and Thumb instruction set features

Separate barrel

shifter and ALUinstructions

Access to barrel

shifter and ALU

Data processing

instructions

Only branch

instructions

MostConditional

execution

3058Core instructions

16-bit32-bitInstruction size

Thumb (cpsr T =1)ARM (cpsr T=0)

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ARM and Thumb instruction set features

8 general purpose

registers+7 high

registers + pc

15 general

purpose registers

+ pc

Register usage

No direct accessRead-write in

privileged mode

Program status

register

Thumb (cpsr T =1)ARM (cpsr T=0)

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Interrupt masks

Interrupt masks are used to stop specific interrupt

requests from interrupting the processor.

Two interrupt request levels- IRQ, FIQ CPSR has two interrupt mask bits

- 7 (I bit )-IRQ

- 8 (F bit )-FIQ

These interrupt requests are masked when set

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Conditional Flags

Updated by

- comparisons

- results of ALU operations that specify Sinstruction suffix.

Eg: SUBS

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Conditional execution

Conditional execution controls whether or not the

core will execute an instruction.

Condition attribute is postfixed to the instructionmnemonic, which is encoded into the instruction.

Prior to execution, the processor compares the

condition attribute with the conditional flags in theCPSR.

If they match then the condition is executed.

When a condition mnemonic is not present, it isalways AL

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Conditional execution

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Using and updating the Condition Field

To execute an instruction conditionally, simply

postfix it with the appropriate condition:

For example an add instruction takes the form:

ADD r0,r1,r2 ; r0 = r1 + r2

(ADDAL)

To execute this only if the zero flag is set:ADDEQ r0,r1,r2 ; If zero flag

set then

; r0 = r1 + r2

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Using and updating the Condition Field

By default, data processing operations do not affect the

condition flags (apart from the comparisons where this is

the only effect). To cause the condition flags to be updated, the S bit of the

instruction needs to be set by postfixing the instruction

(and any condition code) with an S.

For example to add two numbers and set the condition

flags:

ADDS r0,r1,r2 ; r0 = r1 + r2

; ... and set flags

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Exception, Interrupts and the Vector Table

The following exceptions can halt the normalsequential execution of instructions-

Data abort

Prefetch abort

Fast interrupt request Interrupt request

Software interrupt

Reset Undefined instructions

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ARM processor exceptions and associated modes:

Fast interrupt request FIQ mode

Interrupt request IRQ mode

SWI and Reset supervisor mode

Data abort & prefetch abort abort mode

Undefined instruction undefined mode

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When an exception occurs the ARM

processor always switches to ARM state.

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Reset: this is the first instruction executed by the processor

when the power is applied.

Initializes the system, sets up stack pointer, memory,external interrupt sources before enabling FIQ and IRQ.

ISR code should be designed to avoid further triggering of

exceptions.

Data Abort: occurs when memory controller indicates that

an invalid memory address has been accessed.

FIQ exception can be raised within data abort handler.

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FIQ

Occurs when an external peripheral generates the FIQ

input signal. Core disables both FIQ and IRQ interrupts.

IRQ

Occurs when an external peripheral generates the IRQ

input signal.

IRQ handler will be entered if neither FIQ or abort

exceptions occur.

On entry IRQ interrupt is disabled.

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Prefetch Abort

Occurs when an attempt to fetch an instruction results in

memory fault.

FIQ interrupt can be serviced.

Undefined instruction

Occurs when the instruction is not an ARM or THUMB

instruction.

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SWI interrupt

SWI vector is called when you execute a SWI instruction.

The SWI instruction is frequently used as the mechanism

to invoke an operating system routine.

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Fast interrupt request0x1C

Interrupt request0x18

Reserved0x14

Data abort0x10

Prefetch abort0x0C

Software interrupt0x08

Undefined instruction0x04

Reset0x00

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Each exception causes the core to enter a specific

mode.

When the exception causes mode change, core

automatically-Saves the cpsrto the spsrof the exception mode

Saves thepc to the lrof the exception mode

Sets the cpsrto the exception modeSetspc to the address of the exception handler.

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To return, exception handler needs to: Restore CPSR from SPSR of exception mode

Restore PC from LR of the exception mode

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Pipeline

The ARM uses a pipeline in order to increase the

speed of the flow of instructions to the processor.

Allows several operations to be undertakensimultaneously, rather than serially.

Rather than pointing to the instruction being

executed, the PC points to the instruction beingfetched.

Pipeline allows the core to execute an instruction

every cycle.

Pi li

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Pipeline

As the pipeline length increases, the amount of

work done at each stage is reduced.

This allows the processor to attain a higheroperating frequency.

This increases the throughput.

The system latency also increases because it takesmore cycles to fill the pipeline before the core can

execute an instruction.

Pipeline

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Pipeline

The execution of a branch instruction or branching

by the direct modification of thepc causes the

ARM core to flush its pipeline. An instruction in the execute stage will complete

even though an interrupt has been raised.

Other instructions in the pipeline will beabandoned, and the processor will start filling the

pipeline from the appropriate entry in the vector

table.

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ARM nomenclature

T- thumb 16 bit decoder D JTAG debug

M fast multiplier

I embedded ICE J - Jazelle

E Enhanced instructions

ARM7TDMI, ARM9T, ARM9E, ARM10E, etc.

ARM-Intro

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