ARM Embedded Systems Design IAC TTT 2
Transcript of ARM Embedded Systems Design IAC TTT 2
ARM Processors andArchitectures
Train The Trainer - IAC
1Copyright © 2014
ARM Processors andArchitectures
Train The Trainer - IAC
ARM Ltd ARM founded in November 1990 Advanced RISC Machines
Company headquarters in Cambridge, UK Processor design centers in Cambridge, Austin, and Sophia Antipolis Sales, support, and engineering offices all over the world
Best known for its range of RISC processor cores designs Other products – fabric IP, software tools, models, cell libraries - to help partners
develop and ship ARM-based SoCs
ARM does not manufacture silicon
More information about ARM and our offices on our web site: http://www.arm.com/aboutarm/
2Copyright © 2014
ARM founded in November 1990 Advanced RISC Machines
Company headquarters in Cambridge, UK Processor design centers in Cambridge, Austin, and Sophia Antipolis Sales, support, and engineering offices all over the world
Best known for its range of RISC processor cores designs Other products – fabric IP, software tools, models, cell libraries - to help partners
develop and ship ARM-based SoCs
ARM does not manufacture silicon
More information about ARM and our offices on our web site: http://www.arm.com/aboutarm/
ARM Worldwide
3Copyright © 2014
ARM Connected Community – 1000+
4Copyright © 2014
More information on the website -http://www.arm.com/community/index.html
Agenda Introduction to ARM Development Tools
Introduction to ARM Processor Architecture
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
5Copyright © 2014
Introduction to ARM Development Tools
Introduction to ARM Processor Architecture
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
Tools Overview
Debug Adapters
ULINKpro ULINK2 ULINK-ME
Development Targets
MCU development boards µVision Simulator
Software Tools
Keil MicrocontrollerDevelopment Kit (MDK)
DS-5 Basic Professional
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Debug Adapters
ULINKpro ULINK2 ULINK-ME
Development Targets
MCU development boards µVision Simulator
Software Tools
Keil MicrocontrollerDevelopment Kit (MDK)
DS-5 Basic Professional
MCU development boards Fast Models
DSTREAM
Keil MDK Low cost tools for ARM7, ARM9, Cortex-M and Cortex-R4 MCUs Extensive device support for many devices Core and peripheral simulation Flash support
Microcontroller Development Kit (MDK) µVision IDE ARM Compiler, optimized run-time library, KEIL RTX RTOS Realtime trace (for Cortex-M3 and Cortex-M4 based devices)
Real-Time Library KEIL RTX RTOS + Source Code TCP networking suit, Flash File System, CAN Driver Library, USB Device Interface
Debug Hardware Evaluation boards
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Low cost tools for ARM7, ARM9, Cortex-M and Cortex-R4 MCUs Extensive device support for many devices Core and peripheral simulation Flash support
Microcontroller Development Kit (MDK) µVision IDE ARM Compiler, optimized run-time library, KEIL RTX RTOS Realtime trace (for Cortex-M3 and Cortex-M4 based devices)
Real-Time Library KEIL RTX RTOS + Source Code TCP networking suit, Flash File System, CAN Driver Library, USB Device Interface
Debug Hardware Evaluation boards
Keil MDK: µVision IDE The µVision Device Database automatically configures the development tools
for the target microcontroller: http://www.keil.com/dd/whatisdd.asp
The µVision IDE integrates additional third-party tools like VCS, CASE, andFLASH/Device Programming
µVision incorporates a project manager, compiler, editor, and debugger in asingle environment
Identical Target Debugger and Simulator User Interface
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Compiler Assembler Linker Format Converter Libraries Librarian
These are all command line tools Easy to script
All tools emit useful statistics e.g. code size, data size, symbol
table, call graph, image memorymap etc. See the documentation
Keil MDK: ARM Compiler
armcc
armasm
armar
object
assembler source
C/C++ source
compile/assemble
object
objects library
link
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Compiler Assembler Linker Format Converter Libraries Librarian
These are all command line tools Easy to script
All tools emit useful statistics e.g. code size, data size, symbol
table, call graph, image memorymap etc. See the documentation
armlink
armar
binary
libraries
fromelf
executable
objects library
image
object
image stats
Keil MDK: µVision Debugger Source and disassembly level debugger Connects to: uVision Simulator Hardware targets, via ULINK
Analysis Tools: Profiler, Logic and Performance Analyzers, Code Coverage
GCC images supported
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source µVision
binary
µVision Simulator
ULINK + Target
image
AgendaIntroduction to ARM Development Tools
Introduction to ARM Processor Architectures
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
11Copyright © 2014
Introduction to ARM Development Tools
Introduction to ARM Processor Architectures
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
ARM Classic Processor Portfolio Classic, market-proven processor technology Instruction set architecture Processor designs
300+ partners 800+ licenses 30Bu+ shipped
ARM968E-S™
ARM1176JZ(F)-S™
ARM1156T2(F)-S™
ARM1136J(F)-S™
x1-4ARM11™ MPCore™ARMv6
ARMv5 ARM1026EJ-S™
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Classic, market-proven processor technology Instruction set architecture Processor designs
300+ partners 800+ licenses 30Bu+ shipped
ARM968E-S™
ARM946E-S™
SC100™
ARM922T™
ARM926EJ-S™
ARM7EJ-S™
ARMv4
ARMv5
ARM920T™
ARM966E-S™
ARM7TDMI(S)™
ARM1022E™
ARM1026EJ-S™
ARM1020E™SC200™
ARM720T™
ARM Cortex Advanced ProcessorsArchitectural compatibility across a wide application range
ARM Cortex™-A family: Applications processors for feature-
rich OS and 3rd party applications
ARM Cortex-R family: Embedded processors for real-time
signal processing, control applications
ARM Cortex-M family: Microcontroller-oriented processors
for MCU, ASSP, and SoC applications ARM SecurCore™ - Tamper-resistant security
Cortex-R7
Cortex-A7
...2.5GHz
Cortex-A5
Cortex-A8Cortex-A9
Cortex-A57
Cortex-A15Cortex-A53
Cortex-A12
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Architectural compatibility across a wide application range
ARM Cortex™-A family: Applications processors for feature-
rich OS and 3rd party applications
ARM Cortex-R family: Embedded processors for real-time
signal processing, control applications
ARM Cortex-M family: Microcontroller-oriented processors
for MCU, ASSP, and SoC applications ARM SecurCore™ - Tamper-resistant security
<12k gates...
SC300
Cortex-M0+
SC000
Cortex-R5Cortex-R4
Cortex-R7
Cortex-M4Cortex-M3Cortex-M1Cortex-M0
On chipmemory
Example of ARM-based System ARM core deeply embedded
within an SoC External debug and trace via JTAG
or CoreSight interface Design can have both external
and internal memories Varying width, speed and size –
depending on system requirements Can include ARM licensed
CoreLink peripherals Interrupt controller, since core only
has two interrupt sources Other peripherals and interfaces
Can include on-chip memory fromARM Artisan Physical IP Libraries
Elements connected using AMBA(Advanced Microcontroller BusArchitecture)
ARMProcessorcore
AMB
A AX
I
ExternalMemoryInterface
DMAPort
Clocks andReset Controller
DEBUG
nIRQnFIQ
FLASH
SDRAM
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On chipmemory
ARM core deeply embeddedwithin an SoC External debug and trace via JTAG
or CoreSight interface Design can have both external
and internal memories Varying width, speed and size –
depending on system requirements Can include ARM licensed
CoreLink peripherals Interrupt controller, since core only
has two interrupt sources Other peripherals and interfaces
Can include on-chip memory fromARM Artisan Physical IP Libraries
Elements connected using AMBA(Advanced Microcontroller BusArchitecture)
APBBridge
AMB
A AP
B
CoreLinkInterruptController
OtherCoreLinkPeripherals
nIRQnFIQ
ARM based SoCCustomPeripherals
Development of the ARM Architecture
v4T
Halfword andsigned halfword/ byte support
System mode
Thumbinstruction set
ImprovedARM/ThumbInterworking
CLZSaturatedarithmeticDSP multiply-accumulateinstructions
v5TE v6
SIMD Instructions
Multi-processing
v6 Memory architecture
Unaligned data support
Extensions
Thumb-2 (v6T2)
TrustZone (v6Z)
Multicore (v6K)
Thumb-only (v6-M)
v7
Thumb-2
NEON
TrustZone
Virtualization
Architecture Profiles
v7-A (Applications):NEON
v7-R (Real-time):Hardware divide
v7-M (Microcontroller):Hardware divide, Thumb-only
v8
64-bit registers
Privilege Levels
New exception model
New memory model
New instructions
ARMv7 compatible
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Halfword andsigned halfword/ byte support
System mode
Thumbinstruction set
ImprovedARM/ThumbInterworking
CLZSaturatedarithmeticDSP multiply-accumulateinstructions
SIMD Instructions
Multi-processing
v6 Memory architecture
Unaligned data support
Extensions
Thumb-2 (v6T2)
TrustZone (v6Z)
Multicore (v6K)
Thumb-only (v6-M)
Note that implementations of the same architecture can be different: Cortex-A8 - architecture v7-A with a 13-stage pipeline Cortex-A9 - architecture v7-A with an 8-stage pipeline
Thumb-2
NEON
TrustZone
Virtualization
Architecture Profiles
v7-A (Applications):NEON
v7-R (Real-time):Hardware divide
v7-M (Microcontroller):Hardware divide, Thumb-only
64-bit registers
Privilege Levels
New exception model
New memory model
New instructions
ARMv7 compatible
The ARM Cortex Processor Family ARM Cortex-A15 Processor ARMv7-A architecture with extensions big.LITTLE™ companion to ARM Cortex-A7 600MHz – 1.2GHz @ 2.5DMIPS/MHz NEON, Virtualization, LPAE
ARM Cortex-R7 Processor ARMv7-R architecture High-performance real-time 1.6 DMIPS/MHz @ 400MHz ECC support, dual-core capable
ARM Cortex-M0+ Processor ARMv6-M architecture (Thumb-only) Embedded microcontroller, integrated NVIC 1.25DMIPS/MHz @ 135MHz Programmable entirely in C
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ARM Cortex-A15 Processor ARMv7-A architecture with extensions big.LITTLE™ companion to ARM Cortex-A7 600MHz – 1.2GHz @ 2.5DMIPS/MHz NEON, Virtualization, LPAE
ARM Cortex-R7 Processor ARMv7-R architecture High-performance real-time 1.6 DMIPS/MHz @ 400MHz ECC support, dual-core capable
ARM Cortex-M0+ Processor ARMv6-M architecture (Thumb-only) Embedded microcontroller, integrated NVIC 1.25DMIPS/MHz @ 135MHz Programmable entirely in C
Cortex-M processors
ARMv7-M Processors
ARMv6-M Processors
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ARMv7-M Processors
ARMv6-M Processors
ARMv7-M & ARMv6-M profile overview Cortex-M processors are designed to support the microcontroller market Simpler to program – entire application can be programmed in C Fewer features needed than in application processors
Register and ISA changes from other ARM cores No ARM instruction set support Only one set of registers xPSR has different bits than CPSR
Different modes and exception models Only two modes: Thread mode and Handler mode Vector table is addresses, not instructions Exceptions automatically save state (r0-r3, r12, lr, xPSR, pc) on the stack
Different system control/memory layout Cores have a fixed memory map No coprocessor 15 – controlled through memory mapped control registers
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Cortex-M processors are designed to support the microcontroller market Simpler to program – entire application can be programmed in C Fewer features needed than in application processors
Register and ISA changes from other ARM cores No ARM instruction set support Only one set of registers xPSR has different bits than CPSR
Different modes and exception models Only two modes: Thread mode and Handler mode Vector table is addresses, not instructions Exceptions automatically save state (r0-r3, r12, lr, xPSR, pc) on the stack
Different system control/memory layout Cores have a fixed memory map No coprocessor 15 – controlled through memory mapped control registers
AgendaIntroduction to ARM Development Tools
Introduction to ARM Processor Architectures
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
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Introduction to ARM Development Tools
Introduction to ARM Processor Architectures
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
ARMv6-M and ARMv7-M Core Registers Registers R0-R7 Accessible to all instructions
Registers R8-R12 Accessible to a few 16-bit instructions
Accessible to all 32-bit instructions
R13 is the stack pointer (SP) Cores have two banked versions
R14 is the link register (LR)
R15 is the program counter (PC)
Program Status Registers (xPSR) APSR, EPSR, IPSR
Saved to the stack on an exception
Special-purpose Registers
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
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Registers R0-R7 Accessible to all instructions
Registers R8-R12 Accessible to a few 16-bit instructions
Accessible to all 32-bit instructions
R13 is the stack pointer (SP) Cores have two banked versions
R14 is the link register (LR)
R15 is the program counter (PC)
Program Status Registers (xPSR) APSR, EPSR, IPSR
Saved to the stack on an exception
Special-purpose Registers
R10
R11
R12
xPSR
R13 (SP)
R14 (LR)
R15 (PC)
PRIMASK
FAULTMASK
BASEPRI
CONTROL
ARMv7-M only
Program Counter (PC) The program counter can be used for a number of different reasons such as
changing the flow of the program
Some instructions are allowed to read from the PC For example, PC-relative data addressing
Some instructions are allowed to write to the PC For example, a load instruction with the PC as the destination register Bit [0] of the loaded value selects the execution state (must be set to 1)
Some instructions implicitly access the PC For example, a branch instruction (B<cond>) reads from and writes to the PC
When it is permitted to specify the PC, its value is interpreted differentlydepending on the instruction For example, when read implicitly using a BL instruction, the PC points to the
address of the current instruction + 4
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The program counter can be used for a number of different reasons such aschanging the flow of the program
Some instructions are allowed to read from the PC For example, PC-relative data addressing
Some instructions are allowed to write to the PC For example, a load instruction with the PC as the destination register Bit [0] of the loaded value selects the execution state (must be set to 1)
Some instructions implicitly access the PC For example, a branch instruction (B<cond>) reads from and writes to the PC
When it is permitted to specify the PC, its value is interpreted differentlydepending on the instruction For example, when read implicitly using a BL instruction, the PC points to the
address of the current instruction + 4
Link Register (LR) The Link Register (LR) is used to enable returns from subroutines
void func0 (void){
:func1();:
}
func1func0
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Further usage of the LR It has a special function for exception handling
void func0 (void){
:func1();:
}
<func0>LR
Stack Pointer (SP) Usage of a stack is to save register contents in memory The content stored on a stack can be restored for later usage
The Stack Pointer (SP) points to a memory location – the stack
r13 (SP)r13 (SP)0xABCDABCD
0x12345678
register
Push Operation 0x12345678 r13 (SP)
0xABCDABCD
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0x12345678 r13 (SP)
register
0x12345678
Pop Operation
r13 (SP)
0x12345678 r13 (SP)
r13 (SP)
0xABCDABCD
Memory
Program Status Registers
APSR - Application Program Status Register Only ALU flags GE bits only available on Cortex-M4
IPSR - Interrupt Program Status Register Interrupt/Exception Number
EPSR - Execution Program Status Register IT field – If/Then block information ICI field – Interruptible-Continuable Instruction information T bit ( s/b =1, to show core is in Thumb state)
xPSR Composite of the 3 PSRs Stored on the stack on exception entry
31 716 15 024 10 8
N Z C V Q GE[3:0] ISR NumberIT/ICIIT T
2728 232526 19
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APSR - Application Program Status Register Only ALU flags GE bits only available on Cortex-M4
IPSR - Interrupt Program Status Register Interrupt/Exception Number
EPSR - Execution Program Status Register IT field – If/Then block information ICI field – Interruptible-Continuable Instruction information T bit ( s/b =1, to show core is in Thumb state)
xPSR Composite of the 3 PSRs Stored on the stack on exception entry
Bit Field and Register Access in PSR Condition code flags N = Negative result from ALU Z = Zero result from ALU C = ALU operation carry out V = ALU operation overflow Q = Saturated math overflow
IT/ICI bits Contain IF-THEN base condition code or Interrupt Continue information
ISR Number Stacked xPSR shows which exception was pre-empted
T=1 – ARMv7-M always in Thumb state Register Access MRS r0, APSR ; Read Flag state into R0 MRS r0, IPSR ; Read Exception/Interrupt state MRS r0, EPSR ; Read Execution state MSR APSR, r0 ; Write Flag state MRS r0, PSR ; Read the combined program status word MSR PSR, r0 ; Write combined program state word
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Condition code flags N = Negative result from ALU Z = Zero result from ALU C = ALU operation carry out V = ALU operation overflow Q = Saturated math overflow
IT/ICI bits Contain IF-THEN base condition code or Interrupt Continue information
ISR Number Stacked xPSR shows which exception was pre-empted
T=1 – ARMv7-M always in Thumb state Register Access MRS r0, APSR ; Read Flag state into R0 MRS r0, IPSR ; Read Exception/Interrupt state MRS r0, EPSR ; Read Execution state MSR APSR, r0 ; Write Flag state MRS r0, PSR ; Read the combined program status word MSR PSR, r0 ; Write combined program state word
Special Purpose Registers
nPRIV – Defines the execution privilege in Thread mode SPSEL – Defines the stack to be used FPCA – Defines whether the FP extension is active in the current context
Other special purpose registers mask registers are used in managing theprioritization scheme for exceptions and interrupts PRIMASK, FAULTMASK and BASEPRI
012345678910111213141516171819202122232425262728293031
FPCA
SPSEL
nPRIV
The special purpose CONTROL Register is a 2-bit or 3-bit register
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nPRIV – Defines the execution privilege in Thread mode SPSEL – Defines the stack to be used FPCA – Defines whether the FP extension is active in the current context
Other special purpose registers mask registers are used in managing theprioritization scheme for exceptions and interrupts PRIMASK, FAULTMASK and BASEPRI
Modes Overview
ARM Processor
Application Code
ThreadMode
ExceptionEntry
ExceptionReturn
Reset
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Exception Code
HandlerMode
ExceptionEntry
ExceptionReturn
Not shown: Handler mode can also be re-entered on exception return
Privileged Execution Privileged/non-privileged operation Handler mode is always privileged Thread mode can be privileged or non-privileged, depending on the value of
CONTROL.nPRIV
Privileged execution is normally required to manage system resources The memory mapped control registers in the System Control Space (SCS) require
privileged access When code is executing unprivileged, Thread mode can execute an SVC instruction
to generate a supervisor call exception
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Privileged/non-privileged operation Handler mode is always privileged Thread mode can be privileged or non-privileged, depending on the value of
CONTROL.nPRIV
Privileged execution is normally required to manage system resources The memory mapped control registers in the System Control Space (SCS) require
privileged access When code is executing unprivileged, Thread mode can execute an SVC instruction
to generate a supervisor call exception
Stacks Two run-time models supported Single Stack Pointer – MSP for entire application Two Stack Pointers MSP for Handler Mode (Exception Handling) PSP for Thread Mode (Application Code)
Main Stack Pointer (MSP) Used by Thread Mode out of reset Initial MSP value is taken from first entry of Vector Table
Always used by Handler Mode
Process Stack Pointer (PSP) Optionally used for Thread Mode PSP is enabled using CONTROL.SPSEL Must be initialized by user before being used
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Two run-time models supported Single Stack Pointer – MSP for entire application Two Stack Pointers MSP for Handler Mode (Exception Handling) PSP for Thread Mode (Application Code)
Main Stack Pointer (MSP) Used by Thread Mode out of reset Initial MSP value is taken from first entry of Vector Table
Always used by Handler Mode
Process Stack Pointer (PSP) Optionally used for Thread Mode PSP is enabled using CONTROL.SPSEL Must be initialized by user before being used
Reset Sequence
After the processor exits reset, it will read two words from memory Address 0x00000000: Starting value of R13 (the SP) Address 0x00000004: Reset vector (the starting address of program execution) LSB should be set should be set to 1 to indicate Thumb state)
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Initial SP and PC
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reset
Vector Table Definition After Reset
The vector table is an array ofword data inside the systemmemory: each representing the
starting address of oneexception type. The vector table starts after
the initial SP value. The first vector is the reset
vector.
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The vector table is an array ofword data inside the systemmemory: each representing the
starting address of oneexception type. The vector table starts after
the initial SP value. The first vector is the reset
vector.
AgendaIntroduction to the ARM Architecture
Cortex-M Microcontrollers
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
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Introduction to the ARM Architecture
Cortex-M Microcontrollers
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
Instruction Set Support ARMv6-M and ARMv7-M cores implement the Thumb Instruction Set with
Thumb-2 technology Mix of 16-bit and 32-bit instructions – implements almost all of the ARM instruction
set functionality ARMv6-M only supports six 32-bit instructions
Superset of the complete 16-bit Thumb instruction set Load/Store instruction set; no direct manipulation of memory contents Instruction length can vary, depending on functionality
Two optional architecture extensions are available: ARMv7E-M adds DSP instructions Currently supported on Cortex-M4
Single precision floating point instructions Currently supported on Cortex-M4 with Floating-point extension
See the Technical Reference Manual (TRM) for the core for more detail
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ARMv6-M and ARMv7-M cores implement the Thumb Instruction Set withThumb-2 technology Mix of 16-bit and 32-bit instructions – implements almost all of the ARM instruction
set functionality ARMv6-M only supports six 32-bit instructions
Superset of the complete 16-bit Thumb instruction set Load/Store instruction set; no direct manipulation of memory contents Instruction length can vary, depending on functionality
Two optional architecture extensions are available: ARMv7E-M adds DSP instructions Currently supported on Cortex-M4
Single precision floating point instructions Currently supported on Cortex-M4 with Floating-point extension
See the Technical Reference Manual (TRM) for the core for more detail
Binary Upwards Compatibility
ARMv6-MArchitecture
ARMv6-MArchitecture
ARMv7-MArchitecture
ARMv7-MArchitecture
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ARMv6-MArchitecture
ARMv6-MArchitecture
Thumb Instruction Encoding Choice When assembling for an ARMv7-M processor there is often a choice of 16-bit
and 32-bit instruction encodings The assembler will normally generate 16-bit instructions
Thumb instruction width qualifiers Allow you to determine which instruction width the assembler will use Can be placed immediately after instruction mnemonics: .W Forces a 32-bit instruction encoding
.N Forces a 16-bit instruction encoding
Errors raised by assembler if not possible
Disassembly rules One-to-one mapping is defined to ensure correct re-assembly .W or .N suffix used for cases when a bit pattern which doesn’t follow the above
rules is disassembled
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When assembling for an ARMv7-M processor there is often a choice of 16-bitand 32-bit instruction encodings The assembler will normally generate 16-bit instructions
Thumb instruction width qualifiers Allow you to determine which instruction width the assembler will use Can be placed immediately after instruction mnemonics: .W Forces a 32-bit instruction encoding
.N Forces a 16-bit instruction encoding
Errors raised by assembler if not possible
Disassembly rules One-to-one mapping is defined to ensure correct re-assembly .W or .N suffix used for cases when a bit pattern which doesn’t follow the above
rules is disassembled
Data Processing Instructions These instructions operate on the contents of registers They DO NOT affect memory Except for the comparison instructions, they do not set the condition code flags No conditional execution – ARMv7-M provides the IT (If-Then) instruction
arithmetic logical
manipulation(has destination
register)
ADC SBC
RSB
BIC EOR
ORN
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These instructions operate on the contents of registers They DO NOT affect memory Except for the comparison instructions, they do not set the condition code flags No conditional execution – ARMv7-M provides the IT (If-Then) instruction
manipulation(has destination
register)ADD SUB
SBC
RSB
AND ORR
EOR
ORN
comparison(set flags only)
CMN(ADDS)
CMP(SUBS)
TST(ANDS)
TEQ(EORS)
ARMv6-M
ARMv6-M
Data Processing Instruction Examples MOV r3, r0 ; copies r0 into r3
MVN r6, r8 ; copies the complement of r8 into r6
ADD r0, r1, r2 ; r0 = r1 + r2
ADC r0, r1, r2 ; r0 = r1 + r2 + <carry flag>
SUB r3, r1, r7 ; r3 = r1 – r7
RSB r3, r1, r7 ; r3 = r7 – r1
SBC r3, r1, r7 ; r3 = r1 – (r7 + <carry flag>)
AND r0, r1, #0xA5 ; r0 = r1 & 0xA5
BIC r0, r1, #0xA5 ; r0 = r1 with bits 0,2,5,and 7 cleared
ORR r0, r1, #0xA5 ; r0 = r1 with bits 0,2,5,and 7 set
CMP r5, r9 ; same as SUBS, but only affects APSR
CMN r0, r1 ; same as ADDS, but only affects APSR
TST r0, r1 ; same as ANDS, but only affects APSR
TEQ r0, r1 ; same as EORS, but only affects APSR
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MOV r3, r0 ; copies r0 into r3
MVN r6, r8 ; copies the complement of r8 into r6
ADD r0, r1, r2 ; r0 = r1 + r2
ADC r0, r1, r2 ; r0 = r1 + r2 + <carry flag>
SUB r3, r1, r7 ; r3 = r1 – r7
RSB r3, r1, r7 ; r3 = r7 – r1
SBC r3, r1, r7 ; r3 = r1 – (r7 + <carry flag>)
AND r0, r1, #0xA5 ; r0 = r1 & 0xA5
BIC r0, r1, #0xA5 ; r0 = r1 with bits 0,2,5,and 7 cleared
ORR r0, r1, #0xA5 ; r0 = r1 with bits 0,2,5,and 7 set
CMP r5, r9 ; same as SUBS, but only affects APSR
CMN r0, r1 ; same as ADDS, but only affects APSR
TST r0, r1 ; same as ANDS, but only affects APSR
TEQ r0, r1 ; same as EORS, but only affects APSR
Generating Data Processing Instructions
int foo(int a, int b, int c, int d){int x, y;x = a + b;y = c - d;if(x > y){return x = a & 0xAA;
}else{return y = c | 0x55;
}}
PUSH {r4,lr}ADDS r4,r0,r1 ; r4 = r0 + r1SUBS r1,r2,r3 ; r1 = r2 – r3CMP r4,r1 ; same as SUBS but
; only affects APSRBLE |L0.16|AND r0,r0,#0xaa ; r0 = r0 & 0xaaPOP {r4,pc}
|L0.16|ORR r0,r2,#0x55 ; r0 = r2 | 0x55POP {r4,pc}
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int foo(int a, int b, int c, int d){int x, y;x = a + b;y = c - d;if(x > y){return x = a & 0xAA;
}else{return y = c | 0x55;
}}
PUSH {r4,lr}ADDS r4,r0,r1 ; r4 = r0 + r1SUBS r1,r2,r3 ; r1 = r2 – r3CMP r4,r1 ; same as SUBS but
; only affects APSRBLE |L0.16|AND r0,r0,#0xaa ; r0 = r0 & 0xaaPOP {r4,pc}
|L0.16|ORR r0,r2,#0x55 ; r0 = r2 | 0x55POP {r4,pc}
Example built with: –-cpu Cortex-M3
Shift Operations
registerCF 0
LSL: Logical Shift Left
register CF
ASR: Arithmetic Shift Right
Division by a power of 2,preserving the sign bit
int dest2;…dest2 = dest2 << 8;
LSL r9,r9,#8
int dest1;…dest1 = dest1 >> 4;
ASR r8,r8,#4
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These are also available as part of the flexible second operand
registerCF 0
Multiplication by a power of 2
register CF...0
LSR: Logical Shift Right
Division by a power of 2
int dest2;…dest2 = dest2 << 8;
LSL r9,r9,#8
unsigned int dest3;…dest3 = dest3 >> 4;
LSR r10,r10,#4
Rotate Operations
register CF
ROR: Rotate Right
Bit rotate with wrap aroundfrom LSB to MSB
dest1 = __ror(op1,4);ROR r8,r4,#4
__asm int rrx_func(int source){
RRX r0,r0}
int dest, source;…dest1 = rrx_func(source);
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These are also available as part of the flexible second operand
register
RRX: Rotate Right Extended
Single bit rotate with wrap aroundfrom CF to MSB
CF
__asm int rrx_func(int source){
RRX r0,r0}
int dest, source;…dest1 = rrx_func(source);
For many instructions the second operand is flexible Either a register with optional shift Or an immediate constant
Register, with optional shift Shift distance can be a 5-bit unsigned integer
Can be used for multiplication by constant:
Operand1
BarrelShifter
Operand2
Flexible Second Operand - Register
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Result
ALU
int op1, op2, dest1, dest2;…dest1 = op1 * 3;
ADD r8,r4,r4,LSL #1
dest2 = dest1 – op2 * 8;SUB r9,r8,r5,LSL #3
Branch Instructions Branch instructions have the following format B{<cond>} label
Branch range depends on instruction set and width Assembler works out the offset of the label from the PC for the branch instruction
B start
MOV r0, r1
lab1
ADD r0, #1
..
..
start
CMP r0, r1
..
perform PC relative branch to label “start”
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Branch instructions have the following format B{<cond>} label
Branch range depends on instruction set and width Assembler works out the offset of the label from the PC for the branch instruction
B start
MOV r0, r1
lab1
ADD r0, #1
..
..
start
CMP r0, r1
..
continue execution from here
Subroutines: Branch with Link Implementing a conventional subroutine call requires two steps Store the return address Branch to the address of the required subroutine
These steps are carried out in one instruction, BL The return address is stored in the link register (lr/r14) Branch to an address (range dependent on instruction set and width)
Returning is performed by restoring the program counter (pc) from lr
On other ARM cores, the Branch Exchange instructions – BX and BLX – areused for interworking
func1 func2
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Implementing a conventional subroutine call requires two steps Store the return address Branch to the address of the required subroutine
These steps are carried out in one instruction, BL The return address is stored in the link register (lr/r14) Branch to an address (range dependent on instruction set and width)
Returning is performed by restoring the program counter (pc) from lr
On other ARM cores, the Branch Exchange instructions – BX and BLX – areused for interworking
:BL func2
::
BX lr
func1 func2void func1(void){
:func2();:
}
Use to move data between one or two registers and memoryLDRD STRD DoublewordLDR STR Word
LDRB STRB ByteLDRH STRH HalfwordLDRSB Signed byte loadLDRSH Signed halfword load
Syntax LDR{<size>}{<cond>} Rd, <address>
STR{<size>}{<cond>} Rd, <address>
Example
Single/Double Register Data Transfer
Any remaining spacezero filled or sign extended
Memory
Rd31 0
ARMv6-M
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Use to move data between one or two registers and memoryLDRD STRD DoublewordLDR STR Word
LDRB STRB ByteLDRH STRH HalfwordLDRSB Signed byte loadLDRSH Signed halfword load
Syntax LDR{<size>}{<cond>} Rd, <address>
STR{<size>}{<cond>} Rd, <address>
Example
Any remaining spacezero filled or sign extendedRd
short *sptr = source_addr;char *cptr = dest_addr;*cptr = *sptr;
LDRH r0,[r0,#0]STRB r0,[r1,#0]
The address accessed by LDR/STR is specified by a base registerwith an optional offset Base register only (no offset)
LDR r0, [r1]
Base register plus constantLDR r0, [r1, #8]
Base register, plus register (optionally shifted by an immediate value)LDR r0, [r1, r2]LDR r0, [r1, r2, LSL #2]
The offset can be either added orsubtracted from the base registerLDR r0, [r1, #-8]LDR r0, [r1, -r2]LDR r0, [r1, -r2, LSL #2]
Addressing Memory
r2, LSL #2
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The address accessed by LDR/STR is specified by a base registerwith an optional offset Base register only (no offset)
LDR r0, [r1]
Base register plus constantLDR r0, [r1, #8]
Base register, plus register (optionally shifted by an immediate value)LDR r0, [r1, r2]LDR r0, [r1, r2, LSL #2]
The offset can be either added orsubtracted from the base registerLDR r0, [r1, #-8]LDR r0, [r1, -r2]LDR r0, [r1, -r2, LSL #2]
+/-r1 #8
r0
memory
address
r2, LSL #2
or
Pre- and Post-Indexed Addressing Post-indexed (add offset after
memory access)LDR r0, [r1], #12
Pre-indexed (add offset beforememory access)
LDR r0, [r1, #12]{!}
+r1 #12
memory
address
r1
memory
address
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r0
memory
r0
memory
+r1
#12
r1
If ‘!’ present, update base register (r1) Always update base register (r1)
+r1
#12
r1
Multiple Register Data Transfer These instructions move data between multiple registers and memory Syntax
<LDM|STM>{<addressing_mode>}{<cond>} Rb{!}, <register list>
4 addressing modes Increment after/before Decrement after/before
AlsoPUSH/POP, equivalent to STMDB/LDMIA with SP! as base register
ExampleLDM r10, {r0,r1,r4} ; load registers, using r10 base
PUSH {r4-r6,pc} ; store registers, using SP base
(IA)
r1 IncreasingAddress
r4
r0
r1r4
r0r4r10
IB DA DB
Base Register (Rb)
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These instructions move data between multiple registers and memory Syntax
<LDM|STM>{<addressing_mode>}{<cond>} Rb{!}, <register list>
4 addressing modes Increment after/before Decrement after/before
AlsoPUSH/POP, equivalent to STMDB/LDMIA with SP! as base register
ExampleLDM r10, {r0,r1,r4} ; load registers, using r10 base
PUSH {r4-r6,pc} ; store registers, using SP base
IncreasingAddressr0
r1r4
r0 r1r4
r0
r10Base Register (Rb)
LDR= Examples
PC- or register-relative constantsADR Rn, label
Add or subtract an immediate valueto or from the PC to generate theaddress of the label into thespecified register, using oneinstruction ADRL pseudo instruction uses two
instructions, giving a better range Can be used to generate addresses
for position independent code (butonly if in same code section)
Constant determined at run time
Absolute constantsLDR Rn, =<constant>LDR Rn, =label
Pseudo instruction Assembler will use optimal sequence to
generate constant into specified register(one of MOV, MVN or an LDR from aliteral pool) Can load to the PC, causing a branch Use for absolute addressing and
references outside the current section(resulting in position dependent code) Constant determined at assembly or
link time
The assembler provides some instructions for loading values intoregisters These are the recommended mechanisms for loading constants into registers
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PC- or register-relative constantsADR Rn, label
Add or subtract an immediate valueto or from the PC to generate theaddress of the label into thespecified register, using oneinstruction ADRL pseudo instruction uses two
instructions, giving a better range Can be used to generate addresses
for position independent code (butonly if in same code section)
Constant determined at run time
Absolute constantsLDR Rn, =<constant>LDR Rn, =label
Pseudo instruction Assembler will use optimal sequence to
generate constant into specified register(one of MOV, MVN or an LDR from aliteral pool) Can load to the PC, causing a branch Use for absolute addressing and
references outside the current section(resulting in position dependent code) Constant determined at assembly or
link time
Instructions for Loading Constants The following examples show how the LDR= pseudo instruction
makes code more readable, portable and flexible
LDR r0, =0x2543
LDR r0, =0xFFFF43FF
LDR r0, =0xFFFFF5
MOV r0, #0x2543
MVN r0, #0xBC00
LDR r0, [pc, #xx]
...
DCD 0xFFFFF5
DisassemblyCode
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LDR r0, =0x2543
LDR r0, =0xFFFF43FF
LDR r0, =0xFFFFF5
MOV r0, #0x2543
MVN r0, #0xBC00
LDR r0, [pc, #xx]
...
DCD 0xFFFFF5
Instruction Set Examples: Data Processing:
MOV r2, r5 ; r2 = r5
ADD r5, #0x24 ; r5 = r5 + 36
ADD r2, r3, r4, LSL #2 ; r2 = r3 + (r4 * 4)
LSL r2, #3 ; r2 = r2 * 8
MOVT r9, #0x1234 ; upper halfword of r9 = #0x1234
MLA r0, r1, r2, r3 ; r0 = (r1 * r2) + r3
Memory Access:STRB r2, [r10, r1] ; store lower byte in r2 at
address {r10 + r1}
LDR r0, [r1, r2, LSL #2] ; load r0 with data at address{r1 + r2 * 4}
Program Flow:BL <label> ; PC relative branch to <label>
location, and return addressstored in LR (r14)
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Data Processing:MOV r2, r5 ; r2 = r5
ADD r5, #0x24 ; r5 = r5 + 36
ADD r2, r3, r4, LSL #2 ; r2 = r3 + (r4 * 4)
LSL r2, #3 ; r2 = r2 * 8
MOVT r9, #0x1234 ; upper halfword of r9 = #0x1234
MLA r0, r1, r2, r3 ; r0 = (r1 * r2) + r3
Memory Access:STRB r2, [r10, r1] ; store lower byte in r2 at
address {r10 + r1}
LDR r0, [r1, r2, LSL #2] ; load r0 with data at address{r1 + r2 * 4}
Program Flow:BL <label> ; PC relative branch to <label>
location, and return addressstored in LR (r14)
Further Instruction Set Information You should also be familiar with…
Load and store multiple (LDM/STM) Supervisor call (SVC) Special-purpose register access (MSR/MRS) Multiply (MUL/MLA) Divide (UDIV/SDIV) Bit manipulation (BFC/BFI etc) Loading constants into registers (MOVW/MOVT, LDR=) Control flow (CBZ/CBNZ, IT, TBB/TBH) Load and store exclusive (LDREX/STREX) Saturated arithmetic (QADD etc) Sleep control (WFI/WFE/SEV)
All information can be found in the ARMv6-M and ARMv7-M ArchitectureReference Manuals
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You should also be familiar with…
Load and store multiple (LDM/STM) Supervisor call (SVC) Special-purpose register access (MSR/MRS) Multiply (MUL/MLA) Divide (UDIV/SDIV) Bit manipulation (BFC/BFI etc) Loading constants into registers (MOVW/MOVT, LDR=) Control flow (CBZ/CBNZ, IT, TBB/TBH) Load and store exclusive (LDREX/STREX) Saturated arithmetic (QADD etc) Sleep control (WFI/WFE/SEV)
All information can be found in the ARMv6-M and ARMv7-M ArchitectureReference Manuals
AgendaIntroduction to ARM Development Tools
Introduction to ARM Processor Architectures
Cortex-M Microcontrollers
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
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Introduction to ARM Development Tools
Introduction to ARM Processor Architectures
Cortex-M Microcontrollers
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
Exception Handling Exception types: Reset Non-maskable Interrupt (NMI) Faults PendSV SVCall External Interrupts (IRQs) SysTick Interrupt
Exceptions processed in Handler mode (except Reset) Exceptions always run privileged
ARMv6-M and ARMv7-M exception handling reduces software overhead Automatic save and restore of processor registers (xPSR, PC, LR, R12, R3-R0) Allows handler to be written entirely in ‘C’
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Exception types: Reset Non-maskable Interrupt (NMI) Faults PendSV SVCall External Interrupts (IRQs) SysTick Interrupt
Exceptions processed in Handler mode (except Reset) Exceptions always run privileged
ARMv6-M and ARMv7-M exception handling reduces software overhead Automatic save and restore of processor registers (xPSR, PC, LR, R12, R3-R0) Allows handler to be written entirely in ‘C’
Exception Types Exceptions can be caused by various events Internal External
ARM Processor
ThreadMode
Application CodeInternalExceptions
ExternalExceptions
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ThreadMode
HandlerMode
Exception Code
SVCPendSVFaultsSysTick
InternalExceptions
ResetInterruptsFaults
ExternalExceptions
Processor Mode Usage Processor mode may change when exceptions occur Thread Mode is entered on Reset Handler Mode is entered on all other exceptions
ARM Processor
ThreadMode
Application CodeReset
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ThreadMode
HandlerMode
Exception Code
SVCPendSVFaultsSysTick
ExceptionReturn
Reset
InterruptsFaults
External Interrupts External Interrupts handled by Nested Vectored Interrupt Controller (NVIC) Tightly coupled with processor core
One Non-Maskable Interrupt (NMI) supported Number of external interrupts is implementation-defined ARMv6-M supports up to 32 interrupts ARMv7-M supports up to 512 interrupts
NMI
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……
Cortex-MxProcessor Core
IRQ[0]……IRQ[N]
NMI
NVIC
Cortex-Mx Integration Layer
AgendaIntroduction to ARM Development Tools
Introduction to ARM Processor Architectures
Cortex-M Microcontrollers
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
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Introduction to ARM Development Tools
Introduction to ARM Processor Architectures
Cortex-M Microcontrollers
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
Memory Model ARMv6-M and ARMv7-M describe a memory-mapped architecture
Unaligned accesses are supported in ARMv7-M ARMv6-M does not support unaligned accesses
Internal caches are not supported Memory-mapped system caches are supported
ARMv7-M supports exclusive accesses for synchronization and semaphores ARMv6-M does not support exclusive accesses
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ARMv6-M and ARMv7-M describe a memory-mapped architecture
Unaligned accesses are supported in ARMv7-M ARMv6-M does not support unaligned accesses
Internal caches are not supported Memory-mapped system caches are supported
ARMv7-M supports exclusive accesses for synchronization and semaphores ARMv6-M does not support exclusive accesses
System Address Map ARMv6-M and ARMv7-M describe a memory-mapped architecture Same address view for physical memory and processor control & status registers
Memory is divided into 8 x 512MB segments
System
Device
Device
0xFFFFFFFF
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Device
RAM
RAM
Peripheral
SRAM
Code 512MB0x00000000
Memory Types There are 3 different memory types Normal, Device and Strongly Ordered
Normal memory is the most flexible memory type Suitable for different types of memory, for example, ROM, RAM, Flash and SDRAM Accesses may be restarted Caches and Write Buffers are permitted to work alongside Normal memory
Device memory is suitable for peripherals and I/O devices Caches are not permitted, but write buffers are still supported Unaligned accesses are unpredictable Accesses must not be restarted Load/store multiple instructions should not be used to access Device memory
Strongly ordered memory is similar to Device memory Buffers are not supported and the PPB is marked Strongly Ordered
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There are 3 different memory types Normal, Device and Strongly Ordered
Normal memory is the most flexible memory type Suitable for different types of memory, for example, ROM, RAM, Flash and SDRAM Accesses may be restarted Caches and Write Buffers are permitted to work alongside Normal memory
Device memory is suitable for peripherals and I/O devices Caches are not permitted, but write buffers are still supported Unaligned accesses are unpredictable Accesses must not be restarted Load/store multiple instructions should not be used to access Device memory
Strongly ordered memory is similar to Device memory Buffers are not supported and the PPB is marked Strongly Ordered
Instruction alignment Thumb instructions are 16 or 32 bits wide Thumb instructions must be halfword-aligned
Data alignment Unaligned accesses on an ARMv6-M processor generates a HardFault ARMv7-M supports unaligned data accesses On Cortex-M3/M4 unaligned support is only available for: Load/store singles (LDR, LDRH, STR, STRH) Load/store double supports word aligned accesses, but does not permit other
unaligned accesses and generates a fault if this is attempted
Unaligned accesses may still be trapped via the Configuration and ControlRegister (CCR) UNALIGN_TRP bit Some unaligned accesses are architecturally unpredictable and not
recommended: An unaligned access that crosses a memory map boundary An unaligned access that crosses the bit-band alias
Instruction and Data Alignment
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Instruction alignment Thumb instructions are 16 or 32 bits wide Thumb instructions must be halfword-aligned
Data alignment Unaligned accesses on an ARMv6-M processor generates a HardFault ARMv7-M supports unaligned data accesses On Cortex-M3/M4 unaligned support is only available for: Load/store singles (LDR, LDRH, STR, STRH) Load/store double supports word aligned accesses, but does not permit other
unaligned accesses and generates a fault if this is attempted
Unaligned accesses may still be trapped via the Configuration and ControlRegister (CCR) UNALIGN_TRP bit Some unaligned accesses are architecturally unpredictable and not
recommended: An unaligned access that crosses a memory map boundary An unaligned access that crosses the bit-band alias
Address Map OverviewAddress Name Memory Type(s) XN Cache Description / Supported Memory0xE0000000-0xFFFFFFFF
System Device &Strongly Ordered
XN - Vendor system region (VENDOR_SYS) Private Peripheral Bus (PPB)
0xC0000000-0xDFFFFFFF
Device Device XN - Non-shareable memory
0xA0000000-0xBFFFFFFF
Device Device, Shareable XN - Shareable memory
0x80000000-0x9FFFFFFF
RAM Normal - WT Memory with WT cache attributes
0x60000000-0x7FFFFFFF
RAM Normal - WBWA Write-back, Write-allocate L2/L3
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0x60000000-0x7FFFFFFF
0x40000000-0x5FFFFFFF
Peripheral Device XN - On-chip peripheral address space
0x20000000-0x3FFFFFFF
SRAM Normal - WBWA SRAM On-chip RAM
0x00000000-0x1FFFFFF
Code Normal - WT ROM Flash Memory
XN indicates an eXecute Never region Any attempt to execute code from an XN region faults, generates a HardFault exception
The Cache column indicates the cache policy (write-through or write-back writeallocate) See appendix for more information about caches and cache policies
Cortex-M3/M4 Memory Bus Structure The Bus Matrix partitions memory access via the AHB and PPB buses
The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the fileagain. If the red x still appears, you may have to delete the image and then insert it again.
Bus Matrix
E0000000
E0040000
E0100000
FFFFFFFF
External Peripheral
Debug Components
System (XN)
SCS + NVIC
APB
INTERNAL PPB
The image cannot be displayed. Your computer may not have enough memory to open the image,or the image may have been corrupted. Restart your computer, and then open the file again. If thered x still appears, you may have to delete the image and then insert it again.
ProcessorCore
Instruction
Data
1GB
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DebugSYSTEM AHB
Bus Matrixwith
Bit- BanderAligner
and Patch
Code Space
RAM
Peripheral
External RAM
00000000
20000000
40000000
60000000
A0000000SYSTEM AHB
DCODE AHB
ICODE AHB
INTERNAL PPB
Debug
HX
EX+BB
EX
EX = Code execution support
HX = High performance code execution support
BB = Optional Bit banding support
BB
½GB
½GB
½GB
1GB
System Segment Segment for control & configuration of the processor Including resources like NVIC, System Timer or Debug
Top of memory (511MB) can be used for adding additionalimplementation defined system space
0xFFFFFFFF
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System
0xFFFFFFFF
0xE0000000 Private Peripheral Bus(PPB)
0xE0000000
0xE0100000
VENDOR_SYS
Private Peripheral Bus (PPB)
The internal PPB is a 1MB region It is always accessed as little endian In general registers support word
accesses only Some registers support byte/halfword
accesses Unaligned accesses are not
supported
Private Peripheral Bus(PPB)
0xE0100000
0xE0000000
ROM Table4KB
Reserved0xE00FF000
0xE0040000
ETM
TPIU0xE0041000
0xE0042000
4KB
4KB
Reserved0xE000F000
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The internal PPB is a 1MB region It is always accessed as little endian In general registers support word
accesses only Some registers support byte/halfword
accesses Unaligned accesses are not
supported
System Control Space(SCS)
DWT
FPB
ITM
Reserved0xE000E000
0xE0002000
0xE0001000
0xE00030004KB
4KB
0xE00000004KB
0xE000F000
4KB
System Control Space (SCS) 4KB address space within the PPB
Provides arrays of 32-bit registers Configuration Status Control
0xE000EF90
0xE000ED90MPU
ImplementationDefined
0xE000EFD0
Debug0xE000EDF0
0xE000EF00
0xE000EFFF
SW Triggered Interrupt
μC-specific ID
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System Control Space(SCS)
0xE000F000
0xE000E000
0xE000E000Auxiliary Control
0xE000E010SysTick
0xE000E100NVIC
0xE000ED00System Control Block
0xE000ED90
System Control Block (SCB) Provides configuration registers for
the processor
SHPR1
SHPR2
SHPR3
SHCSR
FSRs & FARs
CPUID
CPACR and FP
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System Control Block(SCB)
0xE000ED90
0xE000ED00
CPUID
ICSR
VTOR
AIRCR
SCR
CCR
SHPR1
SCB Registers overview
SHPR1
SHPR2
SHPR3
SHCSR
FSRs & FARs
CPUID
CPACR and FP
Reserved for other CPUID registers
System Handler Control and State Register
System Handler Priority Register 3
System Handler Priority Register 2
Fault status and address registers
Coprocessor Access Control and FP registers
System Handler Priority Register 1
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CPUID
ICSR
VTOR
AIRCR
SCR
CCR
SHPR1
System Control Register
Application Interrupt and Reset Control Register
Interrupt Control and State Register
CPUID Base Register
Configuration and Control Register
System Handler Priority Register 1
Vector Table Offset Register
AgendaIntroduction to ARM Development Tools
Introduction to ARM Processor Architectures
Cortex-M Microcontrollers
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
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Introduction to ARM Development Tools
Introduction to ARM Processor Architectures
Cortex-M Microcontrollers
Programmers’ Model
Instruction Set
Exception Model
Memory Model
Power Management
Power Management Multiple sleep modes supported - controlled through the NVIC Sleep Now (Wait for interrupt/event) instructions
Sleep On Exit Sleep immediately on return from last ISR
Deep Sleep Long duration sleep, so PLL can be stopped Exports additional output signal SLEEPDEEP
Core may be clock gated in all sleep modes Sleep signal is exported allowing external system to be clock gated also NVIC interrupt Interface stays awake
Wake-Up Interrupt Controller (WIC) External wake-up detector allows core to be fully powered down Effective with State-Retention / Power Gating (SRPG) methodology The WIC is optional
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Multiple sleep modes supported - controlled through the NVIC Sleep Now (Wait for interrupt/event) instructions
Sleep On Exit Sleep immediately on return from last ISR
Deep Sleep Long duration sleep, so PLL can be stopped Exports additional output signal SLEEPDEEP
Core may be clock gated in all sleep modes Sleep signal is exported allowing external system to be clock gated also NVIC interrupt Interface stays awake
Wake-Up Interrupt Controller (WIC) External wake-up detector allows core to be fully powered down Effective with State-Retention / Power Gating (SRPG) methodology The WIC is optional
ARM Processors andArchitectures
Train The Trainer - IAC
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ARM Processors andArchitectures
Train The Trainer - IAC
ARM Cortex-MAdvanced Features
Train The Trainer - IAC
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ARM Cortex-MAdvanced Features
Train The Trainer - IAC
Agenda Exceptions Model
Exception Handling
Prioritization and Control
Writing Interrupt Handlers
Memory Protection Unit (MPU) Initialization
SysTick Calibration
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Exceptions Model
Exception Handling
Prioritization and Control
Writing Interrupt Handlers
Memory Protection Unit (MPU) Initialization
SysTick Calibration
Exception Handling Overview ARMv7-M and ARMv6-M exception handling is very different from other
ARM architectures
Designed for microcontroller applications Support for many interrupt sources Efficient handling of nested interrupts Flexible interrupt architecture (highly configurable) Built in RTOS support
Main Features Nested Vector Interrupt Controller (NVIC) Micro-coded architecture handles the “dirty work” No software overhead for Interrupt Entry/Exit and Interrupt Nesting
Only one mode and one stack for all exception handling Handler mode / Main stack
Easy to program All exception handlers may be coded in “C”
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ARMv7-M and ARMv6-M exception handling is very different from otherARM architectures
Designed for microcontroller applications Support for many interrupt sources Efficient handling of nested interrupts Flexible interrupt architecture (highly configurable) Built in RTOS support
Main Features Nested Vector Interrupt Controller (NVIC) Micro-coded architecture handles the “dirty work” No software overhead for Interrupt Entry/Exit and Interrupt Nesting
Only one mode and one stack for all exception handling Handler mode / Main stack
Easy to program All exception handlers may be coded in “C”
Micro-coded Exception Mechanism Exception architecture designed for low latency
Exception prioritization mechanism is built into NVIC
Exception entry/exit is “micro-coded” – controlled by hardware Automatically saves and restores processor context
Allows late determination of highest priority pending interrupt
Allows another pending interrupt to be serviced without a full restore/save ofprocessor state (tail-chaining)
Interrupt Service Routines (ISRs) can be written entirely in C
Some multi-cycle instructions are interruptible for improved exceptionlatency
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Exception architecture designed for low latency
Exception prioritization mechanism is built into NVIC
Exception entry/exit is “micro-coded” – controlled by hardware Automatically saves and restores processor context
Allows late determination of highest priority pending interrupt
Allows another pending interrupt to be serviced without a full restore/save ofprocessor state (tail-chaining)
Interrupt Service Routines (ISRs) can be written entirely in C
Some multi-cycle instructions are interruptible for improved exceptionlatency
Pre-emption Pre-emption occurs when a task is abandoned in order to handle an
exception
The currently running instruction stream is pre-empted
Pre-emption rules When multiple exceptions with the same priority are pending, the one with the lowest
exception number takes place Once an exception is active, only exceptions with a higher priority can pre-empt it
“Late arrival” is a little different In this case, a higher-priority exception takes the place of a lower one after the
exception entry sequence has started More later...
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Pre-emption occurs when a task is abandoned in order to handle anexception
The currently running instruction stream is pre-empted
Pre-emption rules When multiple exceptions with the same priority are pending, the one with the lowest
exception number takes place Once an exception is active, only exceptions with a higher priority can pre-empt it
“Late arrival” is a little different In this case, a higher-priority exception takes the place of a lower one after the
exception entry sequence has started More later...
Exception Handling Example
Higher Priority
IRQ2
IRQ1
IRQ3
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Core Execution
Base CPU
Foreground ISR2 ISR1 ISR2 Foreground
Time
IRQ3
ISR3(ISR 2 resumes)
Exception Model Core begins execution with a “base level of execution priority” At reset all interrupts are disabled The base execution priority level has a lower priority than the lowest
programmable priority level, so any enabled interrupt will pre-empt the core
When an enabled interrupt is asserted Interrupt is taken (serviced by interrupt handler) Core runs the handler at the execution priority level of the interrupt When interrupt handler completes, original priority level is restored
When an enabled interrupt is asserted with lower or equal priority Interrupt is “pended” to run (when it has sufficient priority)
When a disabled interrupt is asserted Interrupt is “pended” to run (when it is enabled and has sufficient priority)
Interrupt nesting is always enabled To avoid nesting set all interrupts to the same priority
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Core begins execution with a “base level of execution priority” At reset all interrupts are disabled The base execution priority level has a lower priority than the lowest
programmable priority level, so any enabled interrupt will pre-empt the core
When an enabled interrupt is asserted Interrupt is taken (serviced by interrupt handler) Core runs the handler at the execution priority level of the interrupt When interrupt handler completes, original priority level is restored
When an enabled interrupt is asserted with lower or equal priority Interrupt is “pended” to run (when it has sufficient priority)
When a disabled interrupt is asserted Interrupt is “pended” to run (when it is enabled and has sufficient priority)
Interrupt nesting is always enabled To avoid nesting set all interrupts to the same priority
Exception Behavior
Exception Handler
Exception Vector
2
3
Main
1
4
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1. Exception occurs Current instruction stream stops Processor accesses vector table
2. Vector address for the exception loaded from the vector table3. Exception handler executes in Handler Mode4. Exception handler returns to main (assuming no nesting – more later)
Exception Vector
Exception States Exceptions can be in the following states Inactive: Not Pending or Active Pending: Exception event has been generated but processing has not started yet Active: Exception processing has been started but is not complete yet An exception handler can interrupt the execution of another exception handler. In this
case both exceptions are in the active state.
Active and Pending: The exception is being serviced by the processor and there isa pending exception from the same source
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Exceptions can be in the following states Inactive: Not Pending or Active Pending: Exception event has been generated but processing has not started yet Active: Exception processing has been started but is not complete yet An exception handler can interrupt the execution of another exception handler. In this
case both exceptions are in the active state.
Active and Pending: The exception is being serviced by the processor and there isa pending exception from the same source
Inactive
Pending
Active &Pending
Active
Exception Entry Behavior (1) When receiving an interrupt the processor will finish the current instruction
for most instructions To minimize interrupt latency, the processor can take an interrupt during the
execution of a multi-cycle instruction - see next slide
Processor state automatically saved to the current stack 8 registers are pushed: PC, R0-R3, R12, LR, xPSR Follows ARM Architecture Procedure Calling Standard (AAPCS)
During (or after) state saving the address of the ISR is read from the VectorTable
Link Register is modified for interrupt return
First instruction of ISR executed For Cortex-M3 or Cortex-M4 the total latency is normally 12 cycles, however,
interrupt late-arrival and interrupt tail-chaining can improve IRQ latency
ISR executes from Handler mode with Main stack
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When receiving an interrupt the processor will finish the current instructionfor most instructions To minimize interrupt latency, the processor can take an interrupt during the
execution of a multi-cycle instruction - see next slide
Processor state automatically saved to the current stack 8 registers are pushed: PC, R0-R3, R12, LR, xPSR Follows ARM Architecture Procedure Calling Standard (AAPCS)
During (or after) state saving the address of the ISR is read from the VectorTable
Link Register is modified for interrupt return
First instruction of ISR executed For Cortex-M3 or Cortex-M4 the total latency is normally 12 cycles, however,
interrupt late-arrival and interrupt tail-chaining can improve IRQ latency
ISR executes from Handler mode with Main stack
Exception Entry Behavior (2) On taking an exception during a multi-cycle instruction the processor either: Continues execution of the instruction after returning from the exception Abandons the instruction and restarts the instruction on returning from the exception
For multi-cycle instructions on the Cortex-M3 and Cortex-M4 processors: Divide, multiply and load/store double instructions are abandoned and restarted Load/store multiple instructions are treated as “exception-continuable instructions”, if
possible The ICI bits in the EPSR are used to hold the continuation state
However, in some situations LDM/STM instructions are abandoned and restarted For example, An LDM/STM instruction within an If-Then block
Architecturally software must not use an LDM/STM to access a volatilelocation The Cortex-M3/M4 processors must not use an LDM/STM to access a volatile
location if it executes inside an IT block it loads the same register as the base register it loads the PC
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On taking an exception during a multi-cycle instruction the processor either: Continues execution of the instruction after returning from the exception Abandons the instruction and restarts the instruction on returning from the exception
For multi-cycle instructions on the Cortex-M3 and Cortex-M4 processors: Divide, multiply and load/store double instructions are abandoned and restarted Load/store multiple instructions are treated as “exception-continuable instructions”, if
possible The ICI bits in the EPSR are used to hold the continuation state
However, in some situations LDM/STM instructions are abandoned and restarted For example, An LDM/STM instruction within an If-Then block
Architecturally software must not use an LDM/STM to access a volatilelocation The Cortex-M3/M4 processors must not use an LDM/STM to access a volatile
location if it executes inside an IT block it loads the same register as the base register it loads the PC
Exception Stacking Foreground stack (Main or Process) used to store the pre-interrupt state
Stack is Full-Descending SP automatically decremented on push SP always points to non-empty value Same behavior as other ARM cores
The stack must be 8-byte aligned AAPCS compliant STKALIGN bit in Configuration and Control
Register should be set to 1 Extra word padded to stack if required
Main stack active after state is saved
ISR can be coded in “C” No prologue code required (no overhead)
Old SP
:<old TOS>
xPSRReturnAddress
LRR12
SP
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Foreground stack (Main or Process) used to store the pre-interrupt state
Stack is Full-Descending SP automatically decremented on push SP always points to non-empty value Same behavior as other ARM cores
The stack must be 8-byte aligned AAPCS compliant STKALIGN bit in Configuration and Control
Register should be set to 1 Extra word padded to stack if required
Main stack active after state is saved
ISR can be coded in “C” No prologue code required (no overhead)
:::
R12R3R2R1R0
0x0
Returning From an Exception The processor can return from an exception with the following instructions
when the PC is loaded with “magic” value of 0xFFFF_FFFX (EXC_RETURN) LDR PC, ….. LDM/POP which includes loading the PC BX LR (most common)
If no exceptions are pending, the foreground state is restored Stack and state specified by EXC_RETURN is used Context restore on Cortex-M3 and Cortex-M4 requires 10 cycles
If another exception is pending, it is serviced if its priority is higher than theforeground’s base priority Tail-chaining may be used to optimize the exception return Latency for servicing new interrupt is only 6 cycles on M3/M4 (state already saved)
If state restore is interrupted, it is abandoned New ISR executed without state saving (original state still intact and valid) Must still fetch new vector and refill pipeline (6-cycle latency on M3/M4)
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The processor can return from an exception with the following instructionswhen the PC is loaded with “magic” value of 0xFFFF_FFFX (EXC_RETURN) LDR PC, ….. LDM/POP which includes loading the PC BX LR (most common)
If no exceptions are pending, the foreground state is restored Stack and state specified by EXC_RETURN is used Context restore on Cortex-M3 and Cortex-M4 requires 10 cycles
If another exception is pending, it is serviced if its priority is higher than theforeground’s base priority Tail-chaining may be used to optimize the exception return Latency for servicing new interrupt is only 6 cycles on M3/M4 (state already saved)
If state restore is interrupted, it is abandoned New ISR executed without state saving (original state still intact and valid) Must still fetch new vector and refill pipeline (6-cycle latency on M3/M4)
Nesting ExampleHigher Priority
Base CPU
IRQ2
IRQ1
Time
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Core Execution
Time
Foreground ISR2 ISR1 ISR2 ForegroundPop Pop
IRQ1 Active
IRQ2 Active
Push Push
10 Cycles for Cortex-M3/M4 13 cycles for Cortex-M0+ 14 cycles for Cortex-M0
Pop 12 cycles for Cortex-M3/M4 15 cycles for Cortex-M0+ 16 cycles for Cortex-M0
Push
Tail Chaining ExampleHigher Priority
Base CPU
IRQ2
IRQ1
Time
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Core Execution Foreground ISR1 ISR2TC Pop
IRQ1 Active IRQ2 Active
Push Foreground
6 cycles on Cortex-M3/M4 11 cycles on Cortex-M0+ 12 cycles on Cortex-M0
TC
Late Arriving ExampleHigher Priority
Base CPU
IRQ2
IRQ1
Time
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Core Execution
Time
Foreground ForegroundPopISR1 ISR2
A pending higher priority exception is handled before an alreadypending lower priority exception even after exception entry sequencehas started
The lower priority exception is handled after the higher priorityexception
Push TC
Pop
Interrupt Arrival During State Restore
Traditional interrupt handlingmust complete stack cycle
Cortex-M3 or Cortex-M4 mayabandon stack operationsdynamically
IRQ1
IRQ2
Higher Priority
26 cycles16 cycles
6 cycles1-10 cycles
Interrupt routine Pop Push Interrupt routine
Interrupt routine TC Interrupt routine
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Cortex-M3 or Cortex-M4 mayabandon stack operationsdynamically
Load Multiple uninterruptible, andhence the core must complete thePOP and then full stack PUSH
POP may be abandoned early ifanother interrupt arrives
If POP is interrupted it only takes 6cycles to enter ISR2 (equivalent toTail-chaining)
ARM7 Cortex-M3 or Cortex-M4
6 cycles1-10 cycles
Agenda Exception Model
Exception Handling
Prioritization and Control
Writing Interrupt Handlers
Memory Protection Unit (MPU) Initialization
SysTick Calibration
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Exception Model
Exception Handling
Prioritization and Control
Writing Interrupt Handlers
Memory Protection Unit (MPU) Initialization
SysTick Calibration
Priority Boosting Priority boosting raises the
base level of execution priority
This feature can be used todisable interrupts and faults
ProgrammableExceptions
0x80
0xC0
LowestPriority
PriorityBoosting
ActivationPrevented
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Priority boosting raises thebase level of execution priority
This feature can be used todisable interrupts and faults
Reset
NMI
Fault
0x00
-1
-2
-3
0x40
HighestPriority
“Base” Execution
Special Purpose Mask Registers There are three methods for masking interrupts and faults
PRIMASK bit sets the execution priority level to 0 Only allows Hard Fault and NMI to pre-empt
FAULTMASK bit sets the execution priority level to -1 Can only be set by an exception handler (auto clears on exception return) Only allows NMI to pre-empt
BASEPRI register sets execution priority level from 1 to N (N=lowest priority) Acts as a general interrupt mask Example BASEPRI = 16 only interrupts with priority levels (-2 to 15) can pre-empt
If BASEPRI = 0 masking is disabled (any enabled interrupt pre-empts the core)
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There are three methods for masking interrupts and faults
PRIMASK bit sets the execution priority level to 0 Only allows Hard Fault and NMI to pre-empt
FAULTMASK bit sets the execution priority level to -1 Can only be set by an exception handler (auto clears on exception return) Only allows NMI to pre-empt
BASEPRI register sets execution priority level from 1 to N (N=lowest priority) Acts as a general interrupt mask Example BASEPRI = 16 only interrupts with priority levels (-2 to 15) can pre-empt
If BASEPRI = 0 masking is disabled (any enabled interrupt pre-empts the core)
ARMv6-M
ARMv6-M
Priority Boosting Instructions BASEPRI is accessed like a Program Status Register
MSR{cond} BASEPRI, Rm ; write BASEPRI
MRS{cond} Rd, BASEPRI ; read BASEPRI
PRIMASK and FAULTMASK map to the classic “I” and “F” flagsCPSID I ; set PRIMASK (disable interrupts)
CPSIE I ; clear PRIMASK (enable interrupts)
CPSID F ; set FAULTMASK (disable faults and interrupts)
CPSIE F ; clear FAULTMASK (enable faults and interrupts)
CMSIS Functions: PRIMASK: __enable_irq(), __disable_irq()
FAULTMASK: __enable_fiq(), __disable_fiq()
BASEPRI: __get_BASEPRI(), __set_BASEPRI(uint32_t value)
Must be in privileged mode to modify execution priority level
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BASEPRI is accessed like a Program Status RegisterMSR{cond} BASEPRI, Rm ; write BASEPRI
MRS{cond} Rd, BASEPRI ; read BASEPRI
PRIMASK and FAULTMASK map to the classic “I” and “F” flagsCPSID I ; set PRIMASK (disable interrupts)
CPSIE I ; clear PRIMASK (enable interrupts)
CPSID F ; set FAULTMASK (disable faults and interrupts)
CPSIE F ; clear FAULTMASK (enable faults and interrupts)
CMSIS Functions: PRIMASK: __enable_irq(), __disable_irq()
FAULTMASK: __enable_fiq(), __disable_fiq()
BASEPRI: __get_BASEPRI(), __set_BASEPRI(uint32_t value)
Must be in privileged mode to modify execution priority level
ARMv7-M Priority Grouping The 8-bit Priority Level is divided into 2 fields Group Priority and Sub-Priority [GROUP.SUB]
Group Priority is the pre-empting priority level Sub-Priority is used only if the Group Priority is the same Exception Number is final tie-breaker If two interrupts have identical priority levels, lowest vector number takes priority
Example 4-bit Group Priority / 4-bit Sub-Priority SysTick is enabled with priority = 0x30 Timer1 is enabled with priority = 0x30 Timer2 is enabled with priority = 0x31 If Timer1 & Timer2 assert simultaneously Timer1 serviced, Timer2 pended If Timer2 is being serviced and Timer1 asserts Timer1 pended If SysTick & Timer1 assert simultaneously SysTick serviced, Timer1 pended
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The 8-bit Priority Level is divided into 2 fields Group Priority and Sub-Priority [GROUP.SUB]
Group Priority is the pre-empting priority level Sub-Priority is used only if the Group Priority is the same Exception Number is final tie-breaker If two interrupts have identical priority levels, lowest vector number takes priority
Example 4-bit Group Priority / 4-bit Sub-Priority SysTick is enabled with priority = 0x30 Timer1 is enabled with priority = 0x30 Timer2 is enabled with priority = 0x31 If Timer1 & Timer2 assert simultaneously Timer1 serviced, Timer2 pended If Timer2 is being serviced and Timer1 asserts Timer1 pended If SysTick & Timer1 assert simultaneously SysTick serviced, Timer1 pended
bit4
SubGroupbit7 bit3 bit0
Group Priority / Sub-Priority Selection
PRIGROUPBinary Point(group.sub)
Group Priority(Pre-empting)
Sub-Priority
Bits Levels Bits Levels
000 7.1 gggggggs 7 128 1 2
001 6.2 ggggggss 6 64 2 4
010 5.3 gggggsss 5 32 3 8
011 4.4 ggggssss 4 16 4 16
100 3.5 gggsssss 3 8 5 32
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Selection made by PRIGROUP in Application Interrupt and Reset Control Reg System-wide configuration applies to all interrupt priorities If less than 8 priority bits implemented, fewer Sub-Priority bits are available Example: 6 priority bits and PRIGROUP = 001 6 Group Bits / 0 Sub-Priority Bits
100 3.5 gggsssss 3 8 5 32
101 2.6 ggssssss 2 4 6 64
110 1.7 gsssssss 1 2 7 128
111 0.8 ssssssss 0 0 8 256
Interrupt Control and Status Bits ENABLE bit (R/W) – is interrupt enabled or disabled?
PENDING bit (R/W) – is interrupt waiting to be serviced? Interrupt is pending if priority is too low or if interrupt is disabled Can set bit to generate an interrupt (if enabled and sufficient priority) Can clear bit to clear a pending interrupt (interrupt will not be serviced)
ACTIVE bit (R only) – is interrupt active or inactive? If interrupts are nested, more than one active bit will be set
PRIORITY bits (R/W) – set the interrupt priority Lower value has higher priority (priority 0 is highest) ARMv6-M: 2 bits (4 levels) ARMv7-M: 3 - 8 bits (8 - 256 levels) May be divided into a group (pre-empt) priority and a sub-group priority (user
defined)
ARMv6-M
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ENABLE bit (R/W) – is interrupt enabled or disabled?
PENDING bit (R/W) – is interrupt waiting to be serviced? Interrupt is pending if priority is too low or if interrupt is disabled Can set bit to generate an interrupt (if enabled and sufficient priority) Can clear bit to clear a pending interrupt (interrupt will not be serviced)
ACTIVE bit (R only) – is interrupt active or inactive? If interrupts are nested, more than one active bit will be set
PRIORITY bits (R/W) – set the interrupt priority Lower value has higher priority (priority 0 is highest) ARMv6-M: 2 bits (4 levels) ARMv7-M: 3 - 8 bits (8 - 256 levels) May be divided into a group (pre-empt) priority and a sub-group priority (user
defined)
ARMv6-M
Agenda Exceptions Model
Exception Handling
Prioritization and Control
Writing Interrupt Handlers
Memory Protection Unit (MPU) Initialization
SysTick Calibration
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Exceptions Model
Exception Handling
Prioritization and Control
Writing Interrupt Handlers
Memory Protection Unit (MPU) Initialization
SysTick Calibration
Writing Interrupt Handlers (1) Clear the interrupt source if required Some may not need to be cleared (like SysTick)
Interrupt nesting always enabled by default No modification needed to interrupt handlers Just be careful of Main stack overflows
STKALIGN bit should be set to 1 to ensure 8-byte stack alignment onexception entry Bit 9 in the Configuration and Control Register The reset value is an implementation option for: Cortex-M3 r2p1 and later All revisions of Cortex-M4
The reset value is 1 for Cortex-M3 r2p0 The reset value is 0 for Cortex-M3 r1p1 and earlier Always reads as 1 in Cortex-M0 and Cortex-M0+
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Clear the interrupt source if required Some may not need to be cleared (like SysTick)
Interrupt nesting always enabled by default No modification needed to interrupt handlers Just be careful of Main stack overflows
STKALIGN bit should be set to 1 to ensure 8-byte stack alignment onexception entry Bit 9 in the Configuration and Control Register The reset value is an implementation option for: Cortex-M3 r2p1 and later All revisions of Cortex-M4
The reset value is 1 for Cortex-M3 r2p0 The reset value is 0 for Cortex-M3 r1p1 and earlier Always reads as 1 in Cortex-M0 and Cortex-M0+
Writing Interrupt Handlers (2) C Code is recommended for all handlers ISR function must be type void and can not accept arguments The __irq keyword is optional (but recommended for clarity)
__irq void SysTickHandler (void) {
}
No special assembly language entry and exit code required
Writing handlers in assembly Must manually save and restore any non-scratch registers which are used R4, R5, R6, R7, R8, R9, R10, R11, LR
Must maintain 8-byte stack alignment if making function calls Must return from interrupt using EXC_RETURN with proper instruction LDR PC, ….. LDM/POP which includes loading the PC BX LR
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C Code is recommended for all handlers ISR function must be type void and can not accept arguments The __irq keyword is optional (but recommended for clarity)
__irq void SysTickHandler (void) {
}
No special assembly language entry and exit code required
Writing handlers in assembly Must manually save and restore any non-scratch registers which are used R4, R5, R6, R7, R8, R9, R10, R11, LR
Must maintain 8-byte stack alignment if making function calls Must return from interrupt using EXC_RETURN with proper instruction LDR PC, ….. LDM/POP which includes loading the PC BX LR
Interrupt Management Read from CLRPENDx / SETPENDx to determine if IRQ is pended Consider writing to CLRPENDx, for example, before enabling an IRQ Read from ACTIVEx to determine if a specific ISR is active
Interrupt Program Status Register (IPSR) shows current active ISR
Interrupt Control and State Register contains more information
Bit 08
ISR NumberIPSR5
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Read from CLRPENDx / SETPENDx to determine if IRQ is pended Consider writing to CLRPENDx, for example, before enabling an IRQ Read from ACTIVEx to determine if a specific ISR is active
Interrupt Program Status Register (IPSR) shows current active ISR
Interrupt Control and State Register contains more information
0xE000ED04Bit 011 812
VECTPENDING VECTACTIVER2122
P
P = ISRPENDING – Set if an interrupt is Pending VECTPENDING – Interrupt number of highest pending ISR R = RETTOBASE – Return to Base, set if number of active exceptions = 1 VECTACTIVE – Interrupt number of the current executing ISR
Same as Interrupt Program Status Register (IPSR)
AgendaException Model
Exception Handling
Prioritization and Control
Writing Interrupt Handlers
Memory Protection Unit (MPU) Initialization
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Regions Overview Each region consists of: Base address Region Attribute and Size Memory Type and Access Control
The base address must always be aligned to the region size The lowest region size in PMSAv6 is 256 bytes and in PMSAv7 it is 32 bytes At least one region must be defined (or PRIVDEFENA set) before enabling
the MPU No regions defined or enabled after reset Accesses that do not fall into any region cause an abort, unless privileged and
PRIVDEFENA is set If HFNMIENA bit set, MPU is enabled while servicing HardFault/NMI exception Region 0 lowest priority Code enabling MPU must be included in an executable region Otherwise, core will continually abort
If MPU enabled, only PPB and vector table loads are guaranteed to be available Other accesses depend upon region settings and PRIVDEFENA
MPU regions are set up through the MPU registers in the SCS
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Each region consists of: Base address Region Attribute and Size Memory Type and Access Control
The base address must always be aligned to the region size The lowest region size in PMSAv6 is 256 bytes and in PMSAv7 it is 32 bytes At least one region must be defined (or PRIVDEFENA set) before enabling
the MPU No regions defined or enabled after reset Accesses that do not fall into any region cause an abort, unless privileged and
PRIVDEFENA is set If HFNMIENA bit set, MPU is enabled while servicing HardFault/NMI exception Region 0 lowest priority Code enabling MPU must be included in an executable region Otherwise, core will continually abort
If MPU enabled, only PPB and vector table loads are guaranteed to be available Other accesses depend upon region settings and PRIVDEFENA
MPU regions are set up through the MPU registers in the SCS
Sub-regions Each individual region can be split into 8 equal sized non-overlapping sub-
regions Allows the granularity of protection and memory attributes to be increased without
significant increase in hardware complexity Reduces the number of regions which must be used to align protection boundaries
to non-aligned addresses
Each region has 8 sub-region disable bits Sub-region disable bit=0, sub region described as part of the region Protection and memory type attributes of the region apply to that sub-region
Sub-region disable bit=1, sub region described as not part of the region Address covered by that sub-region is not matched as part of the region
Region sizes supported 256bytes to 4Gbytes All region sizes between 256bytes and 4Gbytes support 8 sub-regions
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Each individual region can be split into 8 equal sized non-overlapping sub-regions Allows the granularity of protection and memory attributes to be increased without
significant increase in hardware complexity Reduces the number of regions which must be used to align protection boundaries
to non-aligned addresses
Each region has 8 sub-region disable bits Sub-region disable bit=0, sub region described as part of the region Protection and memory type attributes of the region apply to that sub-region
Sub-region disable bit=1, sub region described as not part of the region Address covered by that sub-region is not matched as part of the region
Region sizes supported 256bytes to 4Gbytes All region sizes between 256bytes and 4Gbytes support 8 sub-regions
Further MPU information Candidates should make themselves familiar with… Region overlapping and sub regions Memory types and type extensions Access permissions MPU programming optimization using MPU Alias Registers
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ARM Cortex-MAdvanced Features
Train The Trainer - IAC
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ARM Cortex-MAdvanced Features
Train The Trainer - IAC
Embedded Programmingfor Cortex M
Train The Trainer - IAC
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Embedded Programmingfor Cortex M
Train The Trainer - IAC
Agenda
ARMv7-M Architecture Programmer Overview
CMSIS
CMSIS-CORE Startup and System Initialization
Post Startup Initialization
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ARMv7-M Architecture Programmer Overview
CMSIS
CMSIS-CORE Startup and System Initialization
Post Startup Initialization
Global microcontroller standard, Created by ARM and licensed to partners(NXP, TI, Freescale, Atmel, ST etc.)
ARM is fabless - Different vendors implement variation of microcontrollerbased on ARM IP
RISC low power, upwards compatibility, M0 M1 M3 M4
Use Common Features – provide common program interface Nested Vectored Interrupt Controller Systick Timer
Two operation modes (Thread and Handler)
Two Stack (MSP and PSP)
Memory mapped control registers make it accessible by C via pointerdeclaration
Designed to be fully programmed in C (CMSIS)
Cortex-M Features
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Global microcontroller standard, Created by ARM and licensed to partners(NXP, TI, Freescale, Atmel, ST etc.)
ARM is fabless - Different vendors implement variation of microcontrollerbased on ARM IP
RISC low power, upwards compatibility, M0 M1 M3 M4
Use Common Features – provide common program interface Nested Vectored Interrupt Controller Systick Timer
Two operation modes (Thread and Handler)
Two Stack (MSP and PSP)
Memory mapped control registers make it accessible by C via pointerdeclaration
Designed to be fully programmed in C (CMSIS)
Development Requirement
Programming CMSIS, C, C++, Assembler (Thumb 2)
Startup Code Initialize the core and peripherals
Vector Table Main stack pointer start address Exception subroutine start address
Assembler, Compiler and Linker Scatter load file (linker script)
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Programming CMSIS, C, C++, Assembler (Thumb 2)
Startup Code Initialize the core and peripherals
Vector Table Main stack pointer start address Exception subroutine start address
Assembler, Compiler and Linker Scatter load file (linker script)
Vector Tables in C#define _StackTop 0x10008000
typedef void(*const ExcFuncPtr)(void) __IRQ;
extern int main (void);
// Dummy Exception Handlers
__IRQ void Reset_Handler(void)
{main();
while(1);}
__IRQ void NMI_Handler(void)
{while(1);}
__IRQ void HardFault_Handler(void)
{while(1);}
__IRQ void SVC_Handler (void)
{while(1);}
__IRQ void DebugMon_Handler(void)
{while(1);}
__IRQ void PendSV_Handler(void)
{while(1);}
__IRQ void Systic_Handler(void)
{while(1);}
__IRQ void ExtIRQ_Handler(void)
{while(1);}
Contains Dummy ExceptionHandler and Vector Table
Can be customized for targetapplication
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#define _StackTop 0x10008000
typedef void(*const ExcFuncPtr)(void) __IRQ;
extern int main (void);
// Dummy Exception Handlers
__IRQ void Reset_Handler(void)
{main();
while(1);}
__IRQ void NMI_Handler(void)
{while(1);}
__IRQ void HardFault_Handler(void)
{while(1);}
__IRQ void SVC_Handler (void)
{while(1);}
__IRQ void DebugMon_Handler(void)
{while(1);}
__IRQ void PendSV_Handler(void)
{while(1);}
__IRQ void Systic_Handler(void)
{while(1);}
__IRQ void ExtIRQ_Handler(void)
{while(1);}
Contains Dummy ExceptionHandler and Vector Table
Can be customized for targetapplication
Vector Tables in C (continued..)__attribute__ ((section (“RESET”))) /* AREA = RESET as START POINT */
ExcFuncPtr vector_table [] = { /* vector table */
(ExcFuncPtr) _StackTop, /* Address = 0x00, Initial Stack Pointer */
Reset_Handler,
NMI_Handler,
HardFault_Handler,
0, /* MemManage_Handler in Cortex M3 */
0, /* BusFault_ Handler in Cortex M3 */
0, /* UsageFault_Handler in Cortex M3 */
0, 0, 0, 0, /* Reserved */
SVC_Handler,
0, /* DebugMon_Handler in Cortex M3 */
0, /* Reserved */
PenSV_Handler,
SysTick_Handler,
/* External Interrupts */
ExtIRQ_Handler
};
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__attribute__ ((section (“RESET”))) /* AREA = RESET as START POINT */
ExcFuncPtr vector_table [] = { /* vector table */
(ExcFuncPtr) _StackTop, /* Address = 0x00, Initial Stack Pointer */
Reset_Handler,
NMI_Handler,
HardFault_Handler,
0, /* MemManage_Handler in Cortex M3 */
0, /* BusFault_ Handler in Cortex M3 */
0, /* UsageFault_Handler in Cortex M3 */
0, 0, 0, 0, /* Reserved */
SVC_Handler,
0, /* DebugMon_Handler in Cortex M3 */
0, /* Reserved */
PenSV_Handler,
SysTick_Handler,
/* External Interrupts */
ExtIRQ_Handler
};
Different processors have differentstartup code and vector table
Recommended to use CMSIS functionsfor portability
Example Startup Code in C/* Import symbol from linker script */
extern unsigned long _data,_edata,_text,_bss,_ebss;
void Reset_Handler (void) {
unsigned long *src, *dest;
/* Copy data segment from flash to RAM */
src = &_etext;
for (dest = &_data; dest < &_edata;)
*dest++ = *src++;
/* Initialize the .bss segment of memory to zeros */
src = &_bss;
while (src < &_ebss)
*src++ = 0;
main(); /* Call main function */
while (1) ; /* In case main() fails */
}
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/* Import symbol from linker script */
extern unsigned long _data,_edata,_text,_bss,_ebss;
void Reset_Handler (void) {
unsigned long *src, *dest;
/* Copy data segment from flash to RAM */
src = &_etext;
for (dest = &_data; dest < &_edata;)
*dest++ = *src++;
/* Initialize the .bss segment of memory to zeros */
src = &_bss;
while (src < &_ebss)
*src++ = 0;
main(); /* Call main function */
while (1) ; /* In case main() fails */
}
Example C Application#include “LPC17xx.h”; /* Required */
int main (void) {
// System initialization-part of CMSIS(system_LPC17xx.c)
SystemInit ();
// CMSIS Function to set up the SysTick Timer for 1ms interrupt
if (SysTick_Config (SystemCoreClock/1000) { /* core_cm3.h */
while (1);} /* Wait until Systick interrupt is configured */
// Update SystemCoreClock after set up (system_LPC17xx.c)
SystemCoreClockUpdate();
// Set pin P1.18 as GPIO Pin (0b00)
LPC_PINCON -> PINSEL4 = ((0 << 18)| (0 << 19));
// Set pin P1.18 as output (Output = 1, Input = 0)
LPC_GPIO1 -> (1 << 18);
// Single Blink
LPC_GPIO1 -> FIOPIN | = (1 <<18); // LED ON
delay (100); // 100 x 1ms (Systick Configuration)
LPC_GPIO1 -> FIOPIN &= ~(1 <<18); // LED OFF
}
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#include “LPC17xx.h”; /* Required */
int main (void) {
// System initialization-part of CMSIS(system_LPC17xx.c)
SystemInit ();
// CMSIS Function to set up the SysTick Timer for 1ms interrupt
if (SysTick_Config (SystemCoreClock/1000) { /* core_cm3.h */
while (1);} /* Wait until Systick interrupt is configured */
// Update SystemCoreClock after set up (system_LPC17xx.c)
SystemCoreClockUpdate();
// Set pin P1.18 as GPIO Pin (0b00)
LPC_PINCON -> PINSEL4 = ((0 << 18)| (0 << 19));
// Set pin P1.18 as output (Output = 1, Input = 0)
LPC_GPIO1 -> (1 << 18);
// Single Blink
LPC_GPIO1 -> FIOPIN | = (1 <<18); // LED ON
delay (100); // 100 x 1ms (Systick Configuration)
LPC_GPIO1 -> FIOPIN &= ~(1 <<18); // LED OFF
}
Vector Table in Assembler
; Vector Table
AREA RESET,DATA,READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0,0,0,0 ; Reserved
DCD SVC_Handler ; SVCall Handler
.....
Refer to vendor specific CMSIS based startup file startup_devices.s (example: startup_LPC17xx.s)
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; Vector Table
AREA RESET,DATA,READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0,0,0,0 ; Reserved
DCD SVC_Handler ; SVCall Handler
.....
Vector Table in Assembler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
Weakly linked handlers implementation are provided – can be overwritten by user The Reset_Handler is responsible for calling System_Init
115Copyright © 2014
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
__main is used toimplement the Clibrary
Variables and Constants Variable reside in RAM and can be modified Dynamic (local) when declared inside a function Static (global) when declared outside a function
Constant usually reside in ROM and cannot be modified Along with the code inside a .text section
int MyVar; /* variable allows read/write access */
const int MyConst=33; /* constant allows only read access */
void main (void) {
MyVar=66; /* write access to the variable */
MyFunc (MyVar); /* read access to the variable */
MyFunc (MyConst); /* read access to the constant */
}
116Copyright © 2014
Variable reside in RAM and can be modified Dynamic (local) when declared inside a function Static (global) when declared outside a function
Constant usually reside in ROM and cannot be modified Along with the code inside a .text section
int MyVar; /* variable allows read/write access */
const int MyConst=33; /* constant allows only read access */
void main (void) {
MyVar=66; /* write access to the variable */
MyFunc (MyVar); /* read access to the variable */
MyFunc (MyConst); /* read access to the constant */
}
Memory Allocation C compiler places initialized global variables in the .data
section The .data has to be copied from Flash to RAM
All uninitialized global variables will be initialized to zero Section called .bss is used for uninitialized variables These variables do not have to be stored in Flash (all zero) Memory locations corresponding to these variables have to
initialized to zero
Const are placed in a separate section, called .rodata Since contents of .rodata section will not be modified ,
they can be placed in Flash
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C compiler places initialized global variables in the .datasection The .data has to be copied from Flash to RAM
All uninitialized global variables will be initialized to zero Section called .bss is used for uninitialized variables These variables do not have to be stored in Flash (all zero) Memory locations corresponding to these variables have to
initialized to zero
Const are placed in a separate section, called .rodata Since contents of .rodata section will not be modified ,
they can be placed in Flash
Volatile Pointer Declarations Pointers are a convenient mechanism for accessing memory
mapped register Volatile declarations indicate a value that can change outside
of the processor’s control Typically use if the pointer is pointing to memory location used by the peripheral
/* Volatile declarations */
#define PORTA *(unsigned int volatile *)(0x1005)
#define PORTB *(unsigned int volatile *)(0x1004)
unsigned int info = PORTA;/* input 32 bits from PORTA */
...
if ((PORTA & 0x04) == 0) /* test bit 2 of PORTA */
PORTB = 0; /* if PORTA bit 2 is 0 then make PORTB = 0 */
118Copyright © 2014
Pointers are a convenient mechanism for accessing memorymapped register Volatile declarations indicate a value that can change outside
of the processor’s control Typically use if the pointer is pointing to memory location used by the peripheral
/* Volatile declarations */
#define PORTA *(unsigned int volatile *)(0x1005)
#define PORTB *(unsigned int volatile *)(0x1004)
unsigned int info = PORTA;/* input 32 bits from PORTA */
...
if ((PORTA & 0x04) == 0) /* test bit 2 of PORTA */
PORTB = 0; /* if PORTA bit 2 is 0 then make PORTB = 0 */
Structure in Embedded C Structures are used to facilitate register/peripheral accessesstruct port {
int mode;
unsigned int volatile *addr;
unsigned int volatile *ddr;} PortA;
...
typedef struct {
int mode;
unsigned int volatile *addr;
unsigned int volatile *ddr;} port_t;
port_t PortA;
)
...
PortA.mode = -1;
PortA.addr = (unsigned int volatile *)(0x1005);
119Copyright © 2014
Structures are used to facilitate register/peripheral accessesstruct port {
int mode;
unsigned int volatile *addr;
unsigned int volatile *ddr;} PortA;
...
typedef struct {
int mode;
unsigned int volatile *addr;
unsigned int volatile *ddr;} port_t;
port_t PortA;
)
...
PortA.mode = -1;
PortA.addr = (unsigned int volatile *)(0x1005);
Structure Use Model Inside CMSIS CMSIS relies on structures and linker script to position control
registers within the Cortex-M memory map/* Structure type to access the System Timer (Systick) */
typedef struct
{ __IO uint32 CTRL;
__IO uint32 LOAD;
__IO uint32 VAL;
__IO uint32 CALIB;
} Systick_Type
#define Systick ((SysTick_Type *)SysTick_BASE)
static __INLINE uint32_t SysTick_Config (uint32_t ticks)
{ if (ticks > SysTick_LOAD_RELOAD_Msk)
return(1);
SysTick->LOAD = (ticks & SysTick_LOAD_RELOD_Msk)- 1;
...
}
Placed in Memory
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CMSIS relies on structures and linker script to position controlregisters within the Cortex-M memory map
/* Structure type to access the System Timer (Systick) */
typedef struct
{ __IO uint32 CTRL;
__IO uint32 LOAD;
__IO uint32 VAL;
__IO uint32 CALIB;
} Systick_Type
#define Systick ((SysTick_Type *)SysTick_BASE)
static __INLINE uint32_t SysTick_Config (uint32_t ticks)
{ if (ticks > SysTick_LOAD_RELOAD_Msk)
return(1);
SysTick->LOAD = (ticks & SysTick_LOAD_RELOD_Msk)- 1;
...
}
Linker Script – Scatter file Determines how the memory layout of your controller is organized – Create
image memory map; ***************************************************; *** Scatter-Loading Description File generated by uVision ***; ***************************************************LR_IROM1 0x00000000 0x00001000 { ; load region size_region
ER_IROM1 0x00000000 0x00001000 { ; load address = execution address*.o (RESET, +First)*(InRoot$Sections).ANY (+RO)
}RW_IRAM1 0x40000000 0x00008000 { ; RW data
.ANY (+RW +ZI)}
LR_IROM2 0x00003000 0x0003D000 {ER_IROM2 0x00003000 0x0003D000 { ; load address = execution address
.ANY (+RO)}
}
__attribute__ ( (section ( “ RESET” ) ) )
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Determines how the memory layout of your controller is organized – Createimage memory map
; ***************************************************; *** Scatter-Loading Description File generated by uVision ***; ***************************************************LR_IROM1 0x00000000 0x00001000 { ; load region size_region
ER_IROM1 0x00000000 0x00001000 { ; load address = execution address*.o (RESET, +First)*(InRoot$Sections).ANY (+RO)
}RW_IRAM1 0x40000000 0x00008000 { ; RW data
.ANY (+RW +ZI)}
LR_IROM2 0x00003000 0x0003D000 {ER_IROM2 0x00003000 0x0003D000 { ; load address = execution address
.ANY (+RO)}
}
__attribute__ ( (section ( “ RESET” ) ) )
Vector table
Agenda
Software Development Tools
ARMv7-M Architecture Programmer Overview
CMSIS
CMSIS-CORE Startup and System Initialization
Post Startup Initialization
122Copyright © 2014
Software Development Tools
ARMv7-M Architecture Programmer Overview
CMSIS
CMSIS-CORE Startup and System Initialization
Post Startup Initialization
CMSIS Overview CMSIS helps the embedded industry in software standardization
Provides an abstraction layer for Cortex-M processor based devices
CMSIS benefits the embedded developer Consistent software interfaces for silicon and middleware vendors Simplifies re-use across Cortex-M processor-based devices Reduces learning curve, development costs, and time-to-market
CMSIS uses the following essential coding rules and conventions: Compliant with ANSI C and C++ Uses ANSI C standard data types defined in <stdint.h>
Variables and parameters have a complete data type Expressions for #define constants are enclosed in parentheses Conforms to MISRA 2004
MISRA rule violations are documented
123Copyright © 2014
CMSIS helps the embedded industry in software standardization Provides an abstraction layer for Cortex-M processor based devices
CMSIS benefits the embedded developer Consistent software interfaces for silicon and middleware vendors Simplifies re-use across Cortex-M processor-based devices Reduces learning curve, development costs, and time-to-market
CMSIS uses the following essential coding rules and conventions: Compliant with ANSI C and C++ Uses ANSI C standard data types defined in <stdint.h>
Variables and parameters have a complete data type Expressions for #define constants are enclosed in parentheses Conforms to MISRA 2004
MISRA rule violations are documented
There are seven main components to CMSIS: CMSIS-CORE API for Cortex-M processor and core peripherals CMSIS-DRIVER API for generic peripheral drivers CMSIS-DAP Debug Access Port firmware specification CMSIS-DSP DSP Library with many function types for Cortex-M CMSIS-PACK Device package (PDSC) for software development CMSIS-RTOS API for RTOS integration CMSIS-SVD XML system view description for peripherals
CMSIS Structure
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There are seven main components to CMSIS: CMSIS-CORE API for Cortex-M processor and core peripherals CMSIS-DRIVER API for generic peripheral drivers CMSIS-DAP Debug Access Port firmware specification CMSIS-DSP DSP Library with many function types for Cortex-M CMSIS-PACK Device package (PDSC) for software development CMSIS-RTOS API for RTOS integration CMSIS-SVD XML system view description for peripherals
Using CMSIS-CORE To use the CMSIS-CORE the following files are added to the embedded
application: Startup File startup_<device>.s with reset handler and exception vectors System Configuration Files system_<device>.c and system_<device>.h with
general device configuration (clock setup) Device Header File <device.h> gives access to processor core and all peripherals
Silicon vendors create these device-specific CMSIS-CORE files based ontemplate files provided by ARM
125Copyright © 2014
To use the CMSIS-CORE the following files are added to the embeddedapplication: Startup File startup_<device>.s with reset handler and exception vectors System Configuration Files system_<device>.c and system_<device>.h with
general device configuration (clock setup) Device Header File <device.h> gives access to processor core and all peripherals
Silicon vendors create these device-specific CMSIS-CORE files based ontemplate files provided by ARM
Agenda
Software Development Tools
ARMv7-M Architecture Programmer Overview
CMSIS
CMSIS-CORE Startup and System Initialization
Post Startup Initialization
126Copyright © 2014
Software Development Tools
ARMv7-M Architecture Programmer Overview
CMSIS
CMSIS-CORE Startup and System Initialization
Post Startup Initialization
CMSIS Startup and Initialization CMSIS-CORE provides the following files for an embedded application: Startup File startup_<device>.s with reset handler and exception vectors System Configuration Files system_<device>.c and system_<device.h>
with general device configuration (e.g., clocks, PLLs and bus setup) Device Header File <device.h> gives access to processor core and all
peripherals
For any existing device, ARM recommends including CMSIS-CORE startupand system initialization code from the device vendor If this is not available, startup and system initialization code will have to be created
manually or by using an alternative, non-CMSIS compliant solution
When designing a new device, ARM recommends that the device vendor: Creates a CMSIS-SVD description to automatically generate CMSIS compliant
device header files Formalizes the programmer’s view for device-specific peripherals
Adapts the system initialization and startup template files to their device
127Copyright © 2014
CMSIS-CORE provides the following files for an embedded application: Startup File startup_<device>.s with reset handler and exception vectors System Configuration Files system_<device>.c and system_<device.h>
with general device configuration (e.g., clocks, PLLs and bus setup) Device Header File <device.h> gives access to processor core and all
peripherals
For any existing device, ARM recommends including CMSIS-CORE startupand system initialization code from the device vendor If this is not available, startup and system initialization code will have to be created
manually or by using an alternative, non-CMSIS compliant solution
When designing a new device, ARM recommends that the device vendor: Creates a CMSIS-SVD description to automatically generate CMSIS compliant
device header files Formalizes the programmer’s view for device-specific peripherals
Adapts the system initialization and startup template files to their device
CMSIS-CORE: Startup File The Startup File startup_<device>.s contains the following: Vector table Exception vectors of the Cortex-M processor Interrupt vectors that are device specific Weak functions that implement default routines
Reset handler calls SystemInit followed by __main
Stack and heap configuration __user_initial_stackheap when using the standard C library __initial_sp, __heap_base and __heap_limit when using microlib discussed in more detail later …
The file exists for each supported toolchain and is the only toolchain specificCMSIS file
128Copyright © 2014
The Startup File startup_<device>.s contains the following: Vector table Exception vectors of the Cortex-M processor Interrupt vectors that are device specific Weak functions that implement default routines
Reset handler calls SystemInit followed by __main
Stack and heap configuration __user_initial_stackheap when using the standard C library __initial_sp, __heap_base and __heap_limit when using microlib discussed in more detail later …
The file exists for each supported toolchain and is the only toolchain specificCMSIS file
CMSIS-CORE: Vector Table; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY, ALIGN=8EXPORT __VectorsEXPORT __Vectors_EndEXPORT __Vectors_Size
__Vectors DCD __initial_spDCD Reset_HandlerDCD NMI_HandlerDCD HardFault_HandlerDCD MemManage_HandlerDCD BusFault_HandlerDCD UsageFault_HandlerDCD 0, 0, 0, 0DCD SVC_HandlerDCD DebugMon_HandlerDCD 0DCD PendSV_HandlerDCD SysTick_Handler
; External Interrupts; Add here the vectors for the device specific external interrupts handler
DCD <DeviceInterrupt>_IRQHandler ; 0: Default
__Vectors_End__Vectors_Size EQU __Vectors_End - __Vectors
129Copyright © 2014
; Vector Table Mapped to Address 0 at ResetAREA RESET, DATA, READONLY, ALIGN=8EXPORT __VectorsEXPORT __Vectors_EndEXPORT __Vectors_Size
__Vectors DCD __initial_spDCD Reset_HandlerDCD NMI_HandlerDCD HardFault_HandlerDCD MemManage_HandlerDCD BusFault_HandlerDCD UsageFault_HandlerDCD 0, 0, 0, 0DCD SVC_HandlerDCD DebugMon_HandlerDCD 0DCD PendSV_HandlerDCD SysTick_Handler
; External Interrupts; Add here the vectors for the device specific external interrupts handler
DCD <DeviceInterrupt>_IRQHandler ; 0: Default
__Vectors_End__Vectors_Size EQU __Vectors_End - __Vectors
CMSIS-CORE: Exception Handlers; Reset HandlerReset_Handler PROC
EXPORT Reset_Handler [WEAK]IMPORT SystemInitIMPORT __mainLDR R0, =SystemInitBLX R0LDR R0, =__mainBX R0ENDP
; Dummy Exception Handlers (infinite loops which can be modified)NMI_Handler PROC
EXPORT NMI_Handler [WEAK]B .ENDP
HardFault_Handler PROCEXPORT HardFault_Handler [WEAK]B .ENDP
130Copyright © 2014
; Reset HandlerReset_Handler PROC
EXPORT Reset_Handler [WEAK]IMPORT SystemInitIMPORT __mainLDR R0, =SystemInitBLX R0LDR R0, =__mainBX R0ENDP
; Dummy Exception Handlers (infinite loops which can be modified)NMI_Handler PROC
EXPORT NMI_Handler [WEAK]B .ENDP
HardFault_Handler PROCEXPORT HardFault_Handler [WEAK]B .ENDP
Stack and Heap Setup There are different mechanisms for setting up the stack (MSP) and heap Define the symbol __initial_sp, __heap_base and __heap_limit
In a scatter file, either: Define ARM_LIB_STACK and ARM_LIB_HEAP regions Define an ARM_LIB_STACKHEAP region
Re-implementing __user_setup_stackheap()
Re-implementing the legacy function __user_initial_stackheap()
ARM recommends __user_setup_stackheap() instead of__user_initial_stackheap() for Cortex-M applications The stack pointer (sp) can be left to the same value it had on application entry
The initial stack pointer must be aligned to a multiple of eight bytes
Stack and Heap Setup Method Supported by CMSIS? Supported by microlib?
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There are different mechanisms for setting up the stack (MSP) and heap Define the symbol __initial_sp, __heap_base and __heap_limit
In a scatter file, either: Define ARM_LIB_STACK and ARM_LIB_HEAP regions Define an ARM_LIB_STACKHEAP region
Re-implementing __user_setup_stackheap()
Re-implementing the legacy function __user_initial_stackheap()
ARM recommends __user_setup_stackheap() instead of__user_initial_stackheap() for Cortex-M applications The stack pointer (sp) can be left to the same value it had on application entry
The initial stack pointer must be aligned to a multiple of eight bytes
Stack and Heap Setup Method Supported by CMSIS? Supported by microlib?
Define __inital_sp, __heap_base and __heap_limit ✓ ✓Special Scatter File Regions ✓Re-implement __user_setup_stackheap() ✓
; <h> Stack Configuration; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3Stack_Mem SPACE Stack_Size__initial_sp
; <h> Heap Configuration; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3__heap_baseHeap_Mem SPACE Heap_Size__heap_limit
CMSIS-CORE: Stack and Heap Setup
132Copyright © 2014
; <h> Stack Configuration; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3Stack_Mem SPACE Stack_Size__initial_sp
; <h> Heap Configuration; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>; </h>
Heap_Size EQU 0x00000C00
AREA HEAP, NOINIT, READWRITE, ALIGN=3__heap_baseHeap_Mem SPACE Heap_Size__heap_limit
Stack and Heap Setup (continued..); User Initial Stack & Heap
IF :DEF:__MICROLIBEXPORT __initial_spEXPORT __heap_baseEXPORT __heap_limit
ELSEIMPORT __use_two_region_memoryEXPORT __user_initial_stackheap
__user_initial_stackheap PROCLDR R0, = Heap_MemLDR R1, =(Stack_Mem + Stack_Size)LDR R2, = (Heap_Mem + Heap_Size)LDR R3, = Stack_MemBX LRENDP
133Copyright © 2014
; User Initial Stack & Heap
IF :DEF:__MICROLIBEXPORT __initial_spEXPORT __heap_baseEXPORT __heap_limit
ELSEIMPORT __use_two_region_memoryEXPORT __user_initial_stackheap
__user_initial_stackheap PROCLDR R0, = Heap_MemLDR R1, =(Stack_Mem + Stack_Size)LDR R2, = (Heap_Mem + Heap_Size)LDR R3, = Stack_MemBX LRENDP
Possible Initialization Sequence (1)C Library User Code
__main
copy code anddecompress data
zero uninitialized data
Reset_Handler
calls SystemInit andthen calls __main
2
CMSIS Startup Code
1
Image Entry Point
134Copyright © 2014
__rt_entry
set up application stackand heap
initialize libraryfunctions
call top-levelconstructors (C++)
Exit from application
main()
tells linker to link inlibrary initialization code
2
3
4
Possible initialization sequence (2)C Library User Code
__main
copy code anddecompress data
zero uninitialized data
Reset_Handler
calls SystemInit andthen calls __main
2
CMSIS Startup Code
1
Image Entry Point
135Copyright © 2014
__rt_entry
initialize libraryfunctions
call top-levelconstructors (C++)
Exit from application
main()
tells linker to link inlibrary initialization code
2
5
__user_setup_stackheap()
set up stack & heap
3
4
Possible initialization sequence (3)C Library User Code
__main
copy code anddecompress data
zero uninitialized data
Reset_Handler
calls SystemInit andthen calls __main
2
CMSIS Startup Code
1
Image Entry Point
136Copyright © 2014
__rt_entry
set up application stackand heap
initialize libraryfunctions
call top-levelconstructors (C++)
Exit from application
main()
tells linker to link inlibrary initialization code
2
4$Sub$$main()
enable system features,e.g., NVIC, MPU
5
6
__user_setup_stackheap()
set up stack & heap
3
Agenda
Software Development Tools
ARMv7-M Architecture Programmer Overview
CMSIS
CMSIS-CORE Startup and System Initialization
Post Startup Initialization
137Copyright © 2014
Software Development Tools
ARMv7-M Architecture Programmer Overview
CMSIS
CMSIS-CORE Startup and System Initialization
Post Startup Initialization
Reset and Initialization Cortex-M processors start up in privileged Thread mode
System initialization can only be executed in privileged mode Need to carry out privileged operations, e.g. setup MPU, enable interrupts
Developers should consider whether the main application should run asprivileged or unprivileged Note that some ARMv6-M cores (Cortex-M0 and Cortex-M1) do not implement the
Unprivileged/Privileged Extension and run in privileged mode only
Before entering the main application, the startup code might need toperform a number of things, for example: Setup and enable MPU (if available) Enable hardware enforcement of 8-byte stack alignment for exception handlers Complete any memory (Flash/RAM) remapping Prioritize and enable interrupts Initialize RTOS (if present) (Last) Change Thread mode to Unprivileged – if required
138Copyright © 2014
Cortex-M processors start up in privileged Thread mode
System initialization can only be executed in privileged mode Need to carry out privileged operations, e.g. setup MPU, enable interrupts
Developers should consider whether the main application should run asprivileged or unprivileged Note that some ARMv6-M cores (Cortex-M0 and Cortex-M1) do not implement the
Unprivileged/Privileged Extension and run in privileged mode only
Before entering the main application, the startup code might need toperform a number of things, for example: Setup and enable MPU (if available) Enable hardware enforcement of 8-byte stack alignment for exception handlers Complete any memory (Flash/RAM) remapping Prioritize and enable interrupts Initialize RTOS (if present) (Last) Change Thread mode to Unprivileged – if required
8-byte Stack Alignment in Handlers The ABI requires the stack to be 8-byte aligned at all interfaces
Including within interrupt handlers
But application code might not maintain 8-byte stack alignment internally For example: if an interrupt occurs in a leaf function where the stack is not
aligned
Cortex-M3 (r1p0 and later) and Cortex-M4 allow 8-byte stack alignment tobe enforced by hardware whenever an exception occurs Enabled by setting STKALIGN (bit 9) in Configuration and Control Register
139Copyright © 2014
:
/* If using Cortex-M3 rev1 or later, enable hardware stack alignment */
#if defined (__TARGET_CPU_CORTEX_M3 || __TARGET_CPU_CORTEX_M4)
&& !defined __TARGET_CPU_CORTEX_M3_REV0
SCB->CCR |= SCB_CCR_STKALIGN_Msk;
#endif
__DSB(); /* Force Memory Writes before continuing */
__ISB(); /* Flush and refill pipeline with updated permissions */
:
The ABI requires the stack to be 8-byte aligned at all interfaces Including within interrupt handlers
But application code might not maintain 8-byte stack alignment internally For example: if an interrupt occurs in a leaf function where the stack is not
aligned
Cortex-M3 (r1p0 and later) and Cortex-M4 allow 8-byte stack alignment tobe enforced by hardware whenever an exception occurs Enabled by setting STKALIGN (bit 9) in Configuration and Control Register
Change Thread Mode to Unprivileged Simple applications without an embedded OS will typically not require
Thread mode to be unprivileged The whole application is privileged and uses MSP
Applications that use an embedded OS will typically set Thread mode tounprivileged access level CONTROL.SPSEL = 1 and CONTROL.nPRIV = 1
Software running at unprivileged level cannot switch itself back to privilegedaccess level Untrusted applications run at unprivileged access level This is essential in order to provide a basic security usage model A Supervisor Call (SVC) instruction may be used to request a privileged operation
The CONTROL register can be accessed using CMSIS-CORE functions
140Copyright © 2014
Simple applications without an embedded OS will typically not requireThread mode to be unprivileged The whole application is privileged and uses MSP
Applications that use an embedded OS will typically set Thread mode tounprivileged access level CONTROL.SPSEL = 1 and CONTROL.nPRIV = 1
Software running at unprivileged level cannot switch itself back to privilegedaccess level Untrusted applications run at unprivileged access level This is essential in order to provide a basic security usage model A Supervisor Call (SVC) instruction may be used to request a privileged operation
The CONTROL register can be accessed using CMSIS-CORE functions
/* Change Thread mode to unprivileged and use PSP */__set_CONTROL(0x3);/* Flush and refill pipeline with unprivileged permissions */__ISB();
MOVS r0,#3MSR CONTROL,r0ISB
Embedded Programmingfor Cortex M
Train The Trainer - IAC
141Copyright © 2014
Embedded Programmingfor Cortex M
Train The Trainer - IAC