Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich,...

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Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras

Transcript of Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich,...

Page 1: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Arithmetic Test Pattern Generation: A Bit Level Formulation of the

Optimization Problem

S. Manich, L. García and J. Figueras

Page 2: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Central idea• Embed a set of Test Vectors into a single adder test

pattern generator.

• Minimize length of test pattern sequence

Page 3: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Central idea• Embed a set of Test Vectors into a single adder test

pattern generator.

• Minimize length of test pattern sequence

Seed

Incr

emen

t

Clock i = 0,1,···,k

Load seed at preset

Testpatterns

Page 4: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Embedding TV in -positive numbers

• Apply Euclid’s algorithm to select GCD

Page 5: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Embedding TV in -positive numbers

Change 43 1

Page 6: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Embedding TV in -positive numbers

Page 7: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Exploiting GF(26), addition overflow

Page 8: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Exploiting GF(26), addition overflow

• Computation of GCD (Euclid’s algorithm)

does not properly minimize test sequence

length in GF(2n).

Page 9: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Minimizing length in GF(2n)

• How to compute the length?

0···0

TV

I I Length TVLength < 2n

Page 10: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Solving the length equation• Iterating up to a maximum of

n steps

?

IAt preset 0···0

+

n bits

n bi

ts

n bits

Clock

Shift 1 at clock

Shi

ft 1

at c

lock

TV

Len

gth

I Length TVLength < 2n

Page 11: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example

I

+

n bits

n bi

ts

n bits

TV

Length101001

0010010

00

00

00

037

36

0 0 0 0 0 0

Page 12: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example

I

+

n bits

n bi

ts

n bits

TV

Length101001

0010010

00

00

00

037

36

0 0 0 0 0 0

Page 13: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example

I

+

n bits

n bi

ts

n bits

TV

Length101001

0010010

00

00

01

037

36

0 0 0 0 0 0

Page 14: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example

I

+

n bits

n bi

ts

n bits

TV

Length101001

0010010

01

00

00

437

36

0 1 0 1 0 0

Page 15: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example

I

+

n bits

n bi

ts

n bits

TV

Length101001

0010010

01

00

01

437

36

0 1 0 1 0 0

Page 16: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example

I

+

n bits

n bi

ts

n bits

TV

Length101001

0010010

01

01

0 0

2037

36

1 0 0 1 0 0

Page 17: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example

I

n bits

n bi

ts

n bits

TV

Length101001

0010010

01

01

0

2037

36

1 0 0 1 0 0

Page 18: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Let several TV = {V0, ···, VM-1}

• Assume V0 is the seed.

• Find increment I such that the length to generate all

test vectors is minimized.

I L1 (V1V0)

I L2 (V2V0)

I LM-1 (VM-1V0)···I?

max Length of test sequence

The optimization of the equations give I such that Length is minimized

Page 19: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Extract the loop out of the equations

• In order to isolate Li and make the optimization possible.

I

+

n bitsn

bits

n bits

TV

LengthTV

= Y

TV= 1

0 0 0 1

n bi

ts

n bits

n bits

TV

Length

Page 20: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Extract the loop out of the equations

• In order to isolate Li and make the optimization possible.

Length TV Y

Y I

1

I Y 1

Page 21: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Rewritting equations

Y (V1V0) L1

Y (V2V0) L2

Y (VM-1V0) LM-1

···Y?

max Length of test sequenceThe optimization of the equations give Y such that Length is minimized

Page 22: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Circuital implementation

(V1V0) (VM1V0)

Y

(mod 2n)

L1 LM1

MAXLength of test sequence

(mod 2n)

Page 23: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Optimizing binary search

0 1 0 1 ··· 1

Before evaluating, load 0

YES

NO

After evaluation,write 0

After evaluation, write 1

After ENDminimal test sequenceLength and optimal Y

(V1V0) (VM1V0)

Y

(mod 2n)

L1 LM1

MAXLength of test sequence

(mod 2n)

Optimal Igiven seed V0

Page 24: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

1 1 1 1 1 1

1

59

(mod 26)

59

MAX

62

62

(mod 26)61

61

(mod 26)60

60

(mod 26)

YES

62 = 1 1 1 1 1 0

= 63

Page 25: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

1

59

(mod 26)

59

62

62

(mod 26)61

61

(mod 26)60

60

(mod 26)

0 1 1 1 1 1

62 = 1 1 1 1 1 0

NO

MAX

= 31

Page 26: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

1

59

(mod 26)

59

62

62

(mod 26)61

61

(mod 26)60

60

(mod 26)

0 1 1 1 1 1

62 = 1 1 1 1 1 0

NO

MAX

= 31

Page 27: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

59

59

(mod 26)

25

62

10

(mod 26)61

15

(mod 26)60

20

(mod 26)

0 1 1 1 1 1

25 = 0 1 1 0 0 1

MAX

= 31

YES

Page 28: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

59

59

(mod 26)

25

62

10

(mod 26)61

15

(mod 26)60

20

(mod 26)

25 = 0 1 1 0 0 1

MAX

= 15NO

0 0 1 1 1 1

Page 29: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

59

59

(mod 26)

25

62

10

(mod 26)61

15

(mod 26)60

20

(mod 26)

25 = 0 1 1 0 0 1

MAX

= 15NO

0 0 1 1 1 1

Page 30: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

61

59

(mod 26)

15

62

6

(mod 26)61

9

(mod 26)60

12

(mod 26)

15 = 0 0 1 1 1 1

MAX

= 150 0 1 1 1 1

YES

Page 31: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

61

59

(mod 26)

15

62

6

(mod 26)61

9

(mod 26)60

12

(mod 26)

15 = 0 0 1 1 1 1

MAX

= 70 0 0 1 1 1NO

Page 32: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

61

59

(mod 26)

15

62

6

(mod 26)61

9

(mod 26)60

12

(mod 26)

15 = 0 0 1 1 1 1

MAX

= 70 0 0 1 1 1NO

Page 33: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 70 0 0 1 1 1

YES

Page 34: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 30 0 0 0 1 1NO

Page 35: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 30 0 0 0 1 1NO

Page 36: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 70 0 0 1 1 1NO

Page 37: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 50 0 0 1 0 1

YES

Page 38: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 50 0 0 1 0 1

YES

Page 39: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 40 0 0 1 0 0NO

Page 40: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 40 0 0 1 0 0NO

Page 41: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

= 50 0 0 1 0 1NO

Page 42: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

Minimum test sequence length

Page 43: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63 = Y

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

Minimum test sequence length

I = 63

I Y 1

Page 44: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

63 = Y

59

(mod 26)

5

62

2

(mod 26)61

3

(mod 26)60

4

(mod 26)

5 = 0 0 0 1 0 1

MAX

Minimum test sequence length

I = 63 Optimal increment

Page 45: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Example: TV = {0,59,60,61,62}

Page 46: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

How to evaluate max(Length)i = 0

(mod 26)

(mod 26)

(mod 26)

(mod 26)

MAX

OR 0

0 0 0 0 1 1

+ ++0

+0

+0

+0

Page 47: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

How to evaluate max(Length)i = 0

• Place Stuck-1 at output.

• Detect fault using ATPG methodologies:– Approximate methods.– SAT techniques optimal solution.

Page 48: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Cost of the methodology

• SAT problem is -complete.

• For our problem: cost indicator probability of finding

a max-term at random, number of bits (nstable) and

number of test vectors (Mdown).

M-1n-1

(M-1)n

1 1P[MT]= 2 +

22

Page 49: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

0,0001

0,001

0,01

0,1

1

0 5 10 15 20 25 30 35

Graphically

P[MT] n (number of bits)

M (number of test vectors to embed)

Critical boundary

Page 50: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Critical boundary

• MTmax 1

n M -1 n M -1s820 23 24 c3540 50 51

s1196 31 32 s641 54 55c6288 32 33 c880 60 61s1238 32 33 s838 66 67c1908 33 34 s1423 91 92s420 34 35 c5315 178 179c432 36 37 c7552 207 208c499 41 42 s5378 214 215

c1355 41 42 c2670 233 234s953 45 46 s9234 247 248

Page 51: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

0,0001

0,001

0,01

0,1

1

0 5 10 15 20 25 30 35

Cost: step i

MSBs (0...0

)

step i

MSBs (1...1)

Page 52: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

1E-10

1E-09

1E-08

1E-07

1E-06

1E-05

0,0001

0,001

0,01

0,1

1

0 5 10 15 20 25 30 35

Restriction: (0...01...10...01...10...0) step i

Page 53: Arithmetic Test Pattern Generation: A Bit Level Formulation of the Optimization Problem S. Manich, L. García and J. Figueras.

Conclusions

• Minimization of test sequence length for embedding

of test vectors in a single arithmetic additive

generator is defined.

• The cost of the methodology is estimated.

• The methodology allows embedding of partially

defined test vectors.

• Theoretic background of methodology gives

strategies to improve existing heuristic methods

based on multiple-arithmetic generators (re-loading).