Arithmetic Building Blocks
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Transcript of Arithmetic Building Blocks
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Digital Integrated Circuits ABM H Rashid
Arithmetic Building Blocks
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Digital Integrated Circuits ABM H Rashid
A Generic Digital Processor
MEMORY
DATAPATH
CONTROL
INP
UT
-OU
TP
UT
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Digital Integrated Circuits ABM H Rashid
Building Blocks for Digital Architectures
Arithmetic unit
- Bit-sliced datapath (adder , multiplier, shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
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Digital Integrated Circuits ABM H Rashid
Bit-Sliced Design
Bit 3
Bit 2
Bit 1
Bit 0
Reg
iste
r
Add
er
Shif
ter
Mul
tipl
exer
Control
Dat
a-In
Dat
a-O
ut
Tile identical processing elements
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Digital Integrated Circuits ABM H Rashid
Funnel Shifter
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Digital Integrated Circuits ABM H Rashid
Full-Adder
A B
Cout
Sum
Cin Fulladder
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Digital Integrated Circuits ABM H Rashid
The Binary Adder
S A B Ci =
A= BCi ABCi ABCi ABCi+ + +
Co AB BCi ACi+ +=
A B
Cout
Sum
Cin Fulladder
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Digital Integrated Circuits ABM H Rashid
Express Sum and Carry as a function of P, G, D
Define 3 new variable which ONLY depend on A, B
Generate (G) = AB
Propagate (P) = A B
Delete = A B
Can also derive expressions for S and Co based on D and P
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Digital Integrated Circuits ABM H Rashid
The Ripple-Carry Adder
A0 B0
S0
Co,0Ci,0
A1 B1
S1
Co,1
A2 B2
S2
Co,2
A3 B3
S3
Co,3
(= Ci,1)FA FA FA FA
Worst case delay linear with the number of bits
tadder N 1– tcarry tsum+
td = O(N)
Goal: Make the fastest possible carry path circuit
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Digital Integrated Circuits ABM H Rashid
Complimentary Static CMOS Full Adder
VDD
VDD
VDD
VDD
A B
Ci
S
Co
X
B
A
Ci A
BBA
Ci
A B Ci
Ci
B
A
Ci
A
B
BA
28 Transistors
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Digital Integrated Circuits ABM H Rashid
Inversion Property
A B
S
CoCi FA
A B
S
CoCi FA
S A B Ci S A B Ci
=
Co A B Ci Co A B Ci
=
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Digital Integrated Circuits ABM H Rashid
Minimize Critical Path by Reducing Inverting Stages
A0 B0
S0
Co,0Ci,0
A1 B1
S1
Co,1
A2 B2
S2
Co,2 Co,3FA’ FA’ FA’ FA’
A3 B3
S3
Odd CellEven Cell
Exploit Inversion Property
Note: need 2 different types of cells
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Digital Integrated Circuits ABM H Rashid
The better structure: the Mirror Adder
VDD
Ci
A
BBA
B
A
A BKill
Generate"1"-Propagate
"0"-Propagate
VDD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
VDD
SCo
24 transistors
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Digital Integrated Circuits ABM H Rashid
The Mirror Adder
• The NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling transitions if the NMOS and PMOS devices are properly sized. A maximum of two series transistors can be observed in the carry-generation circuitry.
• When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly
important.
• The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .
• The transistors connected to Ci are placed closest to the output.
• Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.
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Digital Integrated Circuits ABM H Rashid
Single-Bit Addition
Half Adder Full Adder
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Ak BkCk-1 Ck Sk
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A B
S
Cout
A B
C
S
Coutout
S A B
C A B
out ( , , )
S A B C
C MAJ A B C
For the Sum Sk
If Ak=Bk then Sk=Ck-1 else Sk=Ck-1
For the carryIf Ak=Bk then Ck=Ak=Bk else Ck=Ck-1
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Digital Integrated Circuits ABM H Rashid
MUX (NMOS Pass transistor) based Adder
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Digital Integrated Circuits ABM H Rashid
MUX (CMOS Pass gate) based Adder
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Digital Integrated Circuits ABM H Rashid
MUX (CMOS Pass gate) based Adder with Buffer
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Digital Integrated Circuits ABM H Rashid
Leaf Cell (Multiplexer cell with or without cut)
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Digital Integrated Circuits ABM H Rashid
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Digital Integrated Circuits ABM H Rashid
Implementing ALU Function with an Adder
Sk=HkCk-1 + HkCk-1
Ck=AkBk+HkCk-1
Hk=AkBk +AkBk
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Digital Integrated Circuits ABM H Rashid
Carry Select Adder
For a n-bit ripple carry adder, Completion time T=k1n, where k1 is delay
through one adder cell. For Carry select adder the completion time T=Pk1 + (M-1)k2, Where the n-bit adder is divided in M blocks and each block contain P adder cell and k2 is the delay through the multiplexer.Mopt=(nk1/k2)
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Digital Integrated Circuits ABM H Rashid
Carry Skip Adder
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Digital Integrated Circuits ABM H Rashid
Carry Skip Adder
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Digital Integrated Circuits ABM H Rashid
Carry Skip Adder
Worst case carry propagation for carry skip addeer
The total (worst case) propagation delay time T is given by T=2Pk1 + (M-2)k2
Mopt=(2nk1/k2)
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Digital Integrated Circuits ABM H Rashid
Carry Look Ahead Adder
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Digital Integrated Circuits ABM H Rashid
Carry Look Ahead Adder
in
in
CBABABABABACBABAC
CBABAC
))(()()(
)(
0011001111011111
00000
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Digital Integrated Circuits ABM H Rashid
The Array Multiplier
HA FA FA HA
FA FA FA HA
FA FA FA HA
X0X1X2X3 Y1
X0X1X2X3 Y2
X0X1X2X3 Y3
Z1
Z2
Z3Z4Z5Z6
Z0
Z7
X0X1X2X3
Y0
X0X1X2X3
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Digital Integrated Circuits ABM H Rashid
The MxN Array Multiplier— Critical Path
HA FA FA HA
HAFAFAFA
FAFA FA HA
Critical Path 1
Critical Path 2
Critical Path 1 & 2
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Digital Integrated Circuits ABM H Rashid
Carry-Save Multiplier
HA HA HA HA
FAFAFAHA
FAHA FA FA
FAHA FA HA
Vector Merging Adder