Applied Vantage Astra DSA System · 2014-08-04 · NiSi Piping Defects Reduction TEM Top View...

Applied Materials Confidential

Applied Vantage® Astra™ DSA SystemS I M P L Y B E T T E R A N N E A L

Steve GhanayemCorporate VP and General Manager Metal Deposition and Front End Products

December 1, 2009

SILICON SYSTEMS GROUP2 Applied Materials Confidential

Rapid Thermal Processing Market Landscape

Millisecond anneals becoming a growing portion of SAM

Source: Gartner Dataquest, September 2009

F F F F


Building a Transistor

Gate Dielectric Gate Stack Etch Implant & USJ Anneal Spacer

Nickel Deposition Ni Diffusion AnnealRecessed Source/Drain

HARP for Pre-Metal Dielectric

Transistor OnIncreased Drive Current

Phase Transformation to NiSi Anneal

Stress-Inducing Nitride


Selective Epi

Anneal steps are key to device scaling

Source

Poly

Drain

SilicideContact Layer


Evolution of Single-Wafer Anneals

Benchmark performance, consistently delivered by Applied Materials

Technology Node

Ther

mal

Bud

get o

f Ann

eal

250 180 130 90 65 45 32

Spike

<1.5 sec

<0.001 sec

Millisecond Spike

Soak

5-60 sec

Illustration of relative temperature profiles

Radiance

RadiancePlus

Astra


Annealing Technology Drivers

Improved silicide contact is key to scaling without degrading leakage

45nm

32nm

shrinking increases risk

of leakage

!yield inhibiting

less diffusion required for shallower junctions

Transistor Scaling• Minimized diffusion for shallower junctions• High dopant activation• Thinning nickel silicide contact layers• Avoiding yield-inhibiting piping defects

Future Applications

High-k/Metal Gate• Work function optimization

Memory Yield Enhancements• Minimizing defects in cell array• Applying logic junction engineering

advances to periphery

3D Devices


Phase Transformation to NiSi Anneal

Building a Transistor

Gate Dielectric Gate Stack Etch Implant & USJ Anneal Spacer

Nickel DepositionRecessed Source/Drain

HARP for Pre-Metal Dielectric

Transistor OnIncreased Drive Current

Selective Epi

Advanced anneals are key to scaling Millisecond Soak or Spike



XNi Diffusion Anneal


Trend toward Millisecond AnnealMain Anneal Steps

in FEOL Flow

Pre Gate Anneals

Source-Drain-Poly Implant Activation and Diffusion

Activation Boost

HKMG Work-FunctionOptimization Anneal

Ni Silicidation Diffusion

NiSi Phase Transformation

Logic (65nm) Poly Gate


Logic (32nm) Hi-k Metal Gate

Soak

Spike

Soak

Soak

Soak

Spike

Millisecond

Soak

Soak or Millisecond

Soak

Spike

Millisecond

Millisecond

Soak or Millisecond

Millisecond

USJ

NiS

i

Need higher activation temperature, improved leakage control, shorter dwell time

similar use of millisecond can be made in DRAM periphery


Main Anneal Steps in FEOL Flow

Pre Gate Anneals

Source-Drain-Poly Implant Activation and Diffusion

Activation Boost

HKMG Work-FunctionOptimization Anneal

Ni Silicidation Diffusion

NiSi Phase Transformation



Logic (32nm) Hi-k Metal Gate

Soak

Spike

Soak

Soak

Soak

Spike

Millisecond

Soak

Soak or Millisecond

Soak

Spike

Millisecond

Millisecond

Soak or Millisecond

Millisecond

Trend toward Millisecond Anneal

Nickel silicidation is the most challenging millisecond anneal

Spike to Millisecond Lower spike temperatures reduce activation in ultra-shallow junctions; need diffusion-less boost

Millisecond Delivers :- Thinner effective gate oxide at temperatures >1150ºC- Added source-drain activation without added diffusion- Minimal impact on limited thermal budget

Soak to MillisecondThinner silicides without comprising conductivity or yieldMillisecond Delivers :

- Improved dopant activation at higher temperature- Super-fast ramp up/down without deactivation typical of long exposures at mid-range temps- Fewer leakage-inducing defects through steep temperature profile

USJ

NiS

i


The Ideal Time-Temperature Profile for NiSiKey parameters to consider

Preheat : Must be low enough to avoid uncontrolled diffusion

Jump temp : Must be high enough to enable optimal activation w/o wafer breakage or agglomeration

Dwell time : Must be short to avoid wafer bow and breakage

Above profile is key to enabling optimal nickel silicide

Preheat temperature

Time

Tem

pera

ture

Dwell time

700

800

900

1,000

100

200

300

400

500

600 Jump temperature


NiSi Morphology Improvement

Lowest interface roughness achieved with reduced RTP-1 soak temperature and millisecond RTP-2

T1 SoakT2 Soak

T1-40ºC SoakT2+400ºC Millisecond

RTP-1 anneal:RTP-2 anneal:


Source: IEEE - RTP2009 Conference, Advances on 32nm NiPt Salicide Process, Dr. Chen et al. Co-published by UMC / Applied Materials


NiSi Piping Defects ReductionTEM Top View

Lowest piping defects count achieved with combination of reduced RTP-1 soak temperature and millisecond RTP-2


0

20

40

60

80

100

90%

Piping Defects Count

Nor

mal

ized

Def

ects

(%)

Based on e-beam Bright Voltage Contrast (BVC) count on a pattern wafer post WCMP

T1 SoakT2 Soak

T1-40ºC SoakT2+400ºC Millisecond



Electrical Performance – Ion/Ioff

Several percent drive current gain achieved by enhancing nickel silicidecontact using millisecond annealing with low temperature RTP-1 soak

RTP-1: Soak @ T1-40ºCRTP-2: Millisecond (T2+400ºC)

Ioff

(nA

/m

)

NMOS gain = 4% PMOS gain = 3%

0.5 1.0 1.5 2.0 2.5

Normalized Ion

0.5 1.0 1.5 2.0 2.5

Normalized Ion

100

100

0

10

1

0.1



The Ideal Time-Temperature Profile for NiSiKey parameters to considerPreheat : Must be low enough to avoid uncontrolled diffusion

Jump temp : Must be high enough to enable optimal activation w/o wafer breakage or agglomeration

Dwell time : Must be short to avoid wafer bow and breakage

Delivered by Applied Materials’ Vantage Astra system

Applied Vantage Astra

Flash Competitor

Laser Competitor

250ºC or less

350ºC

400ºC

0.25msec

0.8msec0.4msec

Time

Tem

pera

ture

100

700

800

900

1,000

200

300

400

500

600

Ideal Profile


Applied Vantage® Astra™ DSA System Uniquely powerful silicidation

– Up to 5% greater device speed– Higher yields enabled by up to 15x lower leakage– Less wafer stress

Versatile dynamic millisecond anneal– Broad range of processing conditions– Ambient control– Extendible to high-k/metal gate applications

Compact, reliable, cost-effective– Simple, compact and smart chamber design– Solid-state laser with prolonged lifetime– > 40 WPH per two- chamber system– Compatible with an RTP chamber on same system as hybrid

FAST. SMART. RELIABLE.Simply Better Anneal


Applied Vantage Astra DSA System

FAST. SMART. RELIABLE.


Scan and Overlap Concept

Laser Beam Spot

Scan 2Scan 1

Scan 1Scan 2

Beam Profile View


Three dimensional steady state result for 810nm

Dynamic Surface Annealing (DSA)

scan direction75m

Modifying scan speed determines anneal dwell (exposure) time

750m

6mm

1300ºC

Simulation results on bare silicon

450ºC

Cross section view


Availability

0%

20%

40%

60%

80%

100%

Unscheduled

Scheduled

Uptime


weekly monitoring over 1 year


Productivity: Competitor Comparisons

WAFERS PROCESSED

TIME

Applied Vantage AstraFlash CompetitorLaser Competitor



Applied Vantage Astra DSA System

Simply Better Anneal

FAST– Higher throughput– Shorter dwell time

SMART– Compact design– Broad process window– Ambient control

RELIABLE– Solid-state laser– Reduced wafer stress – Based on the production proven Vantage

Applied Materials Confidential

Applied Vantage Astra DSA System · 2014-08-04 · NiSi Piping Defects Reduction TEM Top View...

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